Modules
	Flags Interrupts Management
	macros to manage the specified RCC Flags and interrupts.

	LSE Configuration

	RCC Extended MCOx Clock Config

Macros
#define	__HAL_RCC_MDMA_CLK_ENABLE()
	Enable or disable the AHB3 peripheral clock.

#define	__HAL_RCC_DMA2D_CLK_ENABLE()

#define	__HAL_RCC_FMC_CLK_ENABLE()

#define	__HAL_RCC_SDMMC1_CLK_ENABLE()

#define	__HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

#define	__HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

#define	__HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

#define	__HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

#define	__HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
	Get the enable or disable status of the AHB3 peripheral clock.

#define	__HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)

#define	__HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)

#define	__HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)

#define	__HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)

#define	__HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)

#define	__HAL_RCC_DMA1_CLK_ENABLE()
	Enable or disable the AHB1 peripheral clock.

#define	__HAL_RCC_DMA2_CLK_ENABLE()

#define	__HAL_RCC_ADC12_CLK_ENABLE()

#define	__HAL_RCC_USB1_OTG_HS_CLK_ENABLE()

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()

#define	__HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

#define	__HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

#define	__HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

#define	__HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
	Get the enable or disable status of the AHB1 peripheral clock.

#define	__HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)

#define	__HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)

#define	__HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)

#define	__HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)

#define	__HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)

#define	__HAL_RCC_DCMI_CLK_ENABLE()
	Enable or disable the AHB2 peripheral clock.

#define	__HAL_RCC_RNG_CLK_ENABLE()

#define	__HAL_RCC_SDMMC2_CLK_ENABLE()

#define	__HAL_RCC_AHBSRAM1_CLK_ENABLE()

#define	__HAL_RCC_AHBSRAM2_CLK_ENABLE()

#define	__HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

#define	__HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

#define	__HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

#define	__HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))

#define	__HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))

#define	__HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
	Get the enable or disable status of the AHB2 peripheral clock.

#define	__HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)

#define	__HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)

#define	__HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)

#define	__HAL_RCC_GPIOA_CLK_ENABLE()
	Enable or disable the AHB4 peripheral clock.

#define	__HAL_RCC_GPIOB_CLK_ENABLE()

#define	__HAL_RCC_GPIOC_CLK_ENABLE()

#define	__HAL_RCC_GPIOD_CLK_ENABLE()

#define	__HAL_RCC_GPIOE_CLK_ENABLE()

#define	__HAL_RCC_GPIOF_CLK_ENABLE()

#define	__HAL_RCC_GPIOG_CLK_ENABLE()

#define	__HAL_RCC_GPIOH_CLK_ENABLE()

#define	__HAL_RCC_GPIOJ_CLK_ENABLE()

#define	__HAL_RCC_GPIOK_CLK_ENABLE()

#define	__HAL_RCC_BDMA_CLK_ENABLE()

#define	__HAL_RCC_BKPRAM_CLK_ENABLE()

#define	__HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

#define	__HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

#define	__HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

#define	__HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

#define	__HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

#define	__HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

#define	__HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

#define	__HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

#define	__HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

#define	__HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

#define	__HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

#define	__HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

#define	__HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
	Get the enable or disable status of the AHB4 peripheral clock.

#define	__HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)

#define	__HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)

#define	__HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)

#define	__HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)

#define	__HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)

#define	__HAL_RCC_WWDG1_CLK_ENABLE()
	Enable or disable the APB3 peripheral clock.

#define	__HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

#define	__HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
	Get the enable or disable status of the APB3 peripheral clock.

#define	__HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)

#define	__HAL_RCC_TIM2_CLK_ENABLE()
	Enable or disable the APB1 peripheral clock.

#define	__HAL_RCC_TIM3_CLK_ENABLE()

#define	__HAL_RCC_TIM4_CLK_ENABLE()

#define	__HAL_RCC_TIM5_CLK_ENABLE()

#define	__HAL_RCC_TIM6_CLK_ENABLE()

#define	__HAL_RCC_TIM7_CLK_ENABLE()

#define	__HAL_RCC_TIM12_CLK_ENABLE()

#define	__HAL_RCC_TIM13_CLK_ENABLE()

#define	__HAL_RCC_TIM14_CLK_ENABLE()

#define	__HAL_RCC_LPTIM1_CLK_ENABLE()

#define	__HAL_RCC_SPI2_CLK_ENABLE()

#define	__HAL_RCC_SPI3_CLK_ENABLE()

#define	__HAL_RCC_SPDIFRX_CLK_ENABLE()

#define	__HAL_RCC_USART2_CLK_ENABLE()

#define	__HAL_RCC_USART3_CLK_ENABLE()

#define	__HAL_RCC_UART4_CLK_ENABLE()

#define	__HAL_RCC_UART5_CLK_ENABLE()

#define	__HAL_RCC_I2C1_CLK_ENABLE()

#define	__HAL_RCC_I2C2_CLK_ENABLE()

#define	__HAL_RCC_I2C3_CLK_ENABLE()

#define	__HAL_RCC_CEC_CLK_ENABLE()

#define	__HAL_RCC_DAC12_CLK_ENABLE()

#define	__HAL_RCC_UART7_CLK_ENABLE()

#define	__HAL_RCC_UART8_CLK_ENABLE()

#define	__HAL_RCC_CRS_CLK_ENABLE()

#define	__HAL_RCC_SWPMI1_CLK_ENABLE()

#define	__HAL_RCC_OPAMP_CLK_ENABLE()

#define	__HAL_RCC_MDIOS_CLK_ENABLE()

#define	__HAL_RCC_FDCAN_CLK_ENABLE()

#define	__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

#define	__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

#define	__HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

#define	__HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

#define	__HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

#define	__HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

#define	__HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

#define	__HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

#define	__HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

#define	__HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

#define	__HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

#define	__HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

#define	__HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

#define	__HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

#define	__HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

#define	__HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

#define	__HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

#define	__HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

#define	__HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

#define	__HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

#define	__HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

#define	__HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

#define	__HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

#define	__HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

#define	__HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

#define	__HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

#define	__HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

#define	__HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

#define	__HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

#define	__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
	Get the enable or disable status of the APB1 peripheral clock.

#define	__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)

#define	__HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)

#define	__HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)

#define	__HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)

#define	__HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)

#define	__HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)

#define	__HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)

#define	__HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)

#define	__HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)

#define	__HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)

#define	__HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)

#define	__HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)

#define	__HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)

#define	__HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)

#define	__HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)

#define	__HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)

#define	__HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)

#define	__HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)

#define	__HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)

#define	__HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)

#define	__HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)

#define	__HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)

#define	__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)

#define	__HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)

#define	__HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)

#define	__HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)

#define	__HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)

#define	__HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)

#define	__HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)

#define	__HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)

#define	__HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)

#define	__HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)

#define	__HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)

#define	__HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)

#define	__HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)

#define	__HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)

#define	__HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)

#define	__HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)

#define	__HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)

#define	__HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)

#define	__HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)

#define	__HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)

#define	__HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)

#define	__HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)

#define	__HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)

#define	__HAL_RCC_TIM1_CLK_ENABLE()
	Enable or disable the APB2 peripheral clock.

#define	__HAL_RCC_TIM8_CLK_ENABLE()

#define	__HAL_RCC_USART1_CLK_ENABLE()

#define	__HAL_RCC_USART6_CLK_ENABLE()

#define	__HAL_RCC_SPI1_CLK_ENABLE()

#define	__HAL_RCC_SPI4_CLK_ENABLE()

#define	__HAL_RCC_TIM15_CLK_ENABLE()

#define	__HAL_RCC_TIM16_CLK_ENABLE()

#define	__HAL_RCC_TIM17_CLK_ENABLE()

#define	__HAL_RCC_SPI5_CLK_ENABLE()

#define	__HAL_RCC_SAI1_CLK_ENABLE()

#define	__HAL_RCC_DFSDM1_CLK_ENABLE()

#define	__HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

#define	__HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

#define	__HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

#define	__HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

#define	__HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

#define	__HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

#define	__HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

#define	__HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

#define	__HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

#define	__HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

#define	__HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

#define	__HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

#define	__HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
	Get the enable or disable status of the APB2 peripheral clock.

#define	__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)

#define	__HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)

#define	__HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)

#define	__HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)

#define	__HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)

#define	__HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)

#define	__HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)

#define	__HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)

#define	__HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)

#define	__HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)

#define	__HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)

#define	__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)

#define	__HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)

#define	__HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)

#define	__HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)

#define	__HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)

#define	__HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)

#define	__HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)

#define	__HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)

#define	__HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)

#define	__HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)

#define	__HAL_RCC_SYSCFG_CLK_ENABLE()
	Enable or disable the APB4 peripheral clock.

#define	__HAL_RCC_LPUART1_CLK_ENABLE()

#define	__HAL_RCC_SPI6_CLK_ENABLE()

#define	__HAL_RCC_I2C4_CLK_ENABLE()

#define	__HAL_RCC_LPTIM2_CLK_ENABLE()

#define	__HAL_RCC_LPTIM3_CLK_ENABLE()

#define	__HAL_RCC_COMP12_CLK_ENABLE()

#define	__HAL_RCC_VREF_CLK_ENABLE()

#define	__HAL_RCC_RTC_CLK_ENABLE()

#define	__HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

#define	__HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

#define	__HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

#define	__HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

#define	__HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

#define	__HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

#define	__HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

#define	__HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

#define	__HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

#define	__HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
	Get the enable or disable status of the APB4 peripheral clock.

#define	__HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)

#define	__HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)

#define	__HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)

#define	__HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)

#define	__HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)

#define	__HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)

#define	__HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)

#define	__HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)

#define	__HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)

#define	__HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)

#define	__HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)

#define	__HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)

#define	__HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)

#define	__HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */
	Enable or disable the AHB3 peripheral reset.

#define	__HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_MDMARST))

#define	__HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_DMA2DRST))

#define	__HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))

#define	__HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_SDMMC1RST))

#define	__HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)

#define	__HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

#define	__HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

#define	__HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

#define	__HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

#define	__HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */
	Force or release the AHB1 peripheral reset.

#define	__HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))

#define	__HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))

#define	__HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ADC12RST))

#define	__HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_USB1OTGHSRST))

#define	__HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)

#define	__HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

#define	__HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

#define	__HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

#define	__HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

#define	__HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */
	Force or release the AHB2 peripheral reset.

#define	__HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))

#define	__HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))

#define	__HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_SDMMC2RST))

#define	__HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)

#define	__HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))

#define	__HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

#define	__HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

#define	__HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */
	Force or release the AHB4 peripheral reset.

#define	__HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOARST)

#define	__HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOBRST)

#define	__HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOCRST)

#define	__HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIODRST)

#define	__HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOERST)

#define	__HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOFRST)

#define	__HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOGRST)

#define	__HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOHRST)

#define	__HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOJRST)

#define	__HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOKRST)

#define	__HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_BDMARST)

#define	__HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)

#define	__HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

#define	__HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

#define	__HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

#define	__HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

#define	__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

#define	__HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

#define	__HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

#define	__HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

#define	__HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

#define	__HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

#define	__HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)

#define	__HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */
	Force or release the APB3 peripheral reset.

#define	__HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)

#define	__HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */
	Force or release the APB1 peripheral reset.

#define	__HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */

#define	__HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM2RST)

#define	__HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM3RST)

#define	__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM4RST)

#define	__HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM5RST)

#define	__HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM6RST)

#define	__HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM7RST)

#define	__HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM12RST)

#define	__HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM13RST)

#define	__HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM14RST)

#define	__HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_LPTIM1RST)

#define	__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPI2RST)

#define	__HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPI3RST)

#define	__HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPDIFRXRST)

#define	__HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_USART2RST)

#define	__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_USART3RST)

#define	__HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART4RST)

#define	__HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART5RST)

#define	__HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C1RST)

#define	__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C2RST)

#define	__HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C3RST)

#define	__HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_CECRST)

#define	__HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_DAC12RST)

#define	__HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART7RST)

#define	__HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART8RST)

#define	__HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_CRSRST)

#define	__HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_SWPMIRST)

#define	__HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_OPAMPRST)

#define	__HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_MDIOSRST)

#define	__HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_FDCANRST)

#define	__HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)

#define	__HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)

#define	__HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

#define	__HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

#define	__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

#define	__HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

#define	__HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

#define	__HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

#define	__HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

#define	__HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

#define	__HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

#define	__HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

#define	__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

#define	__HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

#define	__HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

#define	__HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

#define	__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

#define	__HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

#define	__HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

#define	__HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

#define	__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

#define	__HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

#define	__HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

#define	__HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

#define	__HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

#define	__HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

#define	__HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

#define	__HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

#define	__HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

#define	__HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

#define	__HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

#define	__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */
	Force or release the APB2 peripheral reset.

#define	__HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM1RST)

#define	__HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM8RST)

#define	__HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_USART1RST)

#define	__HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_USART6RST)

#define	__HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI1RST)

#define	__HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI4RST)

#define	__HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM15RST)

#define	__HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM16RST)

#define	__HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM17RST)

#define	__HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI5RST)

#define	__HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SAI1RST)

#define	__HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_DFSDM1RST)

#define	__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)

#define	__HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

#define	__HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

#define	__HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

#define	__HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

#define	__HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

#define	__HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

#define	__HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

#define	__HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

#define	__HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

#define	__HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

#define	__HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

#define	__HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

#define	__HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */
	Force or release the APB4 peripheral reset.

#define	__HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_SYSCFGRST)

#define	__HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPUART1RST)

#define	__HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_SPI6RST)

#define	__HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_I2C4RST)

#define	__HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPTIM2RST)

#define	__HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPTIM3RST)

#define	__HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_COMP12RST)

#define	__HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_VREFRST)

#define	__HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)

#define	__HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

#define	__HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

#define	__HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

#define	__HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

#define	__HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

#define	__HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

#define	__HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

#define	__HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

#define	__HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_MDMALPEN))
	Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DMA2DLPEN))

#define	__HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FLASHLPEN))

#define	__HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))

#define	__HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_SDMMC1LPEN))

#define	__HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DTCM1LPEN))

#define	__HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DTCM2LPEN))

#define	__HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_ITCMLPEN))

#define	__HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_AXISRAM1LPEN))

#define	__HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */

#define	__HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

#define	__HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

#define	__HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

#define	__HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

#define	__HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

#define	__HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

#define	__HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

#define	__HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

#define	__HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))

#define	__HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */

#define	__HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
	Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)

#define	__HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)

#define	__HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)

#define	__HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)

#define	__HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)

#define	__HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)

#define	__HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)

#define	__HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)

#define	__HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)

#define	__HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)

#define	__HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)

#define	__HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)

#define	__HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)

#define	__HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)

#define	__HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)

#define	__HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
	ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))

#define	__HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ADC12LPEN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_USB1OTGHSLPEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

#define	__HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

#define	__HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

#define	__HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

#define	__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
	Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)

#define	__HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)

#define	__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)

#define	__HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)

#define	__HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)

#define	__HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
	ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))

#define	__HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_SDMMC2LPEN))

#define	__HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AHBSRAM1LPEN))

#define	__HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AHBSRAM2LPEN))

#define	__HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

#define	__HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

#define	__HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

#define	__HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))

#define	__HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))

#define	__HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
	Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)

#define	__HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)

#define	__HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)

#define	__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOALPEN)
	ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOBLPEN)

#define	__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOCLPEN)

#define	__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIODLPEN)

#define	__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOELPEN)

#define	__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOFLPEN)

#define	__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOGLPEN)

#define	__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOHLPEN)

#define	__HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOJLPEN)

#define	__HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOKLPEN)

#define	__HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_BDMALPEN)

#define	__HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_BKPRAMLPEN)

#define	__HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR \|= (RCC_AHB4LPENR_D3SRAM1LPEN))

#define	__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

#define	__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

#define	__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

#define	__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

#define	__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

#define	__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

#define	__HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

#define	__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

#define	__HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

#define	__HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

#define	__HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

#define	__HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

#define	__HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

#define	__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
	Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)

#define	__HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)

#define	__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)

#define	__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)

#define	__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)

#define	__HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)

#define	__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)

#define	__HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) \|= (RCC_APB3LPENR_WWDG1LPEN)
	ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

#define	__HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
	Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)

#define	__HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM2LPEN)
	ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM3LPEN)

#define	__HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM4LPEN)

#define	__HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM5LPEN)

#define	__HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM6LPEN)

#define	__HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM7LPEN)

#define	__HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM12LPEN)

#define	__HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM13LPEN)

#define	__HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM14LPEN)

#define	__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_LPTIM1LPEN)

#define	__HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPI2LPEN)

#define	__HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPI3LPEN)

#define	__HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPDIFRXLPEN)

#define	__HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_USART2LPEN)

#define	__HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_USART3LPEN)

#define	__HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART4LPEN)

#define	__HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART5LPEN)

#define	__HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C1LPEN)

#define	__HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C2LPEN)

#define	__HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C3LPEN)

#define	__HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_CECLPEN)

#define	__HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_DAC12LPEN)

#define	__HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART7LPEN)

#define	__HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART8LPEN)

#define	__HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_CRSLPEN)

#define	__HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_SWPMILPEN)

#define	__HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_OPAMPLPEN)

#define	__HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_MDIOSLPEN)

#define	__HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_FDCANLPEN)

#define	__HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

#define	__HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

#define	__HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

#define	__HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

#define	__HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

#define	__HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

#define	__HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

#define	__HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

#define	__HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

#define	__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

#define	__HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

#define	__HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

#define	__HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

#define	__HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

#define	__HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

#define	__HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

#define	__HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

#define	__HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

#define	__HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

#define	__HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

#define	__HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

#define	__HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

#define	__HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

#define	__HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

#define	__HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

#define	__HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

#define	__HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

#define	__HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

#define	__HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

#define	__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
	Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)

#define	__HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)

#define	__HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)

#define	__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)

#define	__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)

#define	__HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)

#define	__HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)

#define	__HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)

#define	__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)

#define	__HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)

#define	__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)

#define	__HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)

#define	__HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)

#define	__HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)

#define	__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)

#define	__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)

#define	__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)

#define	__HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)

#define	__HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)

#define	__HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)

#define	__HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)

#define	__HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)

#define	__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)

#define	__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)

#define	__HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)

#define	__HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)

#define	__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)

#define	__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)

#define	__HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)

#define	__HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)

#define	__HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)

#define	__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)

#define	__HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)

#define	__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)

#define	__HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)

#define	__HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)

#define	__HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)

#define	__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)

#define	__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)

#define	__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)

#define	__HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)

#define	__HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)

#define	__HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)

#define	__HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)

#define	__HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)

#define	__HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM1LPEN)
	ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM8LPEN)

#define	__HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_USART1LPEN)

#define	__HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_USART6LPEN)

#define	__HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI1LPEN)

#define	__HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI4LPEN)

#define	__HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM15LPEN)

#define	__HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM16LPEN)

#define	__HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM17LPEN)

#define	__HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI5LPEN)

#define	__HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SAI1LPEN)

#define	__HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_DFSDM1LPEN)

#define	__HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

#define	__HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

#define	__HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

#define	__HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

#define	__HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

#define	__HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

#define	__HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

#define	__HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

#define	__HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

#define	__HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

#define	__HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

#define	__HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

#define	__HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
	Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)

#define	__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)

#define	__HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)

#define	__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)

#define	__HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)

#define	__HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)

#define	__HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)

#define	__HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)

#define	__HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)

#define	__HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)

#define	__HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)

#define	__HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)

#define	__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)

#define	__HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)

#define	__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)

#define	__HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)

#define	__HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)

#define	__HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)

#define	__HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)

#define	__HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)

#define	__HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)

#define	__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_SYSCFGLPEN)
	ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPUART1LPEN)

#define	__HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_SPI6LPEN)

#define	__HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_I2C4LPEN)

#define	__HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPTIM2LPEN)

#define	__HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPTIM3LPEN)

#define	__HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_COMP12LPEN)

#define	__HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_VREFLPEN)

#define	__HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_RTCAPBLPEN)

#define	__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

#define	__HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

#define	__HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

#define	__HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

#define	__HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

#define	__HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

#define	__HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

#define	__HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

#define	__HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

#define	__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
	Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)

#define	__HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)

#define	__HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)

#define	__HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)

#define	__HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)

#define	__HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)

#define	__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)

#define	__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)

#define	__HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)

#define	__HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)

#define	__HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)

#define	__HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)

#define	__HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)

#define	__HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIV , (uint32_t)(__STATE__))
	Enable or disable peripheral bus clock when D3 domain is in DRUN.

#define	__HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
	Macro to get the HSI divider.

#define	__HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
	Macros to enable or disable the Internal High Speed oscillator (HSI).

#define	__HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)

#define	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
	Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

#define	__HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
	Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.

#define	__HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

#define	__HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
	Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

#define	__HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

#define	__HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
	Macros to enable or disable the Internal oscillator (CSI).

#define	__HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)

#define	__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)
	Macro Adjusts the Internal oscillator (CSI) calibration value.

#define	__HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
	Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

#define	__HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

#define	__HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
	Macros to enable or disable the Internal Low Speed oscillator (LSI).

#define	__HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

#define	__HAL_RCC_HSE_CONFIG(__STATE__)
	Macro to configure the External High Speed oscillator (HSE).

#define	__HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
	Macros to enable or disable the the RTC clock.

#define	__HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

#define	__HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
	Macros to configure the RTC clock (RTCCLK).

#define	__HAL_RCC_RTC_CONFIG(__RTCCLKSource__)

#define	__HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

#define	__HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
	Macros to force or release the Backup domain reset.

#define	__HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

#define	__HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
	Macros to enable or disable the main PLL.

#define	__HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

#define	__HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
	Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

#define	__HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

#define	__HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
	Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.

#define	__HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
	Macro to configures the main PLL clock source, multiplication and division factors.

#define	__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
	Macro to configure the PLLs clock source.

#define	__HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
	Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.

#define	__HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
	Macro to select the PLL1 reference frequency range.

#define	__HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
	Macro to select the PLL1 reference frequency range.

#define	__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
	Macro to get the clock source used as system clock.

#define	__HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
	Macro to configure the system clock source.

#define	__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
	Macro to get the oscillator used as PLL clock source.

#define	__HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
	Macro to configure the External Low Speed oscillator (LSE) drive capability.

#define	__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
	Macro to configure the wake up from stop clock.

#define	__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
	Macro to configure the Kernel wake up from stop clock.

#define	RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

Detailed Description

Macro Definition Documentation

◆ __HAL_RCC_ADC12_CLK_ENABLE

#define __HAL_RCC_ADC12_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_AHBSRAM1_CLK_ENABLE

#define __HAL_RCC_AHBSRAM1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_AHBSRAM2_CLK_ENABLE

#define __HAL_RCC_AHBSRAM2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_BACKUPRESET_FORCE

#define __HAL_RCC_BACKUPRESET_FORCE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

Macros to force or release the Backup domain reset.

Note: This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_BDCR register.; The BKPSRAM is not affected by this reset.

◆ __HAL_RCC_BDMA_CLK_ENABLE

#define __HAL_RCC_BDMA_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_BKPRAM_CLK_ENABLE

#define __HAL_RCC_BKPRAM_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_CEC_CLK_ENABLE

#define __HAL_RCC_CEC_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_COMP12_CLK_ENABLE

#define __HAL_RCC_COMP12_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_CRS_CLK_ENABLE

#define __HAL_RCC_CRS_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST

#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST ( __CSICalibrationValue__ )

Value:

           do {                                                                                                                          \
               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \
               } while(0)

Macro Adjusts the Internal oscillator (CSI) calibration value.

Note: The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal CSI RC.

Parameters

__CSICalibrationValue__ specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.

◆ __HAL_RCC_CSI_ENABLE

#define __HAL_RCC_CSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSION)

Macros to enable or disable the Internal oscillator (CSI).

Note: The CSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; CSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the CSI.; After enabling the CSI, the application software should wait on CSIRDY flag to be set indicating that CSI clock is stable and can be used as system clock source.; When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator clock cycles.

◆ __HAL_RCC_CSISTOP_ENABLE

#define __HAL_RCC_CSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_CSIKERON)

Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

Note: Keeping the CSI ON in STOP mode allows to avoid slowing down the communication speed because of the CSI start-up time.; The enable of this function has not effect on the CSION bit. This parameter can be: ENABLE or DISABLE.

Return values

None

◆ __HAL_RCC_DAC12_CLK_ENABLE

#define __HAL_RCC_DAC12_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_DCMI_CLK_ENABLE

#define __HAL_RCC_DCMI_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB2 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_DCMI_CLK_SLEEP_ENABLE

#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE ( ) (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_DCMI_IS_CLK_ENABLED

#define __HAL_RCC_DCMI_IS_CLK_ENABLED ( ) ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)

Get the enable or disable status of the AHB2 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)

Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_DFSDM1_CLK_ENABLE

#define __HAL_RCC_DFSDM1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_DMA1_CLK_ENABLE

#define __HAL_RCC_DMA1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB1 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_DMA1_CLK_SLEEP_ENABLE

#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE ( ) (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_DMA1_IS_CLK_ENABLED

#define __HAL_RCC_DMA1_IS_CLK_ENABLED ( ) ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)

Get the enable or disable status of the AHB1 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)

Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_DMA2_CLK_ENABLE

#define __HAL_RCC_DMA2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_DMA2D_CLK_ENABLE

#define __HAL_RCC_DMA2D_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_FDCAN_CLK_ENABLE

#define __HAL_RCC_FDCAN_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_FMC_CLK_ENABLE

#define __HAL_RCC_FMC_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GET_HSI_DIVIDER

#define __HAL_RCC_GET_HSI_DIVIDER ( ) ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))

Macro to get the HSI divider.

Return values

The	HSI divider. The returned value can be one of the following: RCC_CR_HSIDIV_1 HSI oscillator divided by 1 (default after reset) RCC_CR_HSIDIV_2 HSI oscillator divided by 2 RCC_CR_HSIDIV_4 HSI oscillator divided by 4 RCC_CR_HSIDIV_8 HSI oscillator divided by 8

◆ __HAL_RCC_GET_PLL_OSCSOURCE

#define __HAL_RCC_GET_PLL_OSCSOURCE ( ) ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))

Macro to get the oscillator used as PLL clock source.

Return values

The

oscillator used as PLL clock source. The returned value can be one of the following:

RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.
RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

◆ __HAL_RCC_GET_SYSCLK_SOURCE

#define __HAL_RCC_GET_SYSCLK_SOURCE ( ) ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

Macro to get the clock source used as system clock.

Return values

The	clock source used as system clock. The returned value can be one of the following: RCC_CFGR_SWS_CSI: CSI used as system clock. RCC_CFGR_SWS_HSI: HSI used as system clock. RCC_CFGR_SWS_HSE: HSE used as system clock. RCC_CFGR_SWS_PLL: PLL used as system clock.

◆ __HAL_RCC_GPIOA_CLK_ENABLE

#define __HAL_RCC_GPIOA_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB4 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE

#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE ( ) (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_GPIOA_IS_CLK_ENABLED

#define __HAL_RCC_GPIOA_IS_CLK_ENABLED ( ) ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)

Get the enable or disable status of the AHB4 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)

Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_GPIOB_CLK_ENABLE

#define __HAL_RCC_GPIOB_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOC_CLK_ENABLE

#define __HAL_RCC_GPIOC_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOD_CLK_ENABLE

#define __HAL_RCC_GPIOD_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOE_CLK_ENABLE

#define __HAL_RCC_GPIOE_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOF_CLK_ENABLE

#define __HAL_RCC_GPIOF_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOG_CLK_ENABLE

#define __HAL_RCC_GPIOG_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOH_CLK_ENABLE

#define __HAL_RCC_GPIOH_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOJ_CLK_ENABLE

#define __HAL_RCC_GPIOJ_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_GPIOK_CLK_ENABLE

#define __HAL_RCC_GPIOK_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_HSE_CONFIG

#define __HAL_RCC_HSE_CONFIG ( __STATE__ )

Value:

                    do {                                        \
                      if ((__STATE__) == RCC_HSE_ON)            \
                      {                                         \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
                      }                                         \
                      else if ((__STATE__) == RCC_HSE_OFF)      \
                      {                                         \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
                      }                                         \
                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
                      {                                         \
                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
                      }                                         \
                      else                                      \
                      {                                         \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
                      }                                         \
                    } while(0)

Macro to configure the External High Speed oscillator (HSE).

Note: After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the PLL and/or system clock.; HSE state can not be changed if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).; The HSE is stopped by hardware when entering STOP and STANDBY modes.; This function reset the CSSON bit, so if the clock security system(CSS) was previously enabled you have to enable it again after calling this function.

Parameters

__STATE__

specifies the new state of the HSE. This parameter can be one of the following values:

RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles.
RCC_HSE_ON: turn ON the HSE oscillator.
RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*)

(*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

◆ __HAL_RCC_HSI48_ENABLE

#define __HAL_RCC_HSI48_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSI48ON);

Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

Note: After enabling the HSI48, the application software should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be used to clock the USB.; The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

◆ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST

#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST ( __HSICalibrationValue__ ) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);

Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

Note: The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

Parameters

__HSICalibrationValue__ specifies the calibration trimming value. This parameter must be a number between 0 and 0x7F (3F for Rev Y device).

◆ __HAL_RCC_HSI_CONFIG

#define __HAL_RCC_HSI_CONFIG ( __STATE__ ) MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))

Enable or disable peripheral bus clock when D3 domain is in DRUN.

Note: After reset (default config), peripheral clock is disabled when CPU is in CSTOP

Macro to enable or disable the Internal High Speed oscillator (HSI).

Note: After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.; HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.; The HSI is stopped by hardware when entering STOP and STANDBY modes.

Parameters

__STATE__

specifies the new state of the HSI. This parameter can be one of the following values:

RCC_HSI_OFF turn OFF the HSI oscillator
RCC_HSI_ON turn ON the HSI oscillator
RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)
RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2
RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4
RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8

Note: When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

◆ __HAL_RCC_HSI_ENABLE

#define __HAL_RCC_HSI_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSION)

Macros to enable or disable the Internal High Speed oscillator (HSI).

Note: The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after start-up from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).; HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.; After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source. This parameter can be: ENABLE or DISABLE.; When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

◆ __HAL_RCC_HSISTOP_ENABLE

#define __HAL_RCC_HSISTOP_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_HSIKERON)

Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.

Note: Keeping the HSI ON in STOP mode allows to avoid slowing down the communication speed because of the HSI start-up time.; The enable of this function has not effect on the HSION bit. This parameter can be: ENABLE or DISABLE.

Return values

None

◆ __HAL_RCC_I2C1_CLK_ENABLE

#define __HAL_RCC_I2C1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_I2C2_CLK_ENABLE

#define __HAL_RCC_I2C2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_I2C3_CLK_ENABLE

#define __HAL_RCC_I2C3_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_I2C4_CLK_ENABLE

#define __HAL_RCC_I2C4_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG

#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG ( __RCC_STOPKERWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))

Macro to configure the Kernel wake up from stop clock.

Parameters

__RCC_STOPKERWUCLK__

specifies the Kernel clock source used after wake up from stop This parameter can be one of the following values:

RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source
RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source

Return values

None

◆ __HAL_RCC_LPTIM1_CLK_ENABLE

#define __HAL_RCC_LPTIM1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_LPTIM2_CLK_ENABLE

#define __HAL_RCC_LPTIM2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_LPTIM3_CLK_ENABLE

#define __HAL_RCC_LPTIM3_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_LPUART1_CLK_ENABLE

#define __HAL_RCC_LPUART1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_LSEDRIVE_CONFIG

#define __HAL_RCC_LSEDRIVE_CONFIG ( __LSEDRIVE__ ) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));

Macro to configure the External Low Speed oscillator (LSE) drive capability.

Note: As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using HAL_PWR_EnableBkUpAccess() function before to configure the LSE (to be done once after reset).; On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.

Parameters

__LSEDRIVE__

specifies the new state of the LSE drive capability. This parameter can be one of the following values:

RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.

Return values

None

◆ __HAL_RCC_LSI_ENABLE

#define __HAL_RCC_LSI_ENABLE ( ) SET_BIT(RCC->CSR, RCC_CSR_LSION)

Macros to enable or disable the Internal Low Speed oscillator (LSI).

Note: After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.; LSI can not be disabled if the IWDG is running.; When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

◆ __HAL_RCC_MDIOS_CLK_ENABLE

#define __HAL_RCC_MDIOS_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_MDMA_CLK_ENABLE

#define __HAL_RCC_MDMA_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the AHB3 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_MDMA_CLK_SLEEP_ENABLE

#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE ( ) (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_MDMA_IS_CLK_ENABLED

#define __HAL_RCC_MDMA_IS_CLK_ENABLED ( ) ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)

Get the enable or disable status of the AHB3 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED ( ) ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)

Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_OPAMP_CLK_ENABLE

#define __HAL_RCC_OPAMP_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_PLL_CONFIG

#define __HAL_RCC_PLL_CONFIG	(	__RCC_PLLSOURCE__,
		__PLLM1__,
		__PLLN1__,
		__PLLP1__,
		__PLLQ1__,
		__PLLR1__
	)

Value:

                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \
                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \
                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \
                    } while(0)

Macro to configures the main PLL clock source, multiplication and division factors.

Note: This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSOURCE__

specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note: This clock source (RCC_PLLSource) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .

Parameters

__PLLM1__ specifies the division factor for PLL VCO input clock This parameter must be a number between 1 and 63.

Note: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.

Parameters

__PLLN1__ specifies the multiplication factor for PLL VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).

Note: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

Parameters

__PLLP1__	specifies the division factor for system clock. This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed)
__PLLQ1__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLLR1__	specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128

Note: To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL1P, PLL1Q or PLL1R parameters.

Return values

None

(*) : For stm32h7a3xx and stm32h7b3xx family lines. (**): For stm32h72xxx and stm32h73xxx family lines.

◆ __HAL_RCC_PLL_ENABLE

#define __HAL_RCC_PLL_ENABLE ( ) SET_BIT(RCC->CR, RCC_CR_PLL1ON)

Macros to enable or disable the main PLL.

Note: After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.; The main PLL can not be disabled if it is used as system clock source; The main PLL is disabled by hardware when entering STOP and STANDBY modes.

◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG

#define __HAL_RCC_PLL_PLLSOURCE_CONFIG ( __PLLSOURCE__ ) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))

Macro to configure the PLLs clock source.

Note: This function must be used only when all PLLs are disabled.

Parameters

__PLLSOURCE__

specifies the PLLs entry clock source. This parameter can be one of the following values:

RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

◆ __HAL_RCC_PLL_VCIRANGE

#define __HAL_RCC_PLL_VCIRANGE ( __RCC_PLL1VCIRange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))

Macro to select the PLL1 reference frequency range.

Parameters

__RCC_PLL1VCIRange__

specifies the PLL1 input frequency range This parameter can be one of the following values:

RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz
RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz
RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz
RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz

Return values

None

◆ __HAL_RCC_PLL_VCORANGE

#define __HAL_RCC_PLL_VCORANGE ( __RCC_PLL1VCORange__ ) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))

Macro to select the PLL1 reference frequency range.

Parameters

__RCC_PLL1VCORange__

specifies the PLL1 input frequency range This parameter can be one of the following values:

RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values

None

◆ __HAL_RCC_PLLCLKOUT_ENABLE

#define __HAL_RCC_PLLCLKOUT_ENABLE ( __RCC_PLL1ClockOut__ ) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

Note: Enabling/disabling those Clocks can be done only when the PLL is disabled. This is mainly used to save Power. (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).

Parameters

__RCC_PLL1ClockOut__

specifies the PLL clock to be outputted This parameter can be one of the following values:

RCC_PLL1_DIVP: This clock is used to generate system clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)

(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.

Return values

None

◆ __HAL_RCC_PLLFRACN_CONFIG

#define __HAL_RCC_PLLFRACN_CONFIG ( __RCC_PLL1FRACN__ ) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)

Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.

Note: These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO

Parameters

__RCC_PLL1FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191

Note: Warning: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0 150 to 420 MHz if PLL1VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values

None

◆ __HAL_RCC_PLLFRACN_ENABLE

#define __HAL_RCC_PLLFRACN_ENABLE ( ) SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.

Note: Enabling/disabling Fractional Part can be any time without the need to stop the PLL1

Return values

None

◆ __HAL_RCC_RNG_CLK_ENABLE

#define __HAL_RCC_RNG_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_RTC_CLK_ENABLE

#define __HAL_RCC_RTC_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_RTC_CLKPRESCALER

#define __HAL_RCC_RTC_CLKPRESCALER ( __RTCCLKSource__ )

Value:

(((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \

MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

Macros to configure the RTC clock (RTCCLK).

Note: As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using the Power Backup Access macro before to configure the RTC clock source (to be done once after reset).; Once the RTC clock is configured it can't be changed unless the Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by a Power On Reset (POR).

Parameters

__RTCCLKSource__

specifies the RTC clock source. This parameter can be one of the following values:

RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected as RTC clock, where x:[2,31]

Note: If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.; The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).

◆ __HAL_RCC_RTC_CONFIG

#define __HAL_RCC_RTC_CONFIG ( __RTCCLKSource__ )

Value:

                                                    do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
                                                   } while (0)

◆ __HAL_RCC_RTC_ENABLE

#define __HAL_RCC_RTC_ENABLE ( ) SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

Macros to enable or disable the the RTC clock.

Note: These macros must be used only after the RTC clock source was selected.

◆ __HAL_RCC_SAI1_CLK_ENABLE

#define __HAL_RCC_SAI1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SDMMC1_CLK_ENABLE

#define __HAL_RCC_SDMMC1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SDMMC2_CLK_ENABLE

#define __HAL_RCC_SDMMC2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPDIFRX_CLK_ENABLE

#define __HAL_RCC_SPDIFRX_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI1_CLK_ENABLE

#define __HAL_RCC_SPI1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI2_CLK_ENABLE

#define __HAL_RCC_SPI2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI3_CLK_ENABLE

#define __HAL_RCC_SPI3_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI4_CLK_ENABLE

#define __HAL_RCC_SPI4_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI5_CLK_ENABLE

#define __HAL_RCC_SPI5_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SPI6_CLK_ENABLE

#define __HAL_RCC_SPI6_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SWPMI1_CLK_ENABLE

#define __HAL_RCC_SWPMI1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_SYSCFG_CLK_ENABLE

#define __HAL_RCC_SYSCFG_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB4 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE

#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE ( ) (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_SYSCFG_IS_CLK_ENABLED

#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED ( ) ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)

Get the enable or disable status of the APB4 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)

Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_SYSCLK_CONFIG

#define __HAL_RCC_SYSCLK_CONFIG ( __RCC_SYSCLKSOURCE__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

Macro to configure the system clock source.

Parameters

__RCC_SYSCLKSOURCE__

specifies the system clock source. This parameter can be one of the following values:

RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.
RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

◆ __HAL_RCC_TIM12_CLK_ENABLE

#define __HAL_RCC_TIM12_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM13_CLK_ENABLE

#define __HAL_RCC_TIM13_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM14_CLK_ENABLE

#define __HAL_RCC_TIM14_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM15_CLK_ENABLE

#define __HAL_RCC_TIM15_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM16_CLK_ENABLE

#define __HAL_RCC_TIM16_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM17_CLK_ENABLE

#define __HAL_RCC_TIM17_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM1_CLK_ENABLE

#define __HAL_RCC_TIM1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB2 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM1_CLK_SLEEP_ENABLE

#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE ( ) (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_TIM1_IS_CLK_ENABLED

#define __HAL_RCC_TIM1_IS_CLK_ENABLED ( ) ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)

Get the enable or disable status of the APB2 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)

Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_TIM2_CLK_ENABLE

#define __HAL_RCC_TIM2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB1 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM2_CLK_SLEEP_ENABLE

#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE ( ) (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_TIM2_IS_CLK_ENABLED

#define __HAL_RCC_TIM2_IS_CLK_ENABLED ( ) ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)

Get the enable or disable status of the APB1 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)

Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

◆ __HAL_RCC_TIM3_CLK_ENABLE

#define __HAL_RCC_TIM3_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM4_CLK_ENABLE

#define __HAL_RCC_TIM4_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM5_CLK_ENABLE

#define __HAL_RCC_TIM5_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM6_CLK_ENABLE

#define __HAL_RCC_TIM6_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM7_CLK_ENABLE

#define __HAL_RCC_TIM7_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_TIM8_CLK_ENABLE

#define __HAL_RCC_TIM8_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_UART4_CLK_ENABLE

#define __HAL_RCC_UART4_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_UART5_CLK_ENABLE

#define __HAL_RCC_UART5_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_UART7_CLK_ENABLE

#define __HAL_RCC_UART7_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_UART8_CLK_ENABLE

#define __HAL_RCC_UART8_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USART1_CLK_ENABLE

#define __HAL_RCC_USART1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USART2_CLK_ENABLE

#define __HAL_RCC_USART2_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USART3_CLK_ENABLE

#define __HAL_RCC_USART3_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USART6_CLK_ENABLE

#define __HAL_RCC_USART6_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USB1_OTG_HS_CLK_ENABLE

#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE

#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_VREF_CLK_ENABLE

#define __HAL_RCC_VREF_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

◆ __HAL_RCC_WAKEUPSTOP_CLK_CONFIG

#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG ( __RCC_STOPWUCLK__ ) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))

Macro to configure the wake up from stop clock.

Parameters

__RCC_STOPWUCLK__

specifies the clock source used after wake up from stop This parameter can be one of the following values:

RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source
RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source

Return values

None

◆ __HAL_RCC_WWDG1_CLK_ENABLE

#define __HAL_RCC_WWDG1_CLK_ENABLE ( )

Value:

                                        do { \
                                        __IO uint32_t tmpreg; \
                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        /* Delay after an RCC peripheral clock enabling */ \
                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\
                                        UNUSED(tmpreg); \
                                       } while(0)

Enable or disable the APB3 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE

#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE ( ) (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.; By default, all peripheral clocks are ENABLEd during SLEEP mode.

◆ __HAL_RCC_WWDG1_IS_CLK_ENABLED

#define __HAL_RCC_WWDG1_IS_CLK_ENABLED ( ) ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)

Get the enable or disable status of the APB3 peripheral clock.

Note: After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

◆ __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED

#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED ( ) ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)

Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

Note: Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.; After wakeup from SLEEP mode, the peripheral clock is enabled again.; By default, all peripheral clocks are enabled during SLEEP mode.

Modules

Macros

Detailed Description

Macro Definition Documentation

◆ __HAL_RCC_ADC12_CLK_ENABLE

◆ __HAL_RCC_AHBSRAM1_CLK_ENABLE

◆ __HAL_RCC_AHBSRAM2_CLK_ENABLE

◆ __HAL_RCC_BACKUPRESET_FORCE

◆ __HAL_RCC_BDMA_CLK_ENABLE

◆ __HAL_RCC_BKPRAM_CLK_ENABLE

◆ __HAL_RCC_CEC_CLK_ENABLE

◆ __HAL_RCC_COMP12_CLK_ENABLE

◆ __HAL_RCC_CRS_CLK_ENABLE

◆ __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST

◆ __HAL_RCC_CSI_ENABLE

◆ __HAL_RCC_CSISTOP_ENABLE

◆ __HAL_RCC_DAC12_CLK_ENABLE

◆ __HAL_RCC_DCMI_CLK_ENABLE

◆ __HAL_RCC_DCMI_CLK_SLEEP_ENABLE

◆ __HAL_RCC_DCMI_IS_CLK_ENABLED

◆ __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED

◆ __HAL_RCC_DFSDM1_CLK_ENABLE

◆ __HAL_RCC_DMA1_CLK_ENABLE

◆ __HAL_RCC_DMA1_CLK_SLEEP_ENABLE

◆ __HAL_RCC_DMA1_IS_CLK_ENABLED

◆ __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED

◆ __HAL_RCC_DMA2_CLK_ENABLE

◆ __HAL_RCC_DMA2D_CLK_ENABLE

◆ __HAL_RCC_FDCAN_CLK_ENABLE

◆ __HAL_RCC_FMC_CLK_ENABLE

◆ __HAL_RCC_GET_HSI_DIVIDER

◆ __HAL_RCC_GET_PLL_OSCSOURCE

◆ __HAL_RCC_GET_SYSCLK_SOURCE

◆ __HAL_RCC_GPIOA_CLK_ENABLE

◆ __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE

◆ __HAL_RCC_GPIOA_IS_CLK_ENABLED

◆ __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED

◆ __HAL_RCC_GPIOB_CLK_ENABLE

◆ __HAL_RCC_GPIOC_CLK_ENABLE

◆ __HAL_RCC_GPIOD_CLK_ENABLE

◆ __HAL_RCC_GPIOE_CLK_ENABLE

◆ __HAL_RCC_GPIOF_CLK_ENABLE

◆ __HAL_RCC_GPIOG_CLK_ENABLE

◆ __HAL_RCC_GPIOH_CLK_ENABLE

◆ __HAL_RCC_GPIOJ_CLK_ENABLE

◆ __HAL_RCC_GPIOK_CLK_ENABLE

◆ __HAL_RCC_HSE_CONFIG

◆ __HAL_RCC_HSI48_ENABLE

◆ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST

◆ __HAL_RCC_HSI_CONFIG

◆ __HAL_RCC_HSI_ENABLE

◆ __HAL_RCC_HSISTOP_ENABLE

◆ __HAL_RCC_I2C1_CLK_ENABLE

◆ __HAL_RCC_I2C2_CLK_ENABLE

◆ __HAL_RCC_I2C3_CLK_ENABLE

◆ __HAL_RCC_I2C4_CLK_ENABLE

◆ __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG

◆ __HAL_RCC_LPTIM1_CLK_ENABLE

◆ __HAL_RCC_LPTIM2_CLK_ENABLE

◆ __HAL_RCC_LPTIM3_CLK_ENABLE

◆ __HAL_RCC_LPUART1_CLK_ENABLE

◆ __HAL_RCC_LSEDRIVE_CONFIG

◆ __HAL_RCC_LSI_ENABLE

◆ __HAL_RCC_MDIOS_CLK_ENABLE

◆ __HAL_RCC_MDMA_CLK_ENABLE

◆ __HAL_RCC_MDMA_CLK_SLEEP_ENABLE

◆ __HAL_RCC_MDMA_IS_CLK_ENABLED

◆ __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED

◆ __HAL_RCC_OPAMP_CLK_ENABLE

◆ __HAL_RCC_PLL_CONFIG

◆ __HAL_RCC_PLL_ENABLE

◆ __HAL_RCC_PLL_PLLSOURCE_CONFIG

◆ __HAL_RCC_PLL_VCIRANGE

◆ __HAL_RCC_PLL_VCORANGE

◆ __HAL_RCC_PLLCLKOUT_ENABLE

◆ __HAL_RCC_PLLFRACN_CONFIG

◆ __HAL_RCC_PLLFRACN_ENABLE

◆ __HAL_RCC_RNG_CLK_ENABLE

◆ __HAL_RCC_RTC_CLK_ENABLE

◆ __HAL_RCC_RTC_CLKPRESCALER