RTEMS 6.1-rc5
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stm32h7xx_hal_i2s.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_I2S_H
21#define STM32H7xx_HAL_I2S_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
47typedef struct
48{
49 uint32_t Mode;
52 uint32_t Standard;
55 uint32_t DataFormat;
58 uint32_t MCLKOutput;
61 uint32_t AudioFreq;
64 uint32_t CPOL;
67 uint32_t FirstBit;
70 uint32_t WSInversion;
73 uint32_t Data24BitAlignment;
76 uint32_t MasterKeepIOState;
79} I2S_InitTypeDef;
80
84typedef enum
85{
86 HAL_I2S_STATE_RESET = 0x00UL,
87 HAL_I2S_STATE_READY = 0x01UL,
88 HAL_I2S_STATE_BUSY = 0x02UL,
89 HAL_I2S_STATE_BUSY_TX = 0x03UL,
90 HAL_I2S_STATE_BUSY_RX = 0x04UL,
91 HAL_I2S_STATE_BUSY_TX_RX = 0x05UL,
92 HAL_I2S_STATE_TIMEOUT = 0x06UL,
93 HAL_I2S_STATE_ERROR = 0x07UL
94} HAL_I2S_StateTypeDef;
95
99typedef struct __I2S_HandleTypeDef
100{
101 SPI_TypeDef *Instance;
103 I2S_InitTypeDef Init;
105 const uint16_t *pTxBuffPtr;
107 __IO uint16_t TxXferSize;
109 __IO uint16_t TxXferCount;
111 uint16_t *pRxBuffPtr;
113 __IO uint16_t RxXferSize;
115 __IO uint16_t RxXferCount;
122 void (*RxISR)(struct __I2S_HandleTypeDef *hi2s);
124 void (*TxISR)(struct __I2S_HandleTypeDef *hi2s);
126 DMA_HandleTypeDef *hdmatx;
128 DMA_HandleTypeDef *hdmarx;
130 __IO HAL_LockTypeDef Lock;
132 __IO HAL_I2S_StateTypeDef State;
134 __IO uint32_t ErrorCode;
137#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
138 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
139 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
140 void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
141 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
142 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
143 void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);
144 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);
145 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);
146 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);
148#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
149} I2S_HandleTypeDef;
150
151#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
156typedef enum
157{
158 HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL,
159 HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL,
160 HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02UL,
161 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL,
162 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL,
163 HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL,
164 HAL_I2S_ERROR_CB_ID = 0x06UL,
165 HAL_I2S_MSPINIT_CB_ID = 0x07UL,
166 HAL_I2S_MSPDEINIT_CB_ID = 0x08UL
168} HAL_I2S_CallbackIDTypeDef;
169
173typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s);
175#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
180/* Exported constants --------------------------------------------------------*/
189#define HAL_I2S_ERROR_NONE (0x00000000UL)
190#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL)
191#define HAL_I2S_ERROR_OVR (0x00000002UL)
192#define HAL_I2S_ERROR_UDR (0x00000004UL)
193#define HAL_I2S_ERROR_DMA (0x00000008UL)
194#define HAL_I2S_ERROR_PRESCALER (0x00000010UL)
195#define HAL_I2S_ERROR_FRE (0x00000020UL)
196#define HAL_I2S_ERROR_NO_OGT (0x00000040UL)
197#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000080UL)
198#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
199#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100UL)
200#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
209#define I2S_MODE_SLAVE_TX (0x00000000UL)
210#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
211#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
212#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
213#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
214#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
223#define I2S_STANDARD_PHILIPS (0x00000000UL)
224#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
225#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
226#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
227#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
236#define I2S_DATAFORMAT_16B (0x00000000UL)
237#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
238#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
239#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
248#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
249#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
258#define I2S_AUDIOFREQ_192K (192000UL)
259#define I2S_AUDIOFREQ_96K (96000UL)
260#define I2S_AUDIOFREQ_48K (48000UL)
261#define I2S_AUDIOFREQ_44K (44100UL)
262#define I2S_AUDIOFREQ_32K (32000UL)
263#define I2S_AUDIOFREQ_22K (22050UL)
264#define I2S_AUDIOFREQ_16K (16000UL)
265#define I2S_AUDIOFREQ_11K (11025UL)
266#define I2S_AUDIOFREQ_8K (8000UL)
267#define I2S_AUDIOFREQ_DEFAULT (2UL)
276#define I2S_CPOL_LOW (0x00000000UL)
277#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
286#define I2S_FIRSTBIT_MSB (0x00000000UL)
287#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
296#define I2S_WS_INVERSION_DISABLE (0x00000000UL)
297#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
306#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
307#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
316#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
317#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
326#define I2S_IT_RXP SPI_IER_RXPIE
327#define I2S_IT_TXP SPI_IER_TXPIE
328#define I2S_IT_DXP SPI_IER_DXPIE
329#define I2S_IT_UDR SPI_IER_UDRIE
330#define I2S_IT_OVR SPI_IER_OVRIE
331#define I2S_IT_FRE SPI_IER_TIFREIE
332#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
341#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
342#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
343#define I2S_FLAG_DXP SPI_SR_DXP /* I2S status flag : Dx-Packet space available flag */
344#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
345#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
346#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
347
348#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
357/* Exported macros -----------------------------------------------------------*/
367#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
368#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
369 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \
370 (__HANDLE__)->MspInitCallback = NULL; \
371 (__HANDLE__)->MspDeInitCallback = NULL; \
372 } while(0)
373#else
374#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
375#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
376
381#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
382
387#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
388
402#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
403
417#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
418
433#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
434 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
435
448#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
449
454#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
455
460#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
461
466#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
472/* Exported functions --------------------------------------------------------*/
480/* Initialization/de-initialization functions ********************************/
481HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
482HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
483void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
484void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
485
486/* Callbacks Register/UnRegister functions ***********************************/
487#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
488HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
489 pI2S_CallbackTypeDef pCallback);
490HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
491#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
499/* I/O operation functions ***************************************************/
500/* Blocking mode: Polling */
501HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
502HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
503HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
504 uint16_t Size, uint32_t Timeout);
505
506/* Non-Blocking mode: Interrupt */
507HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
508HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
509HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
510 uint16_t Size);
511
512void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
513
514/* Non-Blocking mode: DMA */
515HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
516HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
517HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
518 uint16_t Size);
519
520HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
521HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
522HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
523
524/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
525void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
526void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
527void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
528void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
529void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
530void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
531void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
539/* Peripheral Control and State functions ************************************/
540HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
541uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
550/* Private types -------------------------------------------------------------*/
551/* Private variables ---------------------------------------------------------*/
552/* Private constants ---------------------------------------------------------*/
562/* Private Functions ---------------------------------------------------------*/
567/* Private functions are defined in stm32h7xx_hal_i2S.c file */
572/* Private macros ------------------------------------------------------------*/
589#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
590 & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
591 ? SET : RESET)
592
605#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__)\
606 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
607
613#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
614 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
615 ((__MODE__) == I2S_MODE_MASTER_TX) || \
616 ((__MODE__) == I2S_MODE_MASTER_RX) || \
617 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
618 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
619
620#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
621 ((__MODE__) == I2S_MODE_MASTER_RX) || \
622 ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
623
624#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
625 ((__MODE__) == I2S_MODE_SLAVE_RX) || \
626 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
627
628#define IS_I2S_FULLDUPLEX(__MODE__) (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX) || \
629 ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
630
631#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
632 ((__STANDARD__) == I2S_STANDARD_MSB) || \
633 ((__STANDARD__) == I2S_STANDARD_LSB) || \
634 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
635 ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
636
637#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
638 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
639 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \
640 ((__FORMAT__) == I2S_DATAFORMAT_32B))
641
642#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
643 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
644
645#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
646 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
647 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
648
649#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
650 ((__CPOL__) == I2S_CPOL_HIGH))
651
652#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
653 ((__BIT__) == I2S_FIRSTBIT_LSB))
654
655#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
656 ((__WSINV__) == I2S_WS_INVERSION_ENABLE))
657
658#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
659 ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
660
661#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
662 ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
663
664
677#ifdef __cplusplus
678}
679#endif
680
681#endif /* STM32H7xx_HAL_I2S_H */
682
__IO
#define __IO
Definition: core_cm4.h:239
HAL_I2S_StateTypeDef
HAL_I2S_StateTypeDef
HAL State structures definition.
Definition: stm32h7xx_hal_i2s.h:85
I2S_HandleTypeDef
struct __I2S_HandleTypeDef I2S_HandleTypeDef
I2S handle Structure definition.
HAL_I2S_STATE_ERROR
@ HAL_I2S_STATE_ERROR
Definition: stm32h7xx_hal_i2s.h:93
HAL_I2S_STATE_BUSY
@ HAL_I2S_STATE_BUSY
Definition: stm32h7xx_hal_i2s.h:88
HAL_I2S_STATE_RESET
@ HAL_I2S_STATE_RESET
Definition: stm32h7xx_hal_i2s.h:86
HAL_I2S_STATE_BUSY_TX_RX
@ HAL_I2S_STATE_BUSY_TX_RX
Definition: stm32h7xx_hal_i2s.h:91
HAL_I2S_STATE_BUSY_RX
@ HAL_I2S_STATE_BUSY_RX
Definition: stm32h7xx_hal_i2s.h:90
HAL_I2S_STATE_TIMEOUT
@ HAL_I2S_STATE_TIMEOUT
Definition: stm32h7xx_hal_i2s.h:92
HAL_I2S_STATE_BUSY_TX
@ HAL_I2S_STATE_BUSY_TX
Definition: stm32h7xx_hal_i2s.h:89
HAL_I2S_STATE_READY
@ HAL_I2S_STATE_READY
Definition: stm32h7xx_hal_i2s.h:87
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
I2S_InitTypeDef
I2S Init structure definition.
Definition: stm32h7xx_hal_i2s.h:48
I2S_InitTypeDef::MasterKeepIOState
uint32_t MasterKeepIOState
Definition: stm32h7xx_hal_i2s.h:76
I2S_InitTypeDef::WSInversion
uint32_t WSInversion
Definition: stm32h7xx_hal_i2s.h:70
I2S_InitTypeDef::AudioFreq
uint32_t AudioFreq
Definition: stm32h7xx_hal_i2s.h:61
I2S_InitTypeDef::FirstBit
uint32_t FirstBit
Definition: stm32h7xx_hal_i2s.h:67
I2S_InitTypeDef::Standard
uint32_t Standard
Definition: stm32h7xx_hal_i2s.h:52
I2S_InitTypeDef::DataFormat
uint32_t DataFormat
Definition: stm32h7xx_hal_i2s.h:55
I2S_InitTypeDef::Data24BitAlignment
uint32_t Data24BitAlignment
Definition: stm32h7xx_hal_i2s.h:73
I2S_InitTypeDef::Mode
uint32_t Mode
Definition: stm32h7xx_hal_i2s.h:49
I2S_InitTypeDef::MCLKOutput
uint32_t MCLKOutput
Definition: stm32h7xx_hal_i2s.h:58
I2S_InitTypeDef::CPOL
uint32_t CPOL
Definition: stm32h7xx_hal_i2s.h:64
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138
__I2S_HandleTypeDef
I2S handle Structure definition.
Definition: stm32h7xx_hal_i2s.h:100
__I2S_HandleTypeDef::TxISR
void(* TxISR)(struct __I2S_HandleTypeDef *hi2s)
Definition: stm32h7xx_hal_i2s.h:124
__I2S_HandleTypeDef::RxXferCount
__IO uint16_t RxXferCount
Definition: stm32h7xx_hal_i2s.h:115
__I2S_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32h7xx_hal_i2s.h:128
__I2S_HandleTypeDef::TxXferCount
__IO uint16_t TxXferCount
Definition: stm32h7xx_hal_i2s.h:109
__I2S_HandleTypeDef::RxXferSize
__IO uint16_t RxXferSize
Definition: stm32h7xx_hal_i2s.h:113
__I2S_HandleTypeDef::Init
I2S_InitTypeDef Init
Definition: stm32h7xx_hal_i2s.h:103
__I2S_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_i2s.h:134
__I2S_HandleTypeDef::Instance
SPI_TypeDef * Instance
Definition: stm32h7xx_hal_i2s.h:101
__I2S_HandleTypeDef::RxISR
void(* RxISR)(struct __I2S_HandleTypeDef *hi2s)
Definition: stm32h7xx_hal_i2s.h:122
__I2S_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32h7xx_hal_i2s.h:126
__I2S_HandleTypeDef::Lock
__IO HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_i2s.h:130
__I2S_HandleTypeDef::pRxBuffPtr
uint16_t * pRxBuffPtr
Definition: stm32h7xx_hal_i2s.h:111
__I2S_HandleTypeDef::State
__IO HAL_I2S_StateTypeDef State
Definition: stm32h7xx_hal_i2s.h:132
__I2S_HandleTypeDef::pTxBuffPtr
const uint16_t * pTxBuffPtr
Definition: stm32h7xx_hal_i2s.h:105
__I2S_HandleTypeDef::TxXferSize
__IO uint16_t TxXferSize
Definition: stm32h7xx_hal_i2s.h:107
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