Iomuxc_lpsr_pads

Modules
	Ssarc_mapping

Typedefs
typedef enum _iomuxc_lpsr_sw_mux_ctl_pad	iomuxc_lpsr_sw_mux_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.
typedef enum _iomuxc_lpsr_sw_pad_ctl_pad	iomuxc_lpsr_sw_pad_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.
typedef enum _iomuxc_lpsr_select_input	iomuxc_lpsr_select_input_t
	Enumeration for the IOMUXC_LPSR select input.
typedef enum _iomuxc_lpsr_sw_mux_ctl_pad	iomuxc_lpsr_sw_mux_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.
typedef enum _iomuxc_lpsr_sw_pad_ctl_pad	iomuxc_lpsr_sw_pad_ctl_pad_t
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.
typedef enum _iomuxc_lpsr_select_input	iomuxc_lpsr_select_input_t
	Enumeration for the IOMUXC_LPSR select input.

Enumerations
enum	_iomuxc_lpsr_sw_mux_ctl_pad {   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD. More...
enum	_iomuxc_lpsr_sw_pad_ctl_pad {   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD. More...
enum	_iomuxc_lpsr_select_input {   kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U , kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U ,   kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U ,   kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U , kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U ,   kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U ,   kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U , kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U , kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U ,   kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U ,   kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U , kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U ,   kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U ,   kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U , kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U ,   kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U ,   kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U , kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U , kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U ,   kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U }
	Enumeration for the IOMUXC_LPSR select input. More...
enum	_iomuxc_lpsr_sw_mux_ctl_pad {   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD. More...
enum	_iomuxc_lpsr_sw_pad_ctl_pad {   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U ,   kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U , kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U }
	Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD. More...
enum	_iomuxc_lpsr_select_input {   kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U , kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U ,   kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U ,   kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U , kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U ,   kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U ,   kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U , kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U , kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U ,   kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U ,   kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U , kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U , kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U ,   kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U , kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U ,   kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U , kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U , kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U ,   kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U , kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U ,   kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U , kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U , kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U ,   kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U , kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U }
	Enumeration for the IOMUXC_LPSR select input. More...

Detailed Description

Typedef Documentation

iomuxc_lpsr_select_input_t [1/2]

typedef enum _iomuxc_lpsr_select_input iomuxc_lpsr_select_input_t

Enumeration for the IOMUXC_LPSR select input.

Defines the enumeration for the IOMUXC_LPSR select input collections.

iomuxc_lpsr_select_input_t [2/2]

typedef enum _iomuxc_lpsr_select_input iomuxc_lpsr_select_input_t

Enumeration for the IOMUXC_LPSR select input.

Defines the enumeration for the IOMUXC_LPSR select input collections.

iomuxc_lpsr_sw_mux_ctl_pad_t [1/2]

typedef enum _iomuxc_lpsr_sw_mux_ctl_pad iomuxc_lpsr_sw_mux_ctl_pad_t

Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.

iomuxc_lpsr_sw_mux_ctl_pad_t [2/2]

typedef enum _iomuxc_lpsr_sw_mux_ctl_pad iomuxc_lpsr_sw_mux_ctl_pad_t

Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.

iomuxc_lpsr_sw_pad_ctl_pad_t [1/2]

typedef enum _iomuxc_lpsr_sw_pad_ctl_pad iomuxc_lpsr_sw_pad_ctl_pad_t

Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.

iomuxc_lpsr_sw_pad_ctl_pad_t [2/2]

typedef enum _iomuxc_lpsr_sw_pad_ctl_pad iomuxc_lpsr_sw_pad_ctl_pad_t

Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.

Enumeration Type Documentation

_iomuxc_lpsr_select_input [1/2]

enum _iomuxc_lpsr_select_input

Enumeration for the IOMUXC_LPSR select input.

Defines the enumeration for the IOMUXC_LPSR select input collections.

Enumerator
kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3	IOMUXC select input index
kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3	IOMUXC select input index
kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT	IOMUXC select input index

_iomuxc_lpsr_select_input [2/2]

enum _iomuxc_lpsr_select_input

Enumeration for the IOMUXC_LPSR select input.

Defines the enumeration for the IOMUXC_LPSR select input collections.

Enumerator
kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3	IOMUXC select input index
kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2	IOMUXC select input index
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3	IOMUXC select input index
kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT	IOMUXC select input index
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT	IOMUXC select input index

_iomuxc_lpsr_sw_mux_ctl_pad [1/2]

enum _iomuxc_lpsr_sw_mux_ctl_pad

Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_MUX_CTL_PAD index

_iomuxc_lpsr_sw_mux_ctl_pad [2/2]

enum _iomuxc_lpsr_sw_mux_ctl_pad

Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.

Enumerator
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_MUX_CTL_PAD index
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_MUX_CTL_PAD index

_iomuxc_lpsr_sw_pad_ctl_pad [1/2]

enum _iomuxc_lpsr_sw_pad_ctl_pad

Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_PAD_CTL_PAD index

_iomuxc_lpsr_sw_pad_ctl_pad [2/2]

enum _iomuxc_lpsr_sw_pad_ctl_pad

Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD.

Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.

Enumerator
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14	IOMUXC SW_PAD_CTL_PAD index
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15	IOMUXC SW_PAD_CTL_PAD index