RTEMS: Cache_armv7_m7

RTEMS 6.1-rc5

Loading...

Searching...

No Matches

Control for cortex-m7 L1 cache
void	L1CACHE_InvalidateICacheByRange (uint32_t address, uint32_t size_byte)
	Invalidate cortex-m7 L1 instruction cache by range.

Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
Mainly used for many drivers for easy cache operation.
void	ICACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates all instruction caches by range.

void	DCACHE_InvalidateByRange (uint32_t address, uint32_t size_byte)
	Invalidates all data caches by range.

void	DCACHE_CleanByRange (uint32_t address, uint32_t size_byte)
	Cleans all data caches by range.

void	DCACHE_CleanInvalidateByRange (uint32_t address, uint32_t size_byte)
	Cleans and Invalidates all data caches by range.

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
	cache driver version 2.0.4.

Driver version
#define	FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
	cache driver version 2.0.4.

Detailed Description

Function Documentation

◆ DCACHE_CleanByRange()

void DCACHE_CleanByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be cleaned. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Cleans all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be cleaned. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

◆ DCACHE_CleanInvalidateByRange()

void DCACHE_CleanInvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned and invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be cleaned and invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be cleaned and invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Cleans and Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be cleaned and invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

◆ DCACHE_InvalidateByRange()

void DCACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidates all data caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

◆ ICACHE_InvalidateByRange()

void ICACHE_InvalidateByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

Parameters

address	The physical address.
size_byte	size of the memory to be invalidated.

Note: address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidates all instruction caches by range.

Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.

param address The physical address. param size_byte size of the memory to be invalidated. note address and size should be aligned to cache line size 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced to align to the cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

◆ L1CACHE_InvalidateICacheByRange()

void L1CACHE_InvalidateICacheByRange	(	uint32_t	address,
		uint32_t	size_byte
	)

Invalidate cortex-m7 L1 instruction cache by range.

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidates cortex-m4 L1 instrument cache by range.

param address The start address of the memory to be invalidated. param size_byte The memory size. note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.

Parameters

address	The start address of the memory to be invalidated.
size_byte	The memory size.

Note: The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.

brief Invalidate cortex-m7 L1 instruction cache by range.

param address The start address of the memory to be invalidated. param size_byte The memory size. note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. The startAddr here will be forced to align to L1 I-cache line size if startAddr is not aligned. For the size_byte, application should make sure the alignment or make sure the right operation order if the size_byte is not aligned.