USBPHY Peripheral Access Layer

Modules
	USBPHY Register Masks

Data Structures
struct	USBPHY_Type

Macros
#define	USBPHY1_BASE   (0x400D9000u)
#define	USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)
#define	USBPHY2_BASE   (0x400DA000u)
#define	USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)
#define	USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
#define	USBPHY_IRQS   { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }
#define	USBPHY_CTRL_ENDEVPLUGINDET_MASK   USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define	USBPHY_CTRL_ENDEVPLUGINDET_SHIFT   USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define	USBPHY_CTRL_ENDEVPLUGINDET(x)   USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define	USBPHY_TX_TXCAL45DM_MASK   USBPHY_TX_TXCAL45DN_MASK
#define	USBPHY_TX_TXCAL45DM_SHIFT   USBPHY_TX_TXCAL45DN_SHIFT
#define	USBPHY_TX_TXCAL45DM(x)   USBPHY_TX_TXCAL45DN(x)
#define	USBPHY_STACK_BASE_ADDRS   { USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY1_BASE   (0x40434000u)
#define	USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)
#define	USBPHY2_BASE   (0x40438000u)
#define	USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)
#define	USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
#define	USBPHY_IRQS   { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
#define	USBPHY_CTRL_ENDEVPLUGINDET_MASK   USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define	USBPHY_CTRL_ENDEVPLUGINDET_SHIFT   USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define	USBPHY_CTRL_ENDEVPLUGINDET(x)   USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define	USBPHY_TX_TXCAL45DM_MASK   USBPHY_TX_TXCAL45DN_MASK
#define	USBPHY_TX_TXCAL45DM_SHIFT   USBPHY_TX_TXCAL45DN_SHIFT
#define	USBPHY_TX_TXCAL45DM(x)   USBPHY_TX_TXCAL45DN(x)
#define	USBPHY_STACK_BASE_ADDRS   { USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY1_BASE   (0x40434000u)
#define	USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)
#define	USBPHY2_BASE   (0x40438000u)
#define	USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)
#define	USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }
#define	USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
#define	USBPHY_IRQS   { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
#define	USBPHY_CTRL_ENDEVPLUGINDET_MASK   USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define	USBPHY_CTRL_ENDEVPLUGINDET_SHIFT   USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define	USBPHY_CTRL_ENDEVPLUGINDET(x)   USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define	USBPHY_TX_TXCAL45DM_MASK   USBPHY_TX_TXCAL45DN_MASK
#define	USBPHY_TX_TXCAL45DM_SHIFT   USBPHY_TX_TXCAL45DN_SHIFT
#define	USBPHY_TX_TXCAL45DM(x)   USBPHY_TX_TXCAL45DN(x)
#define	USBPHY_STACK_BASE_ADDRS   { USBPHY1_BASE, USBPHY2_BASE }

Detailed Description

Macro Definition Documentation

USBPHY1 [1/3]

#define USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)

Peripheral USBPHY1 base pointer

USBPHY1 [2/3]

#define USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)

Peripheral USBPHY1 base pointer

USBPHY1 [3/3]

#define USBPHY1   ((USBPHY_Type *)USBPHY1_BASE)

Peripheral USBPHY1 base pointer

USBPHY1_BASE [1/3]

#define USBPHY1_BASE   (0x400D9000u)

Peripheral USBPHY1 base address

USBPHY1_BASE [2/3]

#define USBPHY1_BASE   (0x40434000u)

Peripheral USBPHY1 base address

USBPHY1_BASE [3/3]

#define USBPHY1_BASE   (0x40434000u)

Peripheral USBPHY1 base address

USBPHY2 [1/3]

#define USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)

Peripheral USBPHY2 base pointer

USBPHY2 [2/3]

#define USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)

Peripheral USBPHY2 base pointer

USBPHY2 [3/3]

#define USBPHY2   ((USBPHY_Type *)USBPHY2_BASE)

Peripheral USBPHY2 base pointer

USBPHY2_BASE [1/3]

#define USBPHY2_BASE   (0x400DA000u)

Peripheral USBPHY2 base address

USBPHY2_BASE [2/3]

#define USBPHY2_BASE   (0x40438000u)

Peripheral USBPHY2 base address

USBPHY2_BASE [3/3]

#define USBPHY2_BASE   (0x40438000u)

Peripheral USBPHY2 base address

USBPHY_BASE_ADDRS [1/3]

#define USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }

Array initializer of USBPHY peripheral base addresses

USBPHY_BASE_ADDRS [2/3]

#define USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }

Array initializer of USBPHY peripheral base addresses

USBPHY_BASE_ADDRS [3/3]

#define USBPHY_BASE_ADDRS   { 0u, USBPHY1_BASE, USBPHY2_BASE }

Array initializer of USBPHY peripheral base addresses

USBPHY_BASE_PTRS [1/3]

#define USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }

Array initializer of USBPHY peripheral base pointers

USBPHY_BASE_PTRS [2/3]

#define USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }

Array initializer of USBPHY peripheral base pointers

USBPHY_BASE_PTRS [3/3]

#define USBPHY_BASE_PTRS   { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }

Array initializer of USBPHY peripheral base pointers

USBPHY_IRQS [1/3]

#define USBPHY_IRQS   { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn }

Interrupt vectors for the USBPHY peripheral type

USBPHY_IRQS [2/3]

#define USBPHY_IRQS   { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }

Interrupt vectors for the USBPHY peripheral type

USBPHY_IRQS [3/3]

#define USBPHY_IRQS   { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }

Interrupt vectors for the USBPHY peripheral type