RTEMS 6.1-rc5
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DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register | |
#define | SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU) |
#define | SSARC_LP_DESC_CTRL0_START_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) |
#define | SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U) |
#define | SSARC_LP_DESC_CTRL0_END_SHIFT (10U) |
#define | SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK) |
DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register | |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U) |
#define | SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U) |
#define | SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) |
#define | SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U) |
#define | SSARC_LP_DESC_CTRL1_RL_SHIFT (18U) |
#define | SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) |
#define | SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U) |
#define | SSARC_LP_DESC_CTRL1_WL_SHIFT (19U) |
#define | SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) |
#define | SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL1_DL_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL1_DL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK) |
DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register | |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK) |
DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register | |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK) |
CTRL - Control Register | |
#define | SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) |
#define | SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U) |
#define | SSARC_LP_CTRL_SW_RESET_SHIFT (31U) |
#define | SSARC_LP_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK) |
INT_STATUS - Interrupt Status Register | |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK) |
HP_TIMEOUT - HP Timeout Register | |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK) |
HW_GROUP_PENDING - Hardware Request Pending Register | |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) |
SW_GROUP_PENDING - Software Request Pending Register | |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) |
DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register | |
#define | SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU) |
#define | SSARC_LP_DESC_CTRL0_START_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) |
#define | SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U) |
#define | SSARC_LP_DESC_CTRL0_END_SHIFT (10U) |
#define | SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U) |
#define | SSARC_LP_DESC_CTRL0_RT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK) |
DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register | |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U) |
#define | SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U) |
#define | SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U) |
#define | SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U) |
#define | SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U) |
#define | SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) |
#define | SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U) |
#define | SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U) |
#define | SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) |
#define | SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U) |
#define | SSARC_LP_DESC_CTRL1_RL_SHIFT (18U) |
#define | SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) |
#define | SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U) |
#define | SSARC_LP_DESC_CTRL1_WL_SHIFT (19U) |
#define | SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) |
#define | SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U) |
#define | SSARC_LP_DESC_CTRL1_DL_SHIFT (20U) |
#define | SSARC_LP_DESC_CTRL1_DL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK) |
DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register | |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_UP_ADDR_UP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK) |
DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register | |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U) |
#define | SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK) |
CTRL - Control Register | |
#define | SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U) |
#define | SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) |
#define | SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U) |
#define | SSARC_LP_CTRL_SW_RESET_SHIFT (31U) |
#define | SSARC_LP_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK) |
INT_STATUS - Interrupt Status Register | |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U) |
#define | SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U) |
#define | SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U) |
#define | SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U) |
#define | SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U) |
#define | SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U) |
#define | SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U) |
#define | SSARC_LP_INT_STATUS_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK) |
HP_TIMEOUT - HP Timeout Register | |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U) |
#define | SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK) |
HW_GROUP_PENDING - Hardware Request Pending Register | |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) |
SW_GROUP_PENDING - Software Request Pending Register | |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U) |
#define | SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) |
#define SSARC_LP_CTRL_DIS_HW_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) |
DIS_HW_REQ - Save/Restore request disable 0b0..PGMC save/restore requests enabled 0b1..PGMC save/restore requests disabled
#define SSARC_LP_CTRL_DIS_HW_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) |
DIS_HW_REQ - Save/Restore request disable 0b0..PGMC save/restore requests enabled 0b1..PGMC save/restore requests disabled
#define SSARC_LP_CTRL_SW_RESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK) |
SW_RESET - Software reset
#define SSARC_LP_CTRL_SW_RESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK) |
SW_RESET - Software reset
#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK) |
ADDR_DOWN - Address field (Low)
#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK) |
ADDR_DOWN - Address field (Low)
#define SSARC_LP_DESC_ADDR_UP_ADDR_UP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK) |
ADDR_UP - Address field (High)
#define SSARC_LP_DESC_ADDR_UP_ADDR_UP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK) |
ADDR_UP - Address field (High)
#define SSARC_LP_DESC_CTRL0_END | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) |
END - End index
#define SSARC_LP_DESC_CTRL0_END | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) |
END - End index
#define SSARC_LP_DESC_CTRL0_RT_ORDER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK) |
RT_ORDER - Restore order 0b0..Descriptors within the group are processed from start to end 0b1..Descriptors within the group are processed from end to start
#define SSARC_LP_DESC_CTRL0_RT_ORDER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK) |
RT_ORDER - Restore order 0b0..Descriptors within the group are processed from start to end 0b1..Descriptors within the group are processed from end to start
#define SSARC_LP_DESC_CTRL0_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) |
START - Start index
#define SSARC_LP_DESC_CTRL0_START | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) |
START - Start index
#define SSARC_LP_DESC_CTRL0_SV_ORDER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) |
SV_ORDER - Save Order 0b0..Descriptors within the group are processed from start to end 0b1..Descriptors within the group are processed from end to start
#define SSARC_LP_DESC_CTRL0_SV_ORDER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) |
SV_ORDER - Save Order 0b0..Descriptors within the group are processed from start to end 0b1..Descriptors within the group are processed from end to start
#define SSARC_LP_DESC_CTRL1_CPUD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) |
CPUD - CPU Domain
#define SSARC_LP_DESC_CTRL1_CPUD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) |
CPUD - CPU Domain
#define SSARC_LP_DESC_CTRL1_DL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK) |
DL - Domain lock 0b1..Lock 0b0..Unlock
#define SSARC_LP_DESC_CTRL1_DL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK) |
DL - Domain lock 0b1..Lock 0b0..Unlock
#define SSARC_LP_DESC_CTRL1_GP_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) |
GP_EN - Group Enable 0b0..Group disabled 0b1..Group enabled
#define SSARC_LP_DESC_CTRL1_GP_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) |
GP_EN - Group Enable 0b0..Group disabled 0b1..Group enabled
#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) |
POWER_DOMAIN 0b000..PGMC_BPC0 0b001..PGMC_BPC1 0b010..PGMC_BPC2 0b011..PGMC_BPC3 0b100..PGMC_BPC4 0b101..PGMC_BPC5 0b110..PGMC_BPC6 0b111..PGMC_BPC7
#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) |
POWER_DOMAIN 0b000..PGMC_BPC0 0b001..PGMC_BPC1 0b010..PGMC_BPC2 0b011..PGMC_BPC3 0b100..PGMC_BPC4 0b101..PGMC_BPC5 0b110..PGMC_BPC6 0b111..PGMC_BPC7
#define SSARC_LP_DESC_CTRL1_RL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) |
RL - Read Lock 0b1..Group is locked (read access not allowed) 0b0..Group is unlocked (read access allowed)
#define SSARC_LP_DESC_CTRL1_RL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) |
RL - Read Lock 0b1..Group is locked (read access not allowed) 0b0..Group is unlocked (read access allowed)
#define SSARC_LP_DESC_CTRL1_RT_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) |
RT_PRIORITY - Restore Priority
#define SSARC_LP_DESC_CTRL1_RT_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) |
RT_PRIORITY - Restore Priority
#define SSARC_LP_DESC_CTRL1_SV_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) |
SV_PRIORITY - Save Priority
#define SSARC_LP_DESC_CTRL1_SV_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) |
SV_PRIORITY - Save Priority
#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) |
SW_TRIG_RT - Software trigger restore 0b1..Request a software restore operation/software restore operation in progress 0b0..No software restore request/software restore request complete
#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) |
SW_TRIG_RT - Software trigger restore 0b1..Request a software restore operation/software restore operation in progress 0b0..No software restore request/software restore request complete
#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) |
SW_TRIG_SV - Software trigger save 0b1..Request a software save operation/software restore operation in progress 0b0..No software save request/software restore request complete
#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) |
SW_TRIG_SV - Software trigger save 0b1..Request a software save operation/software restore operation in progress 0b0..No software save request/software restore request complete
#define SSARC_LP_DESC_CTRL1_WL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) |
WL - Write Lock 0b1..Group is locked (write access not allowed) 0b0..Group is unlocked (write access allowed)
#define SSARC_LP_DESC_CTRL1_WL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) |
WL - Write Lock 0b1..Group is locked (write access not allowed) 0b0..Group is unlocked (write access allowed)
#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK) |
TIMEOUT_VALUE - Time out value
#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK) |
TIMEOUT_VALUE - Time out value
#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) |
HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request
#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK) |
HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request
#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) |
HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request
#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) |
HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request
#define SSARC_LP_INT_STATUS_ADDR_ERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK) |
ADDR_ERR - Address Error field 0b1..An address error has occurred 0b0..No address error
#define SSARC_LP_INT_STATUS_ADDR_ERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK) |
ADDR_ERR - Address Error field 0b1..An address error has occurred 0b0..No address error
#define SSARC_LP_INT_STATUS_AHB_ERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) |
AHB_ERR - AHB Error field 0b1..An AHB error has occurred 0b0..No AHB error
#define SSARC_LP_INT_STATUS_AHB_ERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) |
AHB_ERR - AHB Error field 0b1..An AHB error has occurred 0b0..No AHB error
#define SSARC_LP_INT_STATUS_AHB_RESP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) |
AHB_RESP - AHB Bus response field
#define SSARC_LP_INT_STATUS_AHB_RESP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) |
AHB_RESP - AHB Bus response field
#define SSARC_LP_INT_STATUS_ERR_INDEX | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) |
ERR_INDEX - Error Index
#define SSARC_LP_INT_STATUS_ERR_INDEX | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) |
ERR_INDEX - Error Index
#define SSARC_LP_INT_STATUS_GROUP_CONFLICT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) |
GROUP_CONFLICT - Group Conflict field 0b1..A group conflict error has occurred 0b0..No group conflict error
#define SSARC_LP_INT_STATUS_GROUP_CONFLICT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) |
GROUP_CONFLICT - Group Conflict field 0b1..A group conflict error has occurred 0b0..No group conflict error
#define SSARC_LP_INT_STATUS_SW_REQ_DONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) |
SW_REQ_DONE - Software Request Done 0b1..Atleast one software triggered has been complete 0b0..No software triggered requests or software triggered request still in progress
#define SSARC_LP_INT_STATUS_SW_REQ_DONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) |
SW_REQ_DONE - Software Request Done 0b1..Atleast one software triggered has been complete 0b0..No software triggered requests or software triggered request still in progress
#define SSARC_LP_INT_STATUS_TIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) |
TIMEOUT - Timeout field 0b1..A timeout event has occurred 0b0..No timeout event
#define SSARC_LP_INT_STATUS_TIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) |
TIMEOUT - Timeout field 0b1..A timeout event has occurred 0b0..No timeout event
#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) |
SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request
#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK) |
SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request
#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) |
SW_SAVE_PENDING - This field indicates which groups are pending for save from software request
#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) |
SW_SAVE_PENDING - This field indicates which groups are pending for save from software request