RTEMS no cpu Build Information

Macros
#define	MIPS_HAS_FPU   1
#define	CPU_NAME   "MIPS"
#define	MIPS_EXCEPTION_BASE   0
#define	MIPS_EXCEPTION_INT   MIPS_EXCEPTION_BASE+0
#define	MIPS_EXCEPTION_MOD   MIPS_EXCEPTION_BASE+1
#define	MIPS_EXCEPTION_TLBL   MIPS_EXCEPTION_BASE+2
#define	MIPS_EXCEPTION_TLBS   MIPS_EXCEPTION_BASE+3
#define	MIPS_EXCEPTION_ADEL   MIPS_EXCEPTION_BASE+4
#define	MIPS_EXCEPTION_ADES   MIPS_EXCEPTION_BASE+5
#define	MIPS_EXCEPTION_IBE   MIPS_EXCEPTION_BASE+6
#define	MIPS_EXCEPTION_DBE   MIPS_EXCEPTION_BASE+7
#define	MIPS_EXCEPTION_SYSCALL   MIPS_EXCEPTION_BASE+8
#define	MIPS_EXCEPTION_BREAK   MIPS_EXCEPTION_BASE+9
#define	MIPS_EXCEPTION_RI   MIPS_EXCEPTION_BASE+10
#define	MIPS_EXCEPTION_CPU   MIPS_EXCEPTION_BASE+11
#define	MIPS_EXCEPTION_OVERFLOW   MIPS_EXCEPTION_BASE+12
#define	MIPS_EXCEPTION_TRAP   MIPS_EXCEPTION_BASE+13
#define	MIPS_EXCEPTION_VCEI   MIPS_EXCEPTION_BASE+14
#define	MIPS_EXCEPTION_FPE   MIPS_EXCEPTION_BASE+15
#define	MIPS_EXCEPTION_C2E   MIPS_EXCEPTION_BASE+16
#define	MIPS_EXCEPTION_WATCH   MIPS_EXCEPTION_BASE+23
#define	MIPS_EXCEPTION_VCED   MIPS_EXCEPTION_BASE+31
#define	MIPS_INTERRUPT_BASE   MIPS_EXCEPTION_BASE+32
#define	mips_get_sr(_x)
#define	mips_set_sr(_x)
#define	mips_get_cause(_x)
#define	mips_set_cause(_x)
#define	mips_get_dcic(_x)
#define	mips_set_dcic(_x)
#define	mips_get_bpcrm(_x, _y)
#define	mips_set_bpcrm(_x, _y)
#define	mips_get_bdarm(_x, _y)
#define	mips_set_bdarm(_x, _y)
#define	mips_get_fcr31(_x)
#define	mips_set_fcr31(_x)
#define	mips_enable_in_interrupt_mask(_mask)
#define	mips_disable_in_interrupt_mask(_mask)

Detailed Description

Macro Definition Documentation

mips_disable_in_interrupt_mask

#define mips_disable_in_interrupt_mask

(

_mask

)

Value:

  do { \
    unsigned int _sr; \
    mips_get_sr( _sr ); \
    _sr &= ~(_mask); \
    mips_set_sr( _sr ); \
  } while (0)

mips_enable_in_interrupt_mask

#define mips_enable_in_interrupt_mask

(

_mask

)

Value:

  do { \
    unsigned int _sr; \
    mips_get_sr( _sr ); \
    _sr |= (_mask); \
    mips_set_sr( _sr ); \
  } while (0)

mips_get_bdarm

#define mips_get_bdarm	(		_x,
			_y
	)

Value:

  do { \
    __asm__ volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
    __asm__ volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
  } while (0)

mips_get_bpcrm

#define mips_get_bpcrm	(		_x,
			_y
	)

Value:

  do { \
    __asm__ volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
    __asm__ volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
  } while (0)

mips_get_cause

#define mips_get_cause

(

_x

)

Value:

  do { \
    __asm__ volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
  } while (0)

mips_get_dcic

#define mips_get_dcic

(

_x

)

Value:

  do { \
    __asm__ volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
  } while (0)

mips_get_fcr31

#define mips_get_fcr31

(

_x

)

Value:

  do { \
    __asm__ volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
  } while(0)

mips_get_sr

#define mips_get_sr

(

_x

)

Value:

  do { \
    __asm__ volatile( "mfc0 %0, $12; nop" : "=r" (_x) : ); \
  } while (0)

mips_set_bdarm

#define mips_set_bdarm	(		_x,
			_y
	)

Value:

  do { \
    unsigned int __x = (_x); \
    unsigned int __y = (_y); \
    __asm__ volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
    __asm__ volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
  } while (0)

mips_set_bpcrm

#define mips_set_bpcrm	(		_x,
			_y
	)

Value:

  do { \
    unsigned int __x = (_x); \
    unsigned int __y = (_y); \
    __asm__ volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
    __asm__ volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
  } while (0)

mips_set_cause

#define mips_set_cause

(

_x

)

Value:

  do { \
    unsigned int __x = (_x); \
    __asm__ volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
  } while (0)

mips_set_dcic

#define mips_set_dcic

(

_x

)

Value:

  do { \
    unsigned int __x = (_x); \
    __asm__ volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
  } while (0)

mips_set_fcr31

#define mips_set_fcr31

(

_x

)

Value:

  do { \
    unsigned int __x = (_x); \
    __asm__ volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
  } while(0)

mips_set_sr

#define mips_set_sr

(

_x

)

Value:

  do { \
    unsigned int __x = (_x); \
    __asm__ volatile( "mtc0 %0, $12; nop" : : "r" (__x) ); \
  } while (0)