RTEMS 6.1-rc5
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Data Structures | Macros | Functions
Processor Dependent Context Management

Data Structures

struct  Context_Control
 Thread register context. More...
 
struct  CPU_Interrupt_frame
 Interrupt stack frame (ISF). More...
 

Macros

#define _CPU_Context_Get_SP(_context)    (_context)->register_sp
 

Functions

void _CPU_Context_switch (Context_Control *run, Context_Control *heir)
 CPU switch context.
 
RTEMS_NO_RETURN void _CPU_Context_restore (Context_Control *new_context)
 

Detailed Description

From the highest level viewpoint, there are 2 types of context to save.

  1. Interrupt registers to save
  2. Task level registers to save

Since RTEMS handles integer and floating point contexts separately, this means we have the following 3 context items:

  1. task level context stuff:: Context_Control
  2. floating point task stuff:: Context_Control_fp
  3. special interrupt level context :: CPU_Interrupt_frame

On some processors, it is cost-effective to save only the callee preserved registers during a task context switch. This means that the ISR code needs to save those registers which do not persist across function calls. It is not mandatory to make this distinctions between the caller/callee saves registers for the purpose of minimizing context saved during task switch and on interrupts. If the cost of saving extra registers is minimal, simplicity is the choice. Save the same context on interrupt entry as for tasks in this case.

Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then care should be used in designing the context area.

On some CPUs with hardware floating point support, the Context_Control_fp structure will not be used or it simply consist of an array of a fixed number of bytes. This is done when the floating point context is dumped by a "FP save context" type instruction and the format is not really defined by the CPU. In this case, there is no need to figure out the exact format – only the size. Of course, although this is enough information for RTEMS, it is probably not enough for a debugger such as gdb. But that is another problem.

Port Specific Information:

XXX document implementation including references if appropriate

Should be large enough to run all RTEMS tests. This ensures that a "reasonable" small application should not have any problems.

Port Specific Information:

XXX document implementation including references if appropriate

Initialize the context to a state suitable for starting a task after a context restore operation. Generally, this involves:

This routine generally does not set any unnecessary register in the context. The state of the "general data" registers is undefined at task start time.

Parameters
[in]_the_contextis the context structure to be initialized
[in]_stack_baseis the lowest physical address of this task's stack
[in]_sizeis the size of this task's stack
[in]_isris the interrupt disable level
[in]_entry_pointis the thread's entry point. This is always _Thread_Handler
[in]_is_fpis TRUE if the thread is to be a floating point thread. This is typically only used on CPUs where the FPU may be easily disabled by software such as on the SPARC where the PSR contains an enable FPU bit.
[in]tls_areais the thread-local storage (TLS) area

Port Specific Information:

See implementation in cpu.c

Function Documentation

◆ _CPU_Context_restore()

RTEMS_NO_RETURN void _CPU_Context_restore ( Context_Control new_context)

This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.

Parameters
[in]new_contextpoints to the context to be restored.
Note
May be unnecessary to reload some registers.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Context_switch()

void _CPU_Context_switch ( Context_Control run,
Context_Control heir 
)

CPU switch context.

This routine switches from the run context to the heir context.

Parameters
[in]runpoints to the context of the currently executing task
[in]heirpoints to the context of the heir task

Port Specific Information:

XXX document implementation including references if appropriate