RTEMS 6.1-rc5
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Macros
Interrupt distribution ISR (ISR)

This group contains register bit definitions. More...

Macros

#define GRSPW2_ISR_ISR_SHIFT   0
 
#define GRSPW2_ISR_ISR_MASK   0xffffffffU
 
#define GRSPW2_ISR_ISR_GET(_reg)
 
#define GRSPW2_ISR_ISR_SET(_reg, _val)
 
#define GRSPW2_ISR_ISR(_val)
 

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

◆ GRSPW2_ISR_ISR

#define GRSPW2_ISR_ISR (   _val)
Value:
( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
GRSPW2_ISR_ISR_MASK )

◆ GRSPW2_ISR_ISR_GET

#define GRSPW2_ISR_ISR_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_ISR_ISR_MASK ) >> \
GRSPW2_ISR_ISR_SHIFT )

◆ GRSPW2_ISR_ISR_SET

#define GRSPW2_ISR_ISR_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_ISR_ISR_MASK ) | \
( ( ( _val ) << GRSPW2_ISR_ISR_SHIFT ) & \
GRSPW2_ISR_ISR_MASK ) )