RTEMS 6.1-rc5
Loading...
Searching...
No Matches
Macros
DMA control/status (DMACTRL)

This group contains register bit definitions. More...

Macros

#define GRSPW2_DMACTRL_INTNUM_SHIFT   26
 
#define GRSPW2_DMACTRL_INTNUM_MASK   0xfc000000U
 
#define GRSPW2_DMACTRL_INTNUM_GET(_reg)
 
#define GRSPW2_DMACTRL_INTNUM_SET(_reg, _val)
 
#define GRSPW2_DMACTRL_INTNUM(_val)
 
#define GRSPW2_DMACTRL_RES_SHIFT   24
 
#define GRSPW2_DMACTRL_RES_MASK   0x3000000U
 
#define GRSPW2_DMACTRL_RES_GET(_reg)
 
#define GRSPW2_DMACTRL_RES_SET(_reg, _val)
 
#define GRSPW2_DMACTRL_RES(_val)
 
#define GRSPW2_DMACTRL_EP   0x800000U
 
#define GRSPW2_DMACTRL_TR   0x400000U
 
#define GRSPW2_DMACTRL_IE   0x200000U
 
#define GRSPW2_DMACTRL_IT   0x100000U
 
#define GRSPW2_DMACTRL_RP   0x80000U
 
#define GRSPW2_DMACTRL_TP   0x40000U
 
#define GRSPW2_DMACTRL_TL   0x20000U
 
#define GRSPW2_DMACTRL_LE   0x10000U
 
#define GRSPW2_DMACTRL_SP   0x8000U
 
#define GRSPW2_DMACTRL_SA   0x4000U
 
#define GRSPW2_DMACTRL_EN   0x2000U
 
#define GRSPW2_DMACTRL_NS   0x1000U
 
#define GRSPW2_DMACTRL_RD   0x800U
 
#define GRSPW2_DMACTRL_RX   0x400U
 
#define GRSPW2_DMACTRL_AT   0x200U
 
#define GRSPW2_DMACTRL_RA   0x100U
 
#define GRSPW2_DMACTRL_TA   0x80U
 
#define GRSPW2_DMACTRL_PR   0x40U
 
#define GRSPW2_DMACTRL_PS   0x20U
 
#define GRSPW2_DMACTRL_AI   0x10U
 
#define GRSPW2_DMACTRL_RI   0x8U
 
#define GRSPW2_DMACTRL_TI   0x4U
 
#define GRSPW2_DMACTRL_RE   0x2U
 
#define GRSPW2_DMACTRL_TE   0x1U
 

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

◆ GRSPW2_DMACTRL_INTNUM

#define GRSPW2_DMACTRL_INTNUM (   _val)
Value:
( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
GRSPW2_DMACTRL_INTNUM_MASK )

◆ GRSPW2_DMACTRL_INTNUM_GET

#define GRSPW2_DMACTRL_INTNUM_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_DMACTRL_INTNUM_MASK ) >> \
GRSPW2_DMACTRL_INTNUM_SHIFT )

◆ GRSPW2_DMACTRL_INTNUM_SET

#define GRSPW2_DMACTRL_INTNUM_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_DMACTRL_INTNUM_MASK ) | \
( ( ( _val ) << GRSPW2_DMACTRL_INTNUM_SHIFT ) & \
GRSPW2_DMACTRL_INTNUM_MASK ) )

◆ GRSPW2_DMACTRL_RES

#define GRSPW2_DMACTRL_RES (   _val)
Value:
( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
GRSPW2_DMACTRL_RES_MASK )

◆ GRSPW2_DMACTRL_RES_GET

#define GRSPW2_DMACTRL_RES_GET (   _reg)
Value:
( ( ( _reg ) & GRSPW2_DMACTRL_RES_MASK ) >> \
GRSPW2_DMACTRL_RES_SHIFT )

◆ GRSPW2_DMACTRL_RES_SET

#define GRSPW2_DMACTRL_RES_SET (   _reg,
  _val 
)
Value:
( ( ( _reg ) & ~GRSPW2_DMACTRL_RES_MASK ) | \
( ( ( _val ) << GRSPW2_DMACTRL_RES_SHIFT ) & \
GRSPW2_DMACTRL_RES_MASK ) )