SDRAM configuration register 1 (SDCFG1)

This group contains register bit definitions. More...

Macros
#define	MMCTRL_SDCFG1_RF   0x80000000U
#define	MMCTRL_SDCFG1_TRP   0x40000000U
#define	MMCTRL_SDCFG1_TRFC_SHIFT   27
#define	MMCTRL_SDCFG1_TRFC_MASK   0x38000000U
#define	MMCTRL_SDCFG1_TRFC_GET(_reg)
#define	MMCTRL_SDCFG1_TRFC_SET(_reg, _val)
#define	MMCTRL_SDCFG1_TRFC(_val)
#define	MMCTRL_SDCFG1_TC   0x4000000U
#define	MMCTRL_SDCFG1_BANKSZ_SHIFT   23
#define	MMCTRL_SDCFG1_BANKSZ_MASK   0x3800000U
#define	MMCTRL_SDCFG1_BANKSZ_GET(_reg)
#define	MMCTRL_SDCFG1_BANKSZ_SET(_reg, _val)
#define	MMCTRL_SDCFG1_BANKSZ(_val)
#define	MMCTRL_SDCFG1_COLSZ_SHIFT   21
#define	MMCTRL_SDCFG1_COLSZ_MASK   0x600000U
#define	MMCTRL_SDCFG1_COLSZ_GET(_reg)
#define	MMCTRL_SDCFG1_COLSZ_SET(_reg, _val)
#define	MMCTRL_SDCFG1_COLSZ(_val)
#define	MMCTRL_SDCFG1_COMMAND_SHIFT   18
#define	MMCTRL_SDCFG1_COMMAND_MASK   0x1c0000U
#define	MMCTRL_SDCFG1_COMMAND_GET(_reg)
#define	MMCTRL_SDCFG1_COMMAND_SET(_reg, _val)
#define	MMCTRL_SDCFG1_COMMAND(_val)
#define	MMCTRL_SDCFG1_MS   0x10000U
#define	MMCTRL_SDCFG1_64   0x8000U
#define	MMCTRL_SDCFG1_RFLOAD_SHIFT   0
#define	MMCTRL_SDCFG1_RFLOAD_MASK   0x7fffU
#define	MMCTRL_SDCFG1_RFLOAD_GET(_reg)
#define	MMCTRL_SDCFG1_RFLOAD_SET(_reg, _val)
#define	MMCTRL_SDCFG1_RFLOAD(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

MMCTRL_SDCFG1_BANKSZ

#define MMCTRL_SDCFG1_BANKSZ

(

_val

)

Value:

  ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
    MMCTRL_SDCFG1_BANKSZ_MASK )

MMCTRL_SDCFG1_BANKSZ_GET

#define MMCTRL_SDCFG1_BANKSZ_GET

(

_reg

)

Value:

  ( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \
    MMCTRL_SDCFG1_BANKSZ_SHIFT )

MMCTRL_SDCFG1_BANKSZ_SET

#define MMCTRL_SDCFG1_BANKSZ_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \
    ( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
      MMCTRL_SDCFG1_BANKSZ_MASK ) )

MMCTRL_SDCFG1_COLSZ

#define MMCTRL_SDCFG1_COLSZ

(

_val

)

Value:

  ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
    MMCTRL_SDCFG1_COLSZ_MASK )

MMCTRL_SDCFG1_COLSZ_GET

#define MMCTRL_SDCFG1_COLSZ_GET

(

_reg

)

Value:

  ( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \
    MMCTRL_SDCFG1_COLSZ_SHIFT )

MMCTRL_SDCFG1_COLSZ_SET

#define MMCTRL_SDCFG1_COLSZ_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \
    ( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
      MMCTRL_SDCFG1_COLSZ_MASK ) )

MMCTRL_SDCFG1_COMMAND

#define MMCTRL_SDCFG1_COMMAND

(

_val

)

Value:

  ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
    MMCTRL_SDCFG1_COMMAND_MASK )

MMCTRL_SDCFG1_COMMAND_GET

#define MMCTRL_SDCFG1_COMMAND_GET

(

_reg

)

Value:

  ( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \
    MMCTRL_SDCFG1_COMMAND_SHIFT )

MMCTRL_SDCFG1_COMMAND_SET

#define MMCTRL_SDCFG1_COMMAND_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \
    ( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
      MMCTRL_SDCFG1_COMMAND_MASK ) )

MMCTRL_SDCFG1_RFLOAD

#define MMCTRL_SDCFG1_RFLOAD

(

_val

)

Value:

  ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
    MMCTRL_SDCFG1_RFLOAD_MASK )

MMCTRL_SDCFG1_RFLOAD_GET

#define MMCTRL_SDCFG1_RFLOAD_GET

(

_reg

)

Value:

  ( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \
    MMCTRL_SDCFG1_RFLOAD_SHIFT )

MMCTRL_SDCFG1_RFLOAD_SET

#define MMCTRL_SDCFG1_RFLOAD_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \
    ( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
      MMCTRL_SDCFG1_RFLOAD_MASK ) )

MMCTRL_SDCFG1_TRFC

#define MMCTRL_SDCFG1_TRFC

(

_val

)

Value:

  ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
    MMCTRL_SDCFG1_TRFC_MASK )

MMCTRL_SDCFG1_TRFC_GET

#define MMCTRL_SDCFG1_TRFC_GET

(

_reg

)

Value:

  ( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \
    MMCTRL_SDCFG1_TRFC_SHIFT )

MMCTRL_SDCFG1_TRFC_SET

#define MMCTRL_SDCFG1_TRFC_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \
    ( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
      MMCTRL_SDCFG1_TRFC_MASK ) )