Counter 0-15 control register (CCTRL)

This group contains register bit definitions. More...

Macros
#define	L4STAT_CCTRL_NCPU_SHIFT   28
#define	L4STAT_CCTRL_NCPU_MASK   0xf0000000U
#define	L4STAT_CCTRL_NCPU_GET(_reg)
#define	L4STAT_CCTRL_NCPU_SET(_reg, _val)
#define	L4STAT_CCTRL_NCPU(_val)
#define	L4STAT_CCTRL_NCNT_SHIFT   23
#define	L4STAT_CCTRL_NCNT_MASK   0xf800000U
#define	L4STAT_CCTRL_NCNT_GET(_reg)
#define	L4STAT_CCTRL_NCNT_SET(_reg, _val)
#define	L4STAT_CCTRL_NCNT(_val)
#define	L4STAT_CCTRL_MC   0x400000U
#define	L4STAT_CCTRL_IA   0x200000U
#define	L4STAT_CCTRL_DS   0x100000U
#define	L4STAT_CCTRL_EE   0x80000U
#define	L4STAT_CCTRL_AE   0x40000U
#define	L4STAT_CCTRL_EL   0x20000U
#define	L4STAT_CCTRL_CD   0x10000U
#define	L4STAT_CCTRL_SU_SHIFT   14
#define	L4STAT_CCTRL_SU_MASK   0xc000U
#define	L4STAT_CCTRL_SU_GET(_reg)
#define	L4STAT_CCTRL_SU_SET(_reg, _val)
#define	L4STAT_CCTRL_SU(_val)
#define	L4STAT_CCTRL_CL   0x2000U
#define	L4STAT_CCTRL_EN   0x1000U
#define	L4STAT_CCTRL_EVENT_ID_SHIFT   4
#define	L4STAT_CCTRL_EVENT_ID_MASK   0xff0U
#define	L4STAT_CCTRL_EVENT_ID_GET(_reg)
#define	L4STAT_CCTRL_EVENT_ID_SET(_reg, _val)
#define	L4STAT_CCTRL_EVENT_ID(_val)
#define	L4STAT_CCTRL_CPU_AHBM_SHIFT   0
#define	L4STAT_CCTRL_CPU_AHBM_MASK   0xfU
#define	L4STAT_CCTRL_CPU_AHBM_GET(_reg)
#define	L4STAT_CCTRL_CPU_AHBM_SET(_reg, _val)
#define	L4STAT_CCTRL_CPU_AHBM(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

L4STAT_CCTRL_CPU_AHBM

#define L4STAT_CCTRL_CPU_AHBM

(

_val

)

Value:

  ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
    L4STAT_CCTRL_CPU_AHBM_MASK )

L4STAT_CCTRL_CPU_AHBM_GET

#define L4STAT_CCTRL_CPU_AHBM_GET

(

_reg

)

Value:

  ( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \
    L4STAT_CCTRL_CPU_AHBM_SHIFT )

L4STAT_CCTRL_CPU_AHBM_SET

#define L4STAT_CCTRL_CPU_AHBM_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \
    ( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
      L4STAT_CCTRL_CPU_AHBM_MASK ) )

L4STAT_CCTRL_EVENT_ID

#define L4STAT_CCTRL_EVENT_ID

(

_val

)

Value:

  ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
    L4STAT_CCTRL_EVENT_ID_MASK )

L4STAT_CCTRL_EVENT_ID_GET

#define L4STAT_CCTRL_EVENT_ID_GET

(

_reg

)

Value:

  ( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \
    L4STAT_CCTRL_EVENT_ID_SHIFT )

L4STAT_CCTRL_EVENT_ID_SET

#define L4STAT_CCTRL_EVENT_ID_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \
    ( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
      L4STAT_CCTRL_EVENT_ID_MASK ) )

L4STAT_CCTRL_NCNT

#define L4STAT_CCTRL_NCNT

(

_val

)

Value:

  ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
    L4STAT_CCTRL_NCNT_MASK )

L4STAT_CCTRL_NCNT_GET

#define L4STAT_CCTRL_NCNT_GET

(

_reg

)

Value:

  ( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \
    L4STAT_CCTRL_NCNT_SHIFT )

L4STAT_CCTRL_NCNT_SET

#define L4STAT_CCTRL_NCNT_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \
    ( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
      L4STAT_CCTRL_NCNT_MASK ) )

L4STAT_CCTRL_NCPU

#define L4STAT_CCTRL_NCPU

(

_val

)

Value:

  ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
    L4STAT_CCTRL_NCPU_MASK )

L4STAT_CCTRL_NCPU_GET

#define L4STAT_CCTRL_NCPU_GET

(

_reg

)

Value:

  ( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \
    L4STAT_CCTRL_NCPU_SHIFT )

L4STAT_CCTRL_NCPU_SET

#define L4STAT_CCTRL_NCPU_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \
    ( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
      L4STAT_CCTRL_NCPU_MASK ) )

L4STAT_CCTRL_SU

#define L4STAT_CCTRL_SU

(

_val

)

Value:

  ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
    L4STAT_CCTRL_SU_MASK )

L4STAT_CCTRL_SU_GET

#define L4STAT_CCTRL_SU_GET

(

_reg

)

Value:

  ( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \
    L4STAT_CCTRL_SU_SHIFT )

L4STAT_CCTRL_SU_SET

#define L4STAT_CCTRL_SU_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \
    ( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
      L4STAT_CCTRL_SU_MASK ) )