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#define | GR1553B_RTMCC_RRTB_SHIFT 28 |
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#define | GR1553B_RTMCC_RRTB_MASK 0x30000000U |
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#define | GR1553B_RTMCC_RRTB_GET(_reg) |
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#define | GR1553B_RTMCC_RRTB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_RRTB(_val) |
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#define | GR1553B_RTMCC_RRT_SHIFT 26 |
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#define | GR1553B_RTMCC_RRT_MASK 0xc000000U |
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#define | GR1553B_RTMCC_RRT_GET(_reg) |
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#define | GR1553B_RTMCC_RRT_SET(_reg, _val) |
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#define | GR1553B_RTMCC_RRT(_val) |
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#define | GR1553B_RTMCC_ITFB_SHIFT 24 |
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#define | GR1553B_RTMCC_ITFB_MASK 0x3000000U |
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#define | GR1553B_RTMCC_ITFB_GET(_reg) |
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#define | GR1553B_RTMCC_ITFB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_ITFB(_val) |
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#define | GR1553B_RTMCC_ITF_SHIFT 22 |
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#define | GR1553B_RTMCC_ITF_MASK 0xc00000U |
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#define | GR1553B_RTMCC_ITF_GET(_reg) |
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#define | GR1553B_RTMCC_ITF_SET(_reg, _val) |
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#define | GR1553B_RTMCC_ITF(_val) |
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#define | GR1553B_RTMCC_ISTB_SHIFT 20 |
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#define | GR1553B_RTMCC_ISTB_MASK 0x300000U |
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#define | GR1553B_RTMCC_ISTB_GET(_reg) |
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#define | GR1553B_RTMCC_ISTB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_ISTB(_val) |
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#define | GR1553B_RTMCC_IST_SHIFT 18 |
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#define | GR1553B_RTMCC_IST_MASK 0xc0000U |
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#define | GR1553B_RTMCC_IST_GET(_reg) |
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#define | GR1553B_RTMCC_IST_SET(_reg, _val) |
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#define | GR1553B_RTMCC_IST(_val) |
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#define | GR1553B_RTMCC_DBC_SHIFT 16 |
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#define | GR1553B_RTMCC_DBC_MASK 0x30000U |
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#define | GR1553B_RTMCC_DBC_GET(_reg) |
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#define | GR1553B_RTMCC_DBC_SET(_reg, _val) |
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#define | GR1553B_RTMCC_DBC(_val) |
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#define | GR1553B_RTMCC_TBW_SHIFT 14 |
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#define | GR1553B_RTMCC_TBW_MASK 0xc000U |
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#define | GR1553B_RTMCC_TBW_GET(_reg) |
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#define | GR1553B_RTMCC_TBW_SET(_reg, _val) |
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#define | GR1553B_RTMCC_TBW(_val) |
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#define | GR1553B_RTMCC_TVW_SHIFT 12 |
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#define | GR1553B_RTMCC_TVW_MASK 0x3000U |
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#define | GR1553B_RTMCC_TVW_GET(_reg) |
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#define | GR1553B_RTMCC_TVW_SET(_reg, _val) |
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#define | GR1553B_RTMCC_TVW(_val) |
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#define | GR1553B_RTMCC_TSB_SHIFT 10 |
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#define | GR1553B_RTMCC_TSB_MASK 0xc00U |
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#define | GR1553B_RTMCC_TSB_GET(_reg) |
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#define | GR1553B_RTMCC_TSB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_TSB(_val) |
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#define | GR1553B_RTMCC_TS_SHIFT 8 |
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#define | GR1553B_RTMCC_TS_MASK 0x300U |
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#define | GR1553B_RTMCC_TS_GET(_reg) |
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#define | GR1553B_RTMCC_TS_SET(_reg, _val) |
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#define | GR1553B_RTMCC_TS(_val) |
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#define | GR1553B_RTMCC_SDB_SHIFT 6 |
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#define | GR1553B_RTMCC_SDB_MASK 0xc0U |
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#define | GR1553B_RTMCC_SDB_GET(_reg) |
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#define | GR1553B_RTMCC_SDB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_SDB(_val) |
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#define | GR1553B_RTMCC_SD_SHIFT 4 |
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#define | GR1553B_RTMCC_SD_MASK 0x30U |
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#define | GR1553B_RTMCC_SD_GET(_reg) |
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#define | GR1553B_RTMCC_SD_SET(_reg, _val) |
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#define | GR1553B_RTMCC_SD(_val) |
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#define | GR1553B_RTMCC_SB_SHIFT 2 |
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#define | GR1553B_RTMCC_SB_MASK 0xcU |
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#define | GR1553B_RTMCC_SB_GET(_reg) |
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#define | GR1553B_RTMCC_SB_SET(_reg, _val) |
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#define | GR1553B_RTMCC_SB(_val) |
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#define | GR1553B_RTMCC_S_SHIFT 0 |
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#define | GR1553B_RTMCC_S_MASK 0x3U |
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#define | GR1553B_RTMCC_S_GET(_reg) |
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#define | GR1553B_RTMCC_S_SET(_reg, _val) |
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#define | GR1553B_RTMCC_S(_val) |
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This group contains register bit definitions.