RTEMS 6.1-rc5
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Macros | |
#define | ROMC_ROMPATCHD_COUNT (8U) |
#define | ROMC_ROMPATCHA_COUNT (16U) |
ROMPATCHCNTL - ROMC Control Register | |
#define | ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) |
#define | ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) |
#define | ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) |
#define | ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) |
#define | ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) |
#define | ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) |
ROMPATCHENL - ROMC Enable Register Low | |
#define | ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) |
#define | ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) |
#define | ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) |
ROMPATCHA - ROMC Address Registers | |
#define | ROMC_ROMPATCHA_THUMBX_MASK (0x1U) |
#define | ROMC_ROMPATCHA_THUMBX_SHIFT (0U) |
#define | ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) |
#define | ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) |
#define | ROMC_ROMPATCHA_ADDRX_SHIFT (1U) |
#define | ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) |
ROMPATCHSR - ROMC Status Register | |
#define | ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) |
#define | ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) |
#define | ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) |
#define | ROMC_ROMPATCHSR_SW_MASK (0x20000U) |
#define | ROMC_ROMPATCHSR_SW_SHIFT (17U) |
#define | ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) |
#define ROMC_ROMPATCHA_THUMBX | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) |
THUMBX 0b0..Arm patch 0b1..THUMB patch (ignore if data fix)
#define ROMC_ROMPATCHCNTL_DATAFIX | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) |
DATAFIX 0b00000000..Address comparator triggers a opcode patch 0b00000001..Address comparator triggers a data fix
#define ROMC_ROMPATCHCNTL_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) |
DIS 0b0..Does not affect any ROMC functions (default) 0b1..Disable all ROMC functions: data fixing, and opcode patching
#define ROMC_ROMPATCHENL_ENABLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) |
ENABLE 0b0000000000000000..Address comparator disabled 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address
#define ROMC_ROMPATCHSR_SOURCE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) |
SOURCE 0b000000..Address Comparator 0 matched 0b000001..Address Comparator 1 matched 0b001111..Address Comparator 15 matched
#define ROMC_ROMPATCHSR_SW | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) |
SW 0b0..no event or comparator collisions 0b1..a collision has occurred