RTEMS 6.1-rc5
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BPC_AUTHEN_CTRL - BPC Authentication Control | |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
BPC_MODE - BPC Mode | |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) |
BPC_POWER_CTRL - BPC power control | |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) |
BPC_FLAG - BPC flag | |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK) |
BPC_SSAR_SAVE_CTRL - BPC SSAR save control | |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) |
BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control | |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) |
BPC_AUTHEN_CTRL - BPC Authentication Control | |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) |
#define | PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
BPC_MODE - BPC Mode | |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U) |
#define | PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) |
#define | PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) |
BPC_POWER_CTRL - BPC power control | |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) |
#define | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) |
BPC_FLAG - BPC flag | |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U) |
#define | PGMC_BPC_BPC_FLAG_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK) |
BPC_SSAR_SAVE_CTRL - BPC SSAR save control | |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) |
BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control | |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U) |
#define | PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) |
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
LOCK_CFG - Configuration lock
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK) |
LOCK_CFG - Configuration lock
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
LOCK_LIST - White list lock
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) |
LOCK_LIST - White list lock
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
LOCK_SETTING - Lock NONSECURE and USER
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) |
LOCK_SETTING - Lock NONSECURE and USER
#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) |
NONSECURE - Allow non-secure mode access 0b0..Allow only secure mode to access basic power control registers 0b1..Allow both secure and non-secure mode to access basic power control registers
#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) |
NONSECURE - Allow non-secure mode access 0b0..Allow only secure mode to access basic power control registers 0b1..Allow both secure and non-secure mode to access basic power control registers
#define PGMC_BPC_BPC_AUTHEN_CTRL_USER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) |
USER - Allow user mode access 0b0..Allow only privilege mode to access basic power control registers 0b1..Allow both privilege and user mode to access basic power control registers
#define PGMC_BPC_BPC_AUTHEN_CTRL_USER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) |
USER - Allow user mode access 0b0..Allow only privilege mode to access basic power control registers 0b1..Allow both privilege and user mode to access basic power control registers
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
WHITE_LIST - Domain ID white list
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) |
WHITE_LIST - Domain ID white list
#define PGMC_BPC_BPC_FLAG_PDN_FLAG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK) |
PDN_FLAG - set to 1 after power switch off, cleared by writing 1
#define PGMC_BPC_BPC_FLAG_PDN_FLAG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK) |
PDN_FLAG - set to 1 after power switch off, cleared by writing 1
#define PGMC_BPC_BPC_MODE_CTRL_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) |
CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved
#define PGMC_BPC_BPC_MODE_CTRL_MODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) |
CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved
#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) |
DOMAIN_ASSIGN - Domain assignment of the BPC 0b00..Domain 0 0b01..Domain 1 0b10..Domain 2 0b11..Domain 3
#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) |
DOMAIN_ASSIGN - Domain assignment of the BPC 0b00..Domain 0 0b01..Domain 1 0b10..Domain 2 0b11..Domain 3
#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) |
ISO_OFF_SOFT - Software isolation off trigger
#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) |
ISO_OFF_SOFT - Software isolation off trigger
#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) |
ISO_ON_SOFT - Software isolation on trigger
#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) |
ISO_ON_SOFT - Software isolation on trigger
#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) |
PSW_OFF_SOFT - Software power off trigger
#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) |
PSW_OFF_SOFT - Software power off trigger
#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) |
PSW_ON_SOFT - Software power on trigger
#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) |
PSW_ON_SOFT - Software power on trigger
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) |
PWR_OFF_AT_SP - Power off when system enters Setpoint number
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) |
PWR_OFF_AT_SP - Power off when system enters Setpoint number
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) |
PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) |
PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) |
PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) |
RESTORE_AT_RUN - Restore data at RUN mode
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) |
RESTORE_AT_RUN - Restore data at RUN mode
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) |
RESTORE_AT_SP - Restore data when system enters a Setpoint.
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) |
RESTORE_AT_SP - Restore data when system enters a Setpoint.
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) |
SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) |
SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) |
SAVE_AT_SP - Save data when system enters a Setpoint.
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) |
SAVE_AT_SP - Save data when system enters a Setpoint.
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) |
SAVE_AT_STOP - Save data when domain enters STOP mode
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) |
SAVE_AT_STOP - Save data when domain enters STOP mode
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) |
SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) |
SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) |
SAVE_AT_WAIT - Save data when domain enters WAIT mode
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) |
SAVE_AT_WAIT - Save data when domain enters WAIT mode