LCDIFV2 Register Masks

Macros
#define	LCDIFV2_INT_STATUS_COUNT   (2U)
#define	LCDIFV2_INT_ENABLE_COUNT   (2U)
#define	LCDIFV2_CTRLDESCL1_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL2_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL3_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL4_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL5_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL6_COUNT   (8U)
#define	LCDIFV2_CSC_COEF0_COUNT   (8U)
#define	LCDIFV2_CSC_COEF1_COUNT   (8U)
#define	LCDIFV2_CSC_COEF2_COUNT   (8U)
#define	LCDIFV2_INT_STATUS_COUNT   (2U)
#define	LCDIFV2_INT_ENABLE_COUNT   (2U)
#define	LCDIFV2_CTRLDESCL1_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL2_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL3_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL4_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL5_COUNT   (8U)
#define	LCDIFV2_CTRLDESCL6_COUNT   (8U)
#define	LCDIFV2_CSC_COEF0_COUNT   (8U)
#define	LCDIFV2_CSC_COEF1_COUNT   (8U)
#define	LCDIFV2_CSC_COEF2_COUNT   (8U)

CTRL - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
#define	LCDIFV2_CTRL_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
#define	LCDIFV2_CTRL_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
#define	LCDIFV2_CTRL_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
#define	LCDIFV2_CTRL_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)

CTRL_SET - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_SET_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_SET_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_SET_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
#define	LCDIFV2_CTRL_SET_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_SET_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_SET_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
#define	LCDIFV2_CTRL_SET_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_SET_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_SET_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
#define	LCDIFV2_CTRL_SET_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_SET_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_SET_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_SET_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_SET_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_SET_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
#define	LCDIFV2_CTRL_SET_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SET_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SET_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)

CTRL_CLR - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_CLR_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_CLR_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_CLR_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
#define	LCDIFV2_CTRL_CLR_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_CLR_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_CLR_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
#define	LCDIFV2_CTRL_CLR_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_CLR_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_CLR_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_CLR_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_CLR_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_CLR_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
#define	LCDIFV2_CTRL_CLR_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_CLR_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_CLR_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)

CTRL_TOG - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_TOG_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_TOG_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_TOG_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
#define	LCDIFV2_CTRL_TOG_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_TOG_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_TOG_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
#define	LCDIFV2_CTRL_TOG_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_TOG_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_TOG_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_TOG_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_TOG_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_TOG_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
#define	LCDIFV2_CTRL_TOG_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_TOG_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_TOG_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)

DISP_PARA - Display Parameter Register
#define	LCDIFV2_DISP_PARA_BGND_B_MASK   (0xFFU)
#define	LCDIFV2_DISP_PARA_BGND_B_SHIFT   (0U)
#define	LCDIFV2_DISP_PARA_BGND_B(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
#define	LCDIFV2_DISP_PARA_BGND_G_MASK   (0xFF00U)
#define	LCDIFV2_DISP_PARA_BGND_G_SHIFT   (8U)
#define	LCDIFV2_DISP_PARA_BGND_G(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
#define	LCDIFV2_DISP_PARA_BGND_R_MASK   (0xFF0000U)
#define	LCDIFV2_DISP_PARA_BGND_R_SHIFT   (16U)
#define	LCDIFV2_DISP_PARA_BGND_R(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
#define	LCDIFV2_DISP_PARA_DISP_MODE_MASK   (0x3000000U)
#define	LCDIFV2_DISP_PARA_DISP_MODE_SHIFT   (24U)
#define	LCDIFV2_DISP_PARA_DISP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_MASK   (0x1C000000U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT   (26U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
#define	LCDIFV2_DISP_PARA_DISP_ON_MASK   (0x80000000U)
#define	LCDIFV2_DISP_PARA_DISP_ON_SHIFT   (31U)
#define	LCDIFV2_DISP_PARA_DISP_ON(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)

DISP_SIZE - Display Size Register
#define	LCDIFV2_DISP_SIZE_DELTA_X_MASK   (0xFFFU)
#define	LCDIFV2_DISP_SIZE_DELTA_X_SHIFT   (0U)
#define	LCDIFV2_DISP_SIZE_DELTA_X(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_MASK   (0xFFF0000U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT   (16U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)

HSYN_PARA - Horizontal Sync Parameter Register
#define	LCDIFV2_HSYN_PARA_FP_H_MASK   (0x1FFU)
#define	LCDIFV2_HSYN_PARA_FP_H_SHIFT   (0U)
#define	LCDIFV2_HSYN_PARA_FP_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
#define	LCDIFV2_HSYN_PARA_PW_H_MASK   (0xFF800U)
#define	LCDIFV2_HSYN_PARA_PW_H_SHIFT   (11U)
#define	LCDIFV2_HSYN_PARA_PW_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
#define	LCDIFV2_HSYN_PARA_BP_H_MASK   (0x7FC00000U)
#define	LCDIFV2_HSYN_PARA_BP_H_SHIFT   (22U)
#define	LCDIFV2_HSYN_PARA_BP_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)

VSYN_PARA - Vertical Sync Parameter Register
#define	LCDIFV2_VSYN_PARA_FP_V_MASK   (0x1FFU)
#define	LCDIFV2_VSYN_PARA_FP_V_SHIFT   (0U)
#define	LCDIFV2_VSYN_PARA_FP_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
#define	LCDIFV2_VSYN_PARA_PW_V_MASK   (0xFF800U)
#define	LCDIFV2_VSYN_PARA_PW_V_SHIFT   (11U)
#define	LCDIFV2_VSYN_PARA_PW_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
#define	LCDIFV2_VSYN_PARA_BP_V_MASK   (0x7FC00000U)
#define	LCDIFV2_VSYN_PARA_BP_V_SHIFT   (22U)
#define	LCDIFV2_VSYN_PARA_BP_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)

INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1
#define	LCDIFV2_INT_STATUS_VSYNC_MASK   (0x1U)
#define	LCDIFV2_INT_STATUS_VSYNC_SHIFT   (0U)
#define	LCDIFV2_INT_STATUS_VSYNC(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
#define	LCDIFV2_INT_STATUS_UNDERRUN_MASK   (0x2U)
#define	LCDIFV2_INT_STATUS_UNDERRUN_SHIFT   (1U)
#define	LCDIFV2_INT_STATUS_UNDERRUN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
#define	LCDIFV2_INT_STATUS_VS_BLANK_MASK   (0x4U)
#define	LCDIFV2_INT_STATUS_VS_BLANK_SHIFT   (2U)
#define	LCDIFV2_INT_STATUS_VS_BLANK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
#define	LCDIFV2_INT_STATUS_DMA_ERR_MASK   (0xFF00U)
#define	LCDIFV2_INT_STATUS_DMA_ERR_SHIFT   (8U)
#define	LCDIFV2_INT_STATUS_DMA_ERR(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
#define	LCDIFV2_INT_STATUS_DMA_DONE_MASK   (0xFF0000U)
#define	LCDIFV2_INT_STATUS_DMA_DONE_SHIFT   (16U)
#define	LCDIFV2_INT_STATUS_DMA_DONE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK   (0xFF000000U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT   (24U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)

INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_MASK   (0x1U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT   (0U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK   (0x2U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT   (1U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK   (0x4U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT   (2U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK   (0xFF00U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT   (8U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK   (0xFF0000U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT   (16U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK   (0xFF000000U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)

PDI_PARA - Parallel Data Interface Parameter Register
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_MASK   (0x1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT   (0U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_MASK   (0x2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT   (1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_MASK   (0x4U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT   (2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK   (0x8U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT   (3U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
#define	LCDIFV2_PDI_PARA_MODE_MASK   (0xF0U)
#define	LCDIFV2_PDI_PARA_MODE_SHIFT   (4U)
#define	LCDIFV2_PDI_PARA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
#define	LCDIFV2_PDI_PARA_PDI_SEL_MASK   (0x40000000U)
#define	LCDIFV2_PDI_PARA_PDI_SEL_SHIFT   (30U)
#define	LCDIFV2_PDI_PARA_PDI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
#define	LCDIFV2_PDI_PARA_PDI_EN_MASK   (0x80000000U)
#define	LCDIFV2_PDI_PARA_PDI_EN_SHIFT   (31U)
#define	LCDIFV2_PDI_PARA_PDI_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)

CTRLDESCL1 - Control Descriptor Layer 1 Register
#define	LCDIFV2_CTRLDESCL1_WIDTH_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL1_WIDTH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL1_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)

CTRLDESCL2 - Control Descriptor Layer 2 Register
#define	LCDIFV2_CTRLDESCL2_POSX_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL2_POSX_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL2_POSX(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
#define	LCDIFV2_CTRLDESCL2_POSY_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL2_POSY_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL2_POSY(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)

CTRLDESCL3 - Control Descriptor Layer 3 Register
#define	LCDIFV2_CTRLDESCL3_PITCH_MASK   (0xFFFFU)
#define	LCDIFV2_CTRLDESCL3_PITCH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL3_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)

CTRLDESCL4 - Control Descriptor Layer 4 Register
#define	LCDIFV2_CTRLDESCL4_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIFV2_CTRLDESCL4_ADDR_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL4_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)

CTRLDESCL5 - Control Descriptor Layer 5 Register
#define	LCDIFV2_CTRLDESCL5_AB_MODE_MASK   (0x3U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT   (4U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK   (0xC0U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT   (6U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK   (0x100U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK   (0x200U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK   (0xC000U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT   (14U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
#define	LCDIFV2_CTRLDESCL5_BPP_MASK   (0xF000000U)
#define	LCDIFV2_CTRLDESCL5_BPP_SHIFT   (24U)
#define	LCDIFV2_CTRLDESCL5_BPP(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK   (0x10000000U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT   (28U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT   (30U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
#define	LCDIFV2_CTRLDESCL5_EN_MASK   (0x80000000U)
#define	LCDIFV2_CTRLDESCL5_EN_SHIFT   (31U)
#define	LCDIFV2_CTRLDESCL5_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)

CTRLDESCL6 - Control Descriptor Layer 6 Register
#define	LCDIFV2_CTRLDESCL6_BCLR_B_MASK   (0xFFU)
#define	LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL6_BCLR_B(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_MASK   (0xFF00U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)

CSC_COEF0 - Color Space Conversion Coefficient Register 0
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_MASK   (0x1FFU)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_MASK   (0x3FE00U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT   (9U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
#define	LCDIFV2_CSC_COEF0_C0_MASK   (0x1FFC0000U)
#define	LCDIFV2_CSC_COEF0_C0_SHIFT   (18U)
#define	LCDIFV2_CSC_COEF0_C0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
#define	LCDIFV2_CSC_COEF0_ENABLE_MASK   (0x40000000U)
#define	LCDIFV2_CSC_COEF0_ENABLE_SHIFT   (30U)
#define	LCDIFV2_CSC_COEF0_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK   (0x80000000U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT   (31U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)

CSC_COEF1 - Color Space Conversion Coefficient Register 1
#define	LCDIFV2_CSC_COEF1_C4_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF1_C4_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF1_C4(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
#define	LCDIFV2_CSC_COEF1_C1_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF1_C1_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF1_C1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)

CSC_COEF2 - Color Space Conversion Coefficient Register 2
#define	LCDIFV2_CSC_COEF2_C3_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF2_C3_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF2_C3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
#define	LCDIFV2_CSC_COEF2_C2_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF2_C2_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF2_C2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)

CLUT_LOAD - LCDIFv2 CLUT load Register
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK   (0x1U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK   (0x70U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT   (4U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)

CTRL - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
#define	LCDIFV2_CTRL_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
#define	LCDIFV2_CTRL_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
#define	LCDIFV2_CTRL_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
#define	LCDIFV2_CTRL_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)

CTRL_SET - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_SET_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_SET_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_SET_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
#define	LCDIFV2_CTRL_SET_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_SET_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_SET_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
#define	LCDIFV2_CTRL_SET_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_SET_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_SET_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
#define	LCDIFV2_CTRL_SET_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_SET_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_SET_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_SET_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_SET_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_SET_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
#define	LCDIFV2_CTRL_SET_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_SET_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_SET_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)

CTRL_CLR - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_CLR_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_CLR_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_CLR_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
#define	LCDIFV2_CTRL_CLR_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_CLR_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_CLR_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
#define	LCDIFV2_CTRL_CLR_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_CLR_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_CLR_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_CLR_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_CLR_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_CLR_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_CLR_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
#define	LCDIFV2_CTRL_CLR_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_CLR_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_CLR_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)

CTRL_TOG - LCDIFv2 display control Register
#define	LCDIFV2_CTRL_TOG_INV_HS_MASK   (0x1U)
#define	LCDIFV2_CTRL_TOG_INV_HS_SHIFT   (0U)
#define	LCDIFV2_CTRL_TOG_INV_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
#define	LCDIFV2_CTRL_TOG_INV_VS_MASK   (0x2U)
#define	LCDIFV2_CTRL_TOG_INV_VS_SHIFT   (1U)
#define	LCDIFV2_CTRL_TOG_INV_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
#define	LCDIFV2_CTRL_TOG_INV_DE_MASK   (0x4U)
#define	LCDIFV2_CTRL_TOG_INV_DE_SHIFT   (2U)
#define	LCDIFV2_CTRL_TOG_INV_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_MASK   (0x8U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT   (3U)
#define	LCDIFV2_CTRL_TOG_INV_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
#define	LCDIFV2_CTRL_TOG_NEG_MASK   (0x10U)
#define	LCDIFV2_CTRL_TOG_NEG_SHIFT   (4U)
#define	LCDIFV2_CTRL_TOG_NEG(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
#define	LCDIFV2_CTRL_TOG_SW_RESET_MASK   (0x80000000U)
#define	LCDIFV2_CTRL_TOG_SW_RESET_SHIFT   (31U)
#define	LCDIFV2_CTRL_TOG_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)

DISP_PARA - Display Parameter Register
#define	LCDIFV2_DISP_PARA_BGND_B_MASK   (0xFFU)
#define	LCDIFV2_DISP_PARA_BGND_B_SHIFT   (0U)
#define	LCDIFV2_DISP_PARA_BGND_B(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
#define	LCDIFV2_DISP_PARA_BGND_G_MASK   (0xFF00U)
#define	LCDIFV2_DISP_PARA_BGND_G_SHIFT   (8U)
#define	LCDIFV2_DISP_PARA_BGND_G(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
#define	LCDIFV2_DISP_PARA_BGND_R_MASK   (0xFF0000U)
#define	LCDIFV2_DISP_PARA_BGND_R_SHIFT   (16U)
#define	LCDIFV2_DISP_PARA_BGND_R(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
#define	LCDIFV2_DISP_PARA_DISP_MODE_MASK   (0x3000000U)
#define	LCDIFV2_DISP_PARA_DISP_MODE_SHIFT   (24U)
#define	LCDIFV2_DISP_PARA_DISP_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_MASK   (0x1C000000U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT   (26U)
#define	LCDIFV2_DISP_PARA_LINE_PATTERN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
#define	LCDIFV2_DISP_PARA_DISP_ON_MASK   (0x80000000U)
#define	LCDIFV2_DISP_PARA_DISP_ON_SHIFT   (31U)
#define	LCDIFV2_DISP_PARA_DISP_ON(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)

DISP_SIZE - Display Size Register
#define	LCDIFV2_DISP_SIZE_DELTA_X_MASK   (0xFFFU)
#define	LCDIFV2_DISP_SIZE_DELTA_X_SHIFT   (0U)
#define	LCDIFV2_DISP_SIZE_DELTA_X(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_MASK   (0xFFF0000U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT   (16U)
#define	LCDIFV2_DISP_SIZE_DELTA_Y(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)

HSYN_PARA - Horizontal Sync Parameter Register
#define	LCDIFV2_HSYN_PARA_FP_H_MASK   (0x1FFU)
#define	LCDIFV2_HSYN_PARA_FP_H_SHIFT   (0U)
#define	LCDIFV2_HSYN_PARA_FP_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
#define	LCDIFV2_HSYN_PARA_PW_H_MASK   (0xFF800U)
#define	LCDIFV2_HSYN_PARA_PW_H_SHIFT   (11U)
#define	LCDIFV2_HSYN_PARA_PW_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
#define	LCDIFV2_HSYN_PARA_BP_H_MASK   (0x7FC00000U)
#define	LCDIFV2_HSYN_PARA_BP_H_SHIFT   (22U)
#define	LCDIFV2_HSYN_PARA_BP_H(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)

VSYN_PARA - Vertical Sync Parameter Register
#define	LCDIFV2_VSYN_PARA_FP_V_MASK   (0x1FFU)
#define	LCDIFV2_VSYN_PARA_FP_V_SHIFT   (0U)
#define	LCDIFV2_VSYN_PARA_FP_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
#define	LCDIFV2_VSYN_PARA_PW_V_MASK   (0xFF800U)
#define	LCDIFV2_VSYN_PARA_PW_V_SHIFT   (11U)
#define	LCDIFV2_VSYN_PARA_PW_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
#define	LCDIFV2_VSYN_PARA_BP_V_MASK   (0x7FC00000U)
#define	LCDIFV2_VSYN_PARA_BP_V_SHIFT   (22U)
#define	LCDIFV2_VSYN_PARA_BP_V(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)

INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1
#define	LCDIFV2_INT_STATUS_VSYNC_MASK   (0x1U)
#define	LCDIFV2_INT_STATUS_VSYNC_SHIFT   (0U)
#define	LCDIFV2_INT_STATUS_VSYNC(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
#define	LCDIFV2_INT_STATUS_UNDERRUN_MASK   (0x2U)
#define	LCDIFV2_INT_STATUS_UNDERRUN_SHIFT   (1U)
#define	LCDIFV2_INT_STATUS_UNDERRUN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
#define	LCDIFV2_INT_STATUS_VS_BLANK_MASK   (0x4U)
#define	LCDIFV2_INT_STATUS_VS_BLANK_SHIFT   (2U)
#define	LCDIFV2_INT_STATUS_VS_BLANK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
#define	LCDIFV2_INT_STATUS_DMA_ERR_MASK   (0xFF00U)
#define	LCDIFV2_INT_STATUS_DMA_ERR_SHIFT   (8U)
#define	LCDIFV2_INT_STATUS_DMA_ERR(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
#define	LCDIFV2_INT_STATUS_DMA_DONE_MASK   (0xFF0000U)
#define	LCDIFV2_INT_STATUS_DMA_DONE_SHIFT   (16U)
#define	LCDIFV2_INT_STATUS_DMA_DONE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK   (0xFF000000U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT   (24U)
#define	LCDIFV2_INT_STATUS_FIFO_EMPTY(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)

INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_MASK   (0x1U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT   (0U)
#define	LCDIFV2_INT_ENABLE_VSYNC_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK   (0x2U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT   (1U)
#define	LCDIFV2_INT_ENABLE_UNDERRUN_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK   (0x4U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT   (2U)
#define	LCDIFV2_INT_ENABLE_VS_BLANK_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK   (0xFF00U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT   (8U)
#define	LCDIFV2_INT_ENABLE_DMA_ERR_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK   (0xFF0000U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT   (16U)
#define	LCDIFV2_INT_ENABLE_DMA_DONE_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK   (0xFF000000U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT   (24U)
#define	LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)

PDI_PARA - Parallel Data Interface Parameter Register
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_MASK   (0x1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT   (0U)
#define	LCDIFV2_PDI_PARA_INV_PDI_HS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_MASK   (0x2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT   (1U)
#define	LCDIFV2_PDI_PARA_INV_PDI_VS(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_MASK   (0x4U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT   (2U)
#define	LCDIFV2_PDI_PARA_INV_PDI_DE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK   (0x8U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT   (3U)
#define	LCDIFV2_PDI_PARA_INV_PDI_PXCK(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
#define	LCDIFV2_PDI_PARA_MODE_MASK   (0xF0U)
#define	LCDIFV2_PDI_PARA_MODE_SHIFT   (4U)
#define	LCDIFV2_PDI_PARA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
#define	LCDIFV2_PDI_PARA_PDI_SEL_MASK   (0x40000000U)
#define	LCDIFV2_PDI_PARA_PDI_SEL_SHIFT   (30U)
#define	LCDIFV2_PDI_PARA_PDI_SEL(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
#define	LCDIFV2_PDI_PARA_PDI_EN_MASK   (0x80000000U)
#define	LCDIFV2_PDI_PARA_PDI_EN_SHIFT   (31U)
#define	LCDIFV2_PDI_PARA_PDI_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)

CTRLDESCL1 - Control Descriptor Layer 1 Register
#define	LCDIFV2_CTRLDESCL1_WIDTH_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL1_WIDTH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL1_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL1_HEIGHT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)

CTRLDESCL2 - Control Descriptor Layer 2 Register
#define	LCDIFV2_CTRLDESCL2_POSX_MASK   (0xFFFU)
#define	LCDIFV2_CTRLDESCL2_POSX_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL2_POSX(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
#define	LCDIFV2_CTRLDESCL2_POSY_MASK   (0xFFF0000U)
#define	LCDIFV2_CTRLDESCL2_POSY_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL2_POSY(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)

CTRLDESCL3 - Control Descriptor Layer 3 Register
#define	LCDIFV2_CTRLDESCL3_PITCH_MASK   (0xFFFFU)
#define	LCDIFV2_CTRLDESCL3_PITCH_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL3_PITCH(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)

CTRLDESCL4 - Control Descriptor Layer 4 Register
#define	LCDIFV2_CTRLDESCL4_ADDR_MASK   (0xFFFFFFFFU)
#define	LCDIFV2_CTRLDESCL4_ADDR_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL4_ADDR(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)

CTRLDESCL5 - Control Descriptor Layer 5 Register
#define	LCDIFV2_CTRLDESCL5_AB_MODE_MASK   (0x3U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL5_AB_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK   (0x30U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT   (4U)
#define	LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK   (0xC0U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT   (6U)
#define	LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK   (0x100U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK   (0x200U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT   (9U)
#define	LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK   (0xC000U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT   (14U)
#define	LCDIFV2_CTRLDESCL5_YUV_FORMAT(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
#define	LCDIFV2_CTRLDESCL5_BPP_MASK   (0xF000000U)
#define	LCDIFV2_CTRLDESCL5_BPP_SHIFT   (24U)
#define	LCDIFV2_CTRLDESCL5_BPP(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK   (0x10000000U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT   (28U)
#define	LCDIFV2_CTRLDESCL5_SAFETY_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK   (0x40000000U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT   (30U)
#define	LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
#define	LCDIFV2_CTRLDESCL5_EN_MASK   (0x80000000U)
#define	LCDIFV2_CTRLDESCL5_EN_SHIFT   (31U)
#define	LCDIFV2_CTRLDESCL5_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)

CTRLDESCL6 - Control Descriptor Layer 6 Register
#define	LCDIFV2_CTRLDESCL6_BCLR_B_MASK   (0xFFU)
#define	LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT   (0U)
#define	LCDIFV2_CTRLDESCL6_BCLR_B(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_MASK   (0xFF00U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT   (8U)
#define	LCDIFV2_CTRLDESCL6_BCLR_G(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_MASK   (0xFF0000U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT   (16U)
#define	LCDIFV2_CTRLDESCL6_BCLR_R(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)

CSC_COEF0 - Color Space Conversion Coefficient Register 0
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_MASK   (0x1FFU)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF0_Y_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_MASK   (0x3FE00U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT   (9U)
#define	LCDIFV2_CSC_COEF0_UV_OFFSET(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
#define	LCDIFV2_CSC_COEF0_C0_MASK   (0x1FFC0000U)
#define	LCDIFV2_CSC_COEF0_C0_SHIFT   (18U)
#define	LCDIFV2_CSC_COEF0_C0(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
#define	LCDIFV2_CSC_COEF0_ENABLE_MASK   (0x40000000U)
#define	LCDIFV2_CSC_COEF0_ENABLE_SHIFT   (30U)
#define	LCDIFV2_CSC_COEF0_ENABLE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK   (0x80000000U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT   (31U)
#define	LCDIFV2_CSC_COEF0_YCBCR_MODE(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)

CSC_COEF1 - Color Space Conversion Coefficient Register 1
#define	LCDIFV2_CSC_COEF1_C4_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF1_C4_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF1_C4(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
#define	LCDIFV2_CSC_COEF1_C1_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF1_C1_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF1_C1(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)

CSC_COEF2 - Color Space Conversion Coefficient Register 2
#define	LCDIFV2_CSC_COEF2_C3_MASK   (0x7FFU)
#define	LCDIFV2_CSC_COEF2_C3_SHIFT   (0U)
#define	LCDIFV2_CSC_COEF2_C3(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
#define	LCDIFV2_CSC_COEF2_C2_MASK   (0x7FF0000U)
#define	LCDIFV2_CSC_COEF2_C2_SHIFT   (16U)
#define	LCDIFV2_CSC_COEF2_C2(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)

CLUT_LOAD - LCDIFv2 CLUT load Register
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK   (0x1U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT   (0U)
#define	LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK   (0x70U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT   (4U)
#define	LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x)   (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)

Detailed Description

Macro Definition Documentation

LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN [1/2]

#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)

CLUT_UPDATE_EN - CLUT Update Enable

LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN [2/2]

#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)

CLUT_UPDATE_EN - CLUT Update Enable

LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM [1/2]

#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)

SEL_CLUT_NUM - Selected CLUT Number

LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM [2/2]

#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)

SEL_CLUT_NUM - Selected CLUT Number

LCDIFV2_CSC_COEF0_C0 [1/2]

#define LCDIFV2_CSC_COEF0_C0

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)

C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)

LCDIFV2_CSC_COEF0_C0 [2/2]

#define LCDIFV2_CSC_COEF0_C0

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)

C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)

LCDIFV2_CSC_COEF0_ENABLE [1/2]

#define LCDIFV2_CSC_COEF0_ENABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)

ENABLE - Enable the CSC unit in the LCDIFv2 plane data path 0b0..The CSC is bypassed and the input pixels are RGB data already 0b1..The CSC is enabled and the pixels will be converted to RGB data

LCDIFV2_CSC_COEF0_ENABLE [2/2]

#define LCDIFV2_CSC_COEF0_ENABLE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)

ENABLE - Enable the CSC unit in the LCDIFv2 plane data path 0b0..The CSC is bypassed and the input pixels are RGB data already 0b1..The CSC is enabled and the pixels will be converted to RGB data

LCDIFV2_CSC_COEF0_UV_OFFSET [1/2]

#define LCDIFV2_CSC_COEF0_UV_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)

UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range)

LCDIFV2_CSC_COEF0_UV_OFFSET [2/2]

#define LCDIFV2_CSC_COEF0_UV_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)

UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range)

LCDIFV2_CSC_COEF0_Y_OFFSET [1/2]

#define LCDIFV2_CSC_COEF0_Y_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)

Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0)

LCDIFV2_CSC_COEF0_Y_OFFSET [2/2]

#define LCDIFV2_CSC_COEF0_Y_OFFSET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)

Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is typically -16 (0x1F0)

LCDIFV2_CSC_COEF0_YCBCR_MODE [1/2]

#define LCDIFV2_CSC_COEF0_YCBCR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)

YCBCR_MODE - This bit changes the behavior when performing U/V converting 0b0..Converting YUV to RGB data 0b1..Converting YCbCr to RGB data

LCDIFV2_CSC_COEF0_YCBCR_MODE [2/2]

#define LCDIFV2_CSC_COEF0_YCBCR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)

YCBCR_MODE - This bit changes the behavior when performing U/V converting 0b0..Converting YUV to RGB data 0b1..Converting YCbCr to RGB data

LCDIFV2_CSC_COEF1_C1 [1/2]

#define LCDIFV2_CSC_COEF1_C1

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)

C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)

LCDIFV2_CSC_COEF1_C1 [2/2]

#define LCDIFV2_CSC_COEF1_C1

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)

C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)

LCDIFV2_CSC_COEF1_C4 [1/2]

#define LCDIFV2_CSC_COEF1_C4

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)

C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)

LCDIFV2_CSC_COEF1_C4 [2/2]

#define LCDIFV2_CSC_COEF1_C4

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)

C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)

LCDIFV2_CSC_COEF2_C2 [1/2]

#define LCDIFV2_CSC_COEF2_C2

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)

C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)

LCDIFV2_CSC_COEF2_C2 [2/2]

#define LCDIFV2_CSC_COEF2_C2

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)

C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)

LCDIFV2_CSC_COEF2_C3 [1/2]

#define LCDIFV2_CSC_COEF2_C3

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)

C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)

LCDIFV2_CSC_COEF2_C3 [2/2]

#define LCDIFV2_CSC_COEF2_C3

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)

C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)

LCDIFV2_CTRL_CLR_INV_DE [1/2]

#define LCDIFV2_CTRL_CLR_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_CLR_INV_DE [2/2]

#define LCDIFV2_CTRL_CLR_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_CLR_INV_HS [1/2]

#define LCDIFV2_CTRL_CLR_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_CLR_INV_HS [2/2]

#define LCDIFV2_CTRL_CLR_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_CLR_INV_PXCK [1/2]

#define LCDIFV2_CTRL_CLR_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_CLR_INV_PXCK [2/2]

#define LCDIFV2_CTRL_CLR_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_CLR_INV_VS [1/2]

#define LCDIFV2_CTRL_CLR_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_CLR_INV_VS [2/2]

#define LCDIFV2_CTRL_CLR_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_CLR_NEG [1/2]

#define LCDIFV2_CTRL_CLR_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_CLR_NEG [2/2]

#define LCDIFV2_CTRL_CLR_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_CLR_SW_RESET [1/2]

#define LCDIFV2_CTRL_CLR_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRL_CLR_SW_RESET [2/2]

#define LCDIFV2_CTRL_CLR_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRL_INV_DE [1/2]

#define LCDIFV2_CTRL_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)

INV_DE - Invert Data Enable polarity 0b0..Data enable is active high 0b1..Data enable is active low

LCDIFV2_CTRL_INV_DE [2/2]

#define LCDIFV2_CTRL_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)

INV_DE - Invert Data Enable polarity 0b0..Data enable is active high 0b1..Data enable is active low

LCDIFV2_CTRL_INV_HS [1/2]

#define LCDIFV2_CTRL_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal 0b0..HSYNC signal not inverted (active HIGH) 0b1..Invert HSYNC signal (active LOW)

LCDIFV2_CTRL_INV_HS [2/2]

#define LCDIFV2_CTRL_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal 0b0..HSYNC signal not inverted (active HIGH) 0b1..Invert HSYNC signal (active LOW)

LCDIFV2_CTRL_INV_PXCK [1/2]

#define LCDIFV2_CTRL_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock 0b0..Display samples data on the falling edge 0b1..Display samples data on the rising edge

LCDIFV2_CTRL_INV_PXCK [2/2]

#define LCDIFV2_CTRL_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock 0b0..Display samples data on the falling edge 0b1..Display samples data on the rising edge

LCDIFV2_CTRL_INV_VS [1/2]

#define LCDIFV2_CTRL_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal 0b0..VSYNC signal not inverted (active HIGH) 0b1..Invert VSYNC signal (active LOW)

LCDIFV2_CTRL_INV_VS [2/2]

#define LCDIFV2_CTRL_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal 0b0..VSYNC signal not inverted (active HIGH) 0b1..Invert VSYNC signal (active LOW)

LCDIFV2_CTRL_NEG [1/2]

#define LCDIFV2_CTRL_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated 0b0..Output is to remain same 0b1..Output to be negated

LCDIFV2_CTRL_NEG [2/2]

#define LCDIFV2_CTRL_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated 0b0..Output is to remain same 0b1..Output to be negated

LCDIFV2_CTRL_SET_INV_DE [1/2]

#define LCDIFV2_CTRL_SET_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_SET_INV_DE [2/2]

#define LCDIFV2_CTRL_SET_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_SET_INV_HS [1/2]

#define LCDIFV2_CTRL_SET_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_SET_INV_HS [2/2]

#define LCDIFV2_CTRL_SET_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_SET_INV_PXCK [1/2]

#define LCDIFV2_CTRL_SET_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_SET_INV_PXCK [2/2]

#define LCDIFV2_CTRL_SET_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_SET_INV_VS [1/2]

#define LCDIFV2_CTRL_SET_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_SET_INV_VS [2/2]

#define LCDIFV2_CTRL_SET_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_SET_NEG [1/2]

#define LCDIFV2_CTRL_SET_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_SET_NEG [2/2]

#define LCDIFV2_CTRL_SET_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_SET_SW_RESET [1/2]

#define LCDIFV2_CTRL_SET_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRL_SET_SW_RESET [2/2]

#define LCDIFV2_CTRL_SET_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRL_SW_RESET [1/2]

#define LCDIFV2_CTRL_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)

SW_RESET - Software Reset 0b0..No action 0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected

LCDIFV2_CTRL_SW_RESET [2/2]

#define LCDIFV2_CTRL_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)

SW_RESET - Software Reset 0b0..No action 0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected

LCDIFV2_CTRL_TOG_INV_DE [1/2]

#define LCDIFV2_CTRL_TOG_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_TOG_INV_DE [2/2]

#define LCDIFV2_CTRL_TOG_INV_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)

INV_DE - Invert Data Enable polarity

LCDIFV2_CTRL_TOG_INV_HS [1/2]

#define LCDIFV2_CTRL_TOG_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_TOG_INV_HS [2/2]

#define LCDIFV2_CTRL_TOG_INV_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)

INV_HS - Invert Horizontal synchronization signal

LCDIFV2_CTRL_TOG_INV_PXCK [1/2]

#define LCDIFV2_CTRL_TOG_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_TOG_INV_PXCK [2/2]

#define LCDIFV2_CTRL_TOG_INV_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)

INV_PXCK - Polarity change of Pixel Clock

LCDIFV2_CTRL_TOG_INV_VS [1/2]

#define LCDIFV2_CTRL_TOG_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_TOG_INV_VS [2/2]

#define LCDIFV2_CTRL_TOG_INV_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)

INV_VS - Invert Vertical synchronization signal

LCDIFV2_CTRL_TOG_NEG [1/2]

#define LCDIFV2_CTRL_TOG_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_TOG_NEG [2/2]

#define LCDIFV2_CTRL_TOG_NEG

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)

NEG - Indicates if value at the output (pixel data output) needs to be negated

LCDIFV2_CTRL_TOG_SW_RESET [1/2]

#define LCDIFV2_CTRL_TOG_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRL_TOG_SW_RESET [2/2]

#define LCDIFV2_CTRL_TOG_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)

SW_RESET - Software Reset

LCDIFV2_CTRLDESCL1_HEIGHT [1/2]

#define LCDIFV2_CTRLDESCL1_HEIGHT

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)

HEIGHT - Height of the layer in pixels

LCDIFV2_CTRLDESCL1_HEIGHT [2/2]

#define LCDIFV2_CTRLDESCL1_HEIGHT

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)

HEIGHT - Height of the layer in pixels

LCDIFV2_CTRLDESCL1_WIDTH [1/2]

#define LCDIFV2_CTRLDESCL1_WIDTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)

WIDTH - Width of the layer in pixels

LCDIFV2_CTRLDESCL1_WIDTH [2/2]

#define LCDIFV2_CTRLDESCL1_WIDTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)

WIDTH - Width of the layer in pixels

LCDIFV2_CTRLDESCL2_POSX [1/2]

#define LCDIFV2_CTRLDESCL2_POSX

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)

POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel

LCDIFV2_CTRLDESCL2_POSX [2/2]

#define LCDIFV2_CTRLDESCL2_POSX

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)

POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, only positive values are to the right the left-hand column of the panel

LCDIFV2_CTRLDESCL2_POSY [1/2]

#define LCDIFV2_CTRLDESCL2_POSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)

POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel

LCDIFV2_CTRLDESCL2_POSY [2/2]

#define LCDIFV2_CTRLDESCL2_POSY

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)

POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only positive values are below the top row of the panel

LCDIFV2_CTRLDESCL3_PITCH [1/2]

#define LCDIFV2_CTRLDESCL3_PITCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)

PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry

LCDIFV2_CTRLDESCL3_PITCH [2/2]

#define LCDIFV2_CTRLDESCL3_PITCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)

PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundry

LCDIFV2_CTRLDESCL4_ADDR [1/2]

#define LCDIFV2_CTRLDESCL4_ADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)

ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned

LCDIFV2_CTRLDESCL4_ADDR [2/2]

#define LCDIFV2_CTRLDESCL4_ADDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)

ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned

LCDIFV2_CTRLDESCL5_AB_MODE [1/2]

#define LCDIFV2_CTRLDESCL5_AB_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)

AB_MODE - Alpha Blending Mode 0b00..No alpha Blending (The SAFETY_EN bit need set to 1) 0b01..Blend with global ALPHA 0b10..Blend with embedded ALPHA 0b11..Blend with PoterDuff enable

LCDIFV2_CTRLDESCL5_AB_MODE [2/2]

#define LCDIFV2_CTRLDESCL5_AB_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)

AB_MODE - Alpha Blending Mode 0b00..No alpha Blending (The SAFETY_EN bit need set to 1) 0b01..Blend with global ALPHA 0b10..Blend with embedded ALPHA 0b11..Blend with PoterDuff enable

LCDIFV2_CTRLDESCL5_BPP [1/2]

#define LCDIFV2_CTRLDESCL5_BPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)

BPP - Layer encoding format (bit per pixel) 0b0000..1 bpp 0b0001..2 bpp 0b0010..4 bpp 0b0011..8 bpp 0b0100..16 bpp (RGB565) 0b0101..16 bpp (ARGB1555) 0b0110..16 bpp (ARGB4444) 0b0111..YCbCr422 (Only layer 0/1 can support this format) 0b1000..24 bpp (RGB888) 0b1001..32 bpp (ARGB8888) 0b1010..32 bpp (ABGR8888)

LCDIFV2_CTRLDESCL5_BPP [2/2]

#define LCDIFV2_CTRLDESCL5_BPP

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)

BPP - Layer encoding format (bit per pixel) 0b0000..1 bpp 0b0001..2 bpp 0b0010..4 bpp 0b0011..8 bpp 0b0100..16 bpp (RGB565) 0b0101..16 bpp (ARGB1555) 0b0110..16 bpp (ARGB4444) 0b0111..YCbCr422 (Only layer 0/1 can support this format) 0b1000..24 bpp (RGB888) 0b1001..32 bpp (ARGB8888) 0b1010..32 bpp (ABGR8888)

LCDIFV2_CTRLDESCL5_EN [1/2]

#define LCDIFV2_CTRLDESCL5_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)

EN - Enable the layer for DMA 0b0..OFF 0b1..ON

LCDIFV2_CTRLDESCL5_EN [2/2]

#define LCDIFV2_CTRLDESCL5_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)

EN - Enable the layer for DMA 0b0..OFF 0b1..ON

LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA [1/2]

#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)

GLOBAL_ALPHA - Global Alpha

LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA [2/2]

#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)

GLOBAL_ALPHA - Global Alpha

LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE [1/2]

#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)

PD_ALPHA_MODE - PoterDuff alpha mode 0b0..Straight mode for Porter Duff alpha 0b1..Inversed mode for Porter Duff alpha

LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE [2/2]

#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)

PD_ALPHA_MODE - PoterDuff alpha mode 0b0..Straight mode for Porter Duff alpha 0b1..Inversed mode for Porter Duff alpha

LCDIFV2_CTRLDESCL5_PD_COLOR_MODE [1/2]

#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)

PD_COLOR_MODE - PoterDuff alpha mode 0b0..Straight mode for Porter Duff color 0b1..Inversed mode for Porter Duff color

LCDIFV2_CTRLDESCL5_PD_COLOR_MODE [2/2]

#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)

PD_COLOR_MODE - PoterDuff alpha mode 0b0..Straight mode for Porter Duff color 0b1..Inversed mode for Porter Duff color

LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE [1/2]

#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)

PD_FACTOR_MODE - PoterDuff factor mode 0b00..Using 1 0b01..Using 0 0b10..Using straight alpha 0b11..Using inverse alpha

LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE [2/2]

#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)

PD_FACTOR_MODE - PoterDuff factor mode 0b00..Using 1 0b01..Using 0 0b10..Using straight alpha 0b11..Using inverse alpha

LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE [1/2]

#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)

PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode 0b00..Using global alpha 0b01..Using local alpha 0b10..Using scaled alpha 0b11..Using scaled alpha

LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE [2/2]

#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)

PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode 0b00..Using global alpha 0b01..Using local alpha 0b10..Using scaled alpha 0b11..Using scaled alpha

LCDIFV2_CTRLDESCL5_SAFETY_EN [1/2]

#define LCDIFV2_CTRLDESCL5_SAFETY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)

SAFETY_EN - Safety Mode Enable Bit 0b0..Safety Mode is disabled 0b1..Safety Mode is enabled for this layer

LCDIFV2_CTRLDESCL5_SAFETY_EN [2/2]

#define LCDIFV2_CTRLDESCL5_SAFETY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)

SAFETY_EN - Safety Mode Enable Bit 0b0..Safety Mode is disabled 0b1..Safety Mode is enabled for this layer

LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN [1/2]

#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)

SHADOW_LOAD_EN - Shadow Load Enable

LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN [2/2]

#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)

SHADOW_LOAD_EN - Shadow Load Enable

LCDIFV2_CTRLDESCL5_YUV_FORMAT [1/2]

#define LCDIFV2_CTRLDESCL5_YUV_FORMAT

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)

YUV_FORMAT - The YUV422 input format selection 0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2 0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2 0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1 0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1

LCDIFV2_CTRLDESCL5_YUV_FORMAT [2/2]

#define LCDIFV2_CTRLDESCL5_YUV_FORMAT

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)

YUV_FORMAT - The YUV422 input format selection 0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2 0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2 0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1 0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1

LCDIFV2_CTRLDESCL6_BCLR_B [1/2]

#define LCDIFV2_CTRLDESCL6_BCLR_B

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)

BCLR_B - Background B component value

LCDIFV2_CTRLDESCL6_BCLR_B [2/2]

#define LCDIFV2_CTRLDESCL6_BCLR_B

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)

BCLR_B - Background B component value

LCDIFV2_CTRLDESCL6_BCLR_G [1/2]

#define LCDIFV2_CTRLDESCL6_BCLR_G

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)

BCLR_G - Background G component value

LCDIFV2_CTRLDESCL6_BCLR_G [2/2]

#define LCDIFV2_CTRLDESCL6_BCLR_G

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)

BCLR_G - Background G component value

LCDIFV2_CTRLDESCL6_BCLR_R [1/2]

#define LCDIFV2_CTRLDESCL6_BCLR_R

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)

BCLR_R - Background R component value

LCDIFV2_CTRLDESCL6_BCLR_R [2/2]

#define LCDIFV2_CTRLDESCL6_BCLR_R

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)

BCLR_R - Background R component value

LCDIFV2_DISP_PARA_BGND_B [1/2]

#define LCDIFV2_DISP_PARA_BGND_B

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)

BGND_B - Blue component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_BGND_B [2/2]

#define LCDIFV2_DISP_PARA_BGND_B

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)

BGND_B - Blue component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_BGND_G [1/2]

#define LCDIFV2_DISP_PARA_BGND_G

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)

BGND_G - Green component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_BGND_G [2/2]

#define LCDIFV2_DISP_PARA_BGND_G

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)

BGND_G - Green component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_BGND_R [1/2]

#define LCDIFV2_DISP_PARA_BGND_R

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)

BGND_R - Red component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_BGND_R [2/2]

#define LCDIFV2_DISP_PARA_BGND_R

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)

BGND_R - Red component of the default color displayed in the sectors where no layer is active

LCDIFV2_DISP_PARA_DISP_MODE [1/2]

#define LCDIFV2_DISP_PARA_DISP_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)

DISP_MODE - LCDIFv2 operating mode 0b00..Normal mode. Panel content controlled by layer configuration 0b01..Test Mode1(BGND Color Display) 0b10..Test Mode2(Column Color Bar) 0b11..Test Mode3(Row Color Bar)

LCDIFV2_DISP_PARA_DISP_MODE [2/2]

#define LCDIFV2_DISP_PARA_DISP_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)

DISP_MODE - LCDIFv2 operating mode 0b00..Normal mode. Panel content controlled by layer configuration 0b01..Test Mode1(BGND Color Display) 0b10..Test Mode2(Column Color Bar) 0b11..Test Mode3(Row Color Bar)

LCDIFV2_DISP_PARA_DISP_ON [1/2]

#define LCDIFV2_DISP_PARA_DISP_ON

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)

DISP_ON - Display panel On/Off mode 0b0..Display Off 0b1..Display On

LCDIFV2_DISP_PARA_DISP_ON [2/2]

#define LCDIFV2_DISP_PARA_DISP_ON

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)

DISP_ON - Display panel On/Off mode 0b0..Display Off 0b1..Display On

LCDIFV2_DISP_PARA_LINE_PATTERN [1/2]

#define LCDIFV2_DISP_PARA_LINE_PATTERN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)

LINE_PATTERN - LCDIFv2 line output order 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

LCDIFV2_DISP_PARA_LINE_PATTERN [2/2]

#define LCDIFV2_DISP_PARA_LINE_PATTERN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)

LINE_PATTERN - LCDIFv2 line output order 0b000..RGB 0b001..RBG 0b010..GBR 0b011..GRB 0b100..BRG 0b101..BGR

LCDIFV2_DISP_SIZE_DELTA_X [1/2]

#define LCDIFV2_DISP_SIZE_DELTA_X

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)

DELTA_X - Sets the display size horizontal resolution in pixels

LCDIFV2_DISP_SIZE_DELTA_X [2/2]

#define LCDIFV2_DISP_SIZE_DELTA_X

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)

DELTA_X - Sets the display size horizontal resolution in pixels

LCDIFV2_DISP_SIZE_DELTA_Y [1/2]

#define LCDIFV2_DISP_SIZE_DELTA_Y

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)

DELTA_Y - Sets the display size vertical resolution in pixels

LCDIFV2_DISP_SIZE_DELTA_Y [2/2]

#define LCDIFV2_DISP_SIZE_DELTA_Y

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)

DELTA_Y - Sets the display size vertical resolution in pixels

LCDIFV2_HSYN_PARA_BP_H [1/2]

#define LCDIFV2_HSYN_PARA_BP_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)

BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_HSYN_PARA_BP_H [2/2]

#define LCDIFV2_HSYN_PARA_BP_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)

BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_HSYN_PARA_FP_H [1/2]

#define LCDIFV2_HSYN_PARA_FP_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)

FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_HSYN_PARA_FP_H [2/2]

#define LCDIFV2_HSYN_PARA_FP_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)

FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_HSYN_PARA_PW_H [1/2]

#define LCDIFV2_HSYN_PARA_PW_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)

PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_HSYN_PARA_PW_H [2/2]

#define LCDIFV2_HSYN_PARA_PW_H

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)

PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1

LCDIFV2_INT_ENABLE_DMA_DONE_EN [1/2]

#define LCDIFV2_INT_ENABLE_DMA_DONE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)

DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory

LCDIFV2_INT_ENABLE_DMA_DONE_EN [2/2]

#define LCDIFV2_INT_ENABLE_DMA_DONE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)

DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory

LCDIFV2_INT_ENABLE_DMA_ERR_EN [1/2]

#define LCDIFV2_INT_ENABLE_DMA_ERR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)

DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface

LCDIFV2_INT_ENABLE_DMA_ERR_EN [2/2]

#define LCDIFV2_INT_ENABLE_DMA_ERR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)

DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface

LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN [1/2]

#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)

FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed

LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN [2/2]

#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)

FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed

LCDIFV2_INT_ENABLE_UNDERRUN_EN [1/2]

#define LCDIFV2_INT_ENABLE_UNDERRUN_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)

UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition 0b0..Output buffer underrun disable 0b1..Output buffer underrun enable

LCDIFV2_INT_ENABLE_UNDERRUN_EN [2/2]

#define LCDIFV2_INT_ENABLE_UNDERRUN_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)

UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition 0b0..Output buffer underrun disable 0b1..Output buffer underrun enable

LCDIFV2_INT_ENABLE_VS_BLANK_EN [1/2]

#define LCDIFV2_INT_ENABLE_VS_BLANK_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)

VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period 0b0..Vertical blanking start interrupt disable 0b1..Vertical blanking start interrupt enable

LCDIFV2_INT_ENABLE_VS_BLANK_EN [2/2]

#define LCDIFV2_INT_ENABLE_VS_BLANK_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)

VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period 0b0..Vertical blanking start interrupt disable 0b1..Vertical blanking start interrupt enable

LCDIFV2_INT_ENABLE_VSYNC_EN [1/2]

#define LCDIFV2_INT_ENABLE_VSYNC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)

VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0b0..VSYNC interrupt disable 0b1..VSYNC interrupt enable

LCDIFV2_INT_ENABLE_VSYNC_EN [2/2]

#define LCDIFV2_INT_ENABLE_VSYNC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)

VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0b0..VSYNC interrupt disable 0b1..VSYNC interrupt enable

LCDIFV2_INT_STATUS_DMA_DONE [1/2]

#define LCDIFV2_INT_STATUS_DMA_DONE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)

DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory

LCDIFV2_INT_STATUS_DMA_DONE [2/2]

#define LCDIFV2_INT_STATUS_DMA_DONE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)

DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory

LCDIFV2_INT_STATUS_DMA_ERR [1/2]

#define LCDIFV2_INT_STATUS_DMA_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)

DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface

LCDIFV2_INT_STATUS_DMA_ERR [2/2]

#define LCDIFV2_INT_STATUS_DMA_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)

DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface

LCDIFV2_INT_STATUS_FIFO_EMPTY [1/2]

#define LCDIFV2_INT_STATUS_FIFO_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)

FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed

LCDIFV2_INT_STATUS_FIFO_EMPTY [2/2]

#define LCDIFV2_INT_STATUS_FIFO_EMPTY

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)

FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed

LCDIFV2_INT_STATUS_UNDERRUN [1/2]

#define LCDIFV2_INT_STATUS_UNDERRUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)

UNDERRUN - Interrupt flag to indicate the output buffer underrun condition 0b0..Output buffer not underrun 0b1..Output buffer underrun

LCDIFV2_INT_STATUS_UNDERRUN [2/2]

#define LCDIFV2_INT_STATUS_UNDERRUN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)

UNDERRUN - Interrupt flag to indicate the output buffer underrun condition 0b0..Output buffer not underrun 0b1..Output buffer underrun

LCDIFV2_INT_STATUS_VS_BLANK [1/2]

#define LCDIFV2_INT_STATUS_VS_BLANK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)

VS_BLANK - Interrupt flag to indicate vertical blanking period 0b0..Vertical blanking period has not started 0b1..Vertical blanking period has started

LCDIFV2_INT_STATUS_VS_BLANK [2/2]

#define LCDIFV2_INT_STATUS_VS_BLANK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)

VS_BLANK - Interrupt flag to indicate vertical blanking period 0b0..Vertical blanking period has not started 0b1..Vertical blanking period has started

LCDIFV2_INT_STATUS_VSYNC [1/2]

#define LCDIFV2_INT_STATUS_VSYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)

VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0b0..VSYNC has not started 0b1..VSYNC has started

LCDIFV2_INT_STATUS_VSYNC [2/2]

#define LCDIFV2_INT_STATUS_VSYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)

VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) 0b0..VSYNC has not started 0b1..VSYNC has started

LCDIFV2_PDI_PARA_INV_PDI_DE [1/2]

#define LCDIFV2_PDI_PARA_INV_PDI_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)

INV_PDI_DE - Polarity of PDI input Data Enable 0b0..Data enable is active HIGH 0b1..Data enable is active LOW

LCDIFV2_PDI_PARA_INV_PDI_DE [2/2]

#define LCDIFV2_PDI_PARA_INV_PDI_DE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)

INV_PDI_DE - Polarity of PDI input Data Enable 0b0..Data enable is active HIGH 0b1..Data enable is active LOW

LCDIFV2_PDI_PARA_INV_PDI_HS [1/2]

#define LCDIFV2_PDI_PARA_INV_PDI_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)

INV_PDI_HS - Polarity of PDI input HSYNC 0b0..HSYNC is active HIGH 0b1..HSYNC is active LOW

LCDIFV2_PDI_PARA_INV_PDI_HS [2/2]

#define LCDIFV2_PDI_PARA_INV_PDI_HS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)

INV_PDI_HS - Polarity of PDI input HSYNC 0b0..HSYNC is active HIGH 0b1..HSYNC is active LOW

LCDIFV2_PDI_PARA_INV_PDI_PXCK [1/2]

#define LCDIFV2_PDI_PARA_INV_PDI_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)

INV_PDI_PXCK - Polarity of PDI input Pixel Clock 0b0..Samples data on the falling edge 0b1..Samples data on the rising edge

LCDIFV2_PDI_PARA_INV_PDI_PXCK [2/2]

#define LCDIFV2_PDI_PARA_INV_PDI_PXCK

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)

INV_PDI_PXCK - Polarity of PDI input Pixel Clock 0b0..Samples data on the falling edge 0b1..Samples data on the rising edge

LCDIFV2_PDI_PARA_INV_PDI_VS [1/2]

#define LCDIFV2_PDI_PARA_INV_PDI_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)

INV_PDI_VS - Polarity of PDI input VSYNC 0b0..VSYNC is active HIGH 0b1..VSYNC is active LOW

LCDIFV2_PDI_PARA_INV_PDI_VS [2/2]

#define LCDIFV2_PDI_PARA_INV_PDI_VS

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)

INV_PDI_VS - Polarity of PDI input VSYNC 0b0..VSYNC is active HIGH 0b1..VSYNC is active LOW

LCDIFV2_PDI_PARA_MODE [1/2]

#define LCDIFV2_PDI_PARA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)

MODE - The PDI mode for input data format 0b0000..32 bpp (ARGB8888) 0b0001..24 bpp (RGB888) 0b0010..24 bpp (RGB666) 0b0011..16 bpp (RGB565) 0b0100..16 bpp (RGB444) 0b0101..16 bpp (RGB555) 0b0110..16 bpp (YCbCr422)

LCDIFV2_PDI_PARA_MODE [2/2]

#define LCDIFV2_PDI_PARA_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)

MODE - The PDI mode for input data format 0b0000..32 bpp (ARGB8888) 0b0001..24 bpp (RGB888) 0b0010..24 bpp (RGB666) 0b0011..16 bpp (RGB565) 0b0100..16 bpp (RGB444) 0b0101..16 bpp (RGB555) 0b0110..16 bpp (YCbCr422)

LCDIFV2_PDI_PARA_PDI_EN [1/2]

#define LCDIFV2_PDI_PARA_PDI_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)

PDI_EN - Enable PDI input data to LCDIFv2 display 0b0..Disable PDI input data 0b1..Enable PDI input data

LCDIFV2_PDI_PARA_PDI_EN [2/2]

#define LCDIFV2_PDI_PARA_PDI_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)

PDI_EN - Enable PDI input data to LCDIFv2 display 0b0..Disable PDI input data 0b1..Enable PDI input data

LCDIFV2_PDI_PARA_PDI_SEL [1/2]

#define LCDIFV2_PDI_PARA_PDI_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)

PDI_SEL - PDI selected on LCDIFv2 plane number 0b0..PDI selected on LCDIFv2 plane 0 0b1..PDI selected on LCDIFv2 plane 1

LCDIFV2_PDI_PARA_PDI_SEL [2/2]

#define LCDIFV2_PDI_PARA_PDI_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)

PDI_SEL - PDI selected on LCDIFv2 plane number 0b0..PDI selected on LCDIFv2 plane 0 0b1..PDI selected on LCDIFv2 plane 1

LCDIFV2_VSYN_PARA_BP_V [1/2]

#define LCDIFV2_VSYN_PARA_BP_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)

BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1

LCDIFV2_VSYN_PARA_BP_V [2/2]

#define LCDIFV2_VSYN_PARA_BP_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)

BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1

LCDIFV2_VSYN_PARA_FP_V [1/2]

#define LCDIFV2_VSYN_PARA_FP_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)

FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1

LCDIFV2_VSYN_PARA_FP_V [2/2]

#define LCDIFV2_VSYN_PARA_FP_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)

FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1

LCDIFV2_VSYN_PARA_PW_V [1/2]

#define LCDIFV2_VSYN_PARA_PW_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)

PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1

LCDIFV2_VSYN_PARA_PW_V [2/2]

#define LCDIFV2_VSYN_PARA_PW_V

(

x

)

(((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)

PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1