RTEMS 6.1-rc5
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Files | Data Structures | Macros | Variables
L2C-310 Cache Support

This group contains the L2C-310 cache support. More...

Files

file  cache-l2c-310.c
 This source file contains the implementation of the ARM L2C-310 cache controller support.
 

Data Structures

struct  L2CC
 L2CC Register Offsets. More...
 

Macros

#define CPU_DATA_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_DATA_ALIGNMENT
 
#define CPU_INSTRUCTION_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
 
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
 
#define L2C_310_DATA_LINE_MASK   ( CPU_DATA_CACHE_ALIGNMENT - 1 )
 
#define L2C_310_INSTRUCTION_LINE_MASK
 
#define L2C_310_NUM_WAYS   8
 
#define L2C_310_WAY_MASK   ( ( 1 << L2C_310_NUM_WAYS ) - 1 )
 
#define L2C_310_MIN(a, b)    ((a < b) ? (a) : (b))
 
#define L2C_310_MAX_LOCKING_BYTES   (4 * 1024)
 
#define L2C_310_RTL_RELEASE_R0_P0   0x0
 
#define L2C_310_RTL_RELEASE_R1_P0   0x2
 
#define L2C_310_RTL_RELEASE_R2_P0   0x4
 
#define L2C_310_RTL_RELEASE_R3_P0   0x5
 
#define L2C_310_RTL_RELEASE_R3_P1   0x6
 
#define L2C_310_RTL_RELEASE_R3_P2   0x8
 
#define L2C_310_RTL_RELEASE_R3_P3   0x9
 
#define BSP_ARM_L2C_310_RTL_RELEASE   (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
 
#define L2C_310_ERRATA_IS_APPLICABLE_588369
 
#define CACHE_ARM_ERRATA_775420_HANDLER()
 

Variables

rtems_interrupt_lock l2c_310_lock
 

Detailed Description

This group contains the L2C-310 cache support.

Macro Definition Documentation

◆ CACHE_ARM_ERRATA_775420_HANDLER

#define CACHE_ARM_ERRATA_775420_HANDLER ( )
Value:
if( arm_errata_is_applicable_processor_errata_775420 ) { \
} \

◆ L2C_310_INSTRUCTION_LINE_MASK

#define L2C_310_INSTRUCTION_LINE_MASK
Value:
( CPU_INSTRUCTION_CACHE_ALIGNMENT \
- 1 )

Variable Documentation

◆ l2c_310_lock

rtems_interrupt_lock l2c_310_lock
Initial value:
"L2-310 cache controller"
)
#define RTEMS_INTERRUPT_LOCK_INITIALIZER(_name)
Statically initializes an ISR lock object.
Definition: intr.h:909