I2S Register Masks

Macros
#define	I2S_TDR_COUNT   (4U)
#define	I2S_TFR_COUNT   (4U)
#define	I2S_RDR_COUNT   (4U)
#define	I2S_RFR_COUNT   (4U)
#define	I2S_TDR_COUNT   (4U)
#define	I2S_TFR_COUNT   (4U)
#define	I2S_RDR_COUNT   (4U)
#define	I2S_RFR_COUNT   (4U)
#define	I2S_TDR_COUNT   (4U)
#define	I2S_TFR_COUNT   (4U)
#define	I2S_RDR_COUNT   (4U)
#define	I2S_RFR_COUNT   (4U)

VERID - Version ID Register
#define	I2S_VERID_FEATURE_MASK   (0xFFFFU)
#define	I2S_VERID_FEATURE_SHIFT   (0U)
#define	I2S_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define	I2S_VERID_MINOR_MASK   (0xFF0000U)
#define	I2S_VERID_MINOR_SHIFT   (16U)
#define	I2S_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define	I2S_VERID_MAJOR_MASK   (0xFF000000U)
#define	I2S_VERID_MAJOR_SHIFT   (24U)
#define	I2S_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	I2S_PARAM_DATALINE_MASK   (0xFU)
#define	I2S_PARAM_DATALINE_SHIFT   (0U)
#define	I2S_PARAM_DATALINE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define	I2S_PARAM_FIFO_MASK   (0xF00U)
#define	I2S_PARAM_FIFO_SHIFT   (8U)
#define	I2S_PARAM_FIFO(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define	I2S_PARAM_FRAME_MASK   (0xF0000U)
#define	I2S_PARAM_FRAME_SHIFT   (16U)
#define	I2S_PARAM_FRAME(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)

TCSR - SAI Transmit Control Register
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TCR1 - SAI Transmit Configuration 1 Register
#define	I2S_TCR1_TFW_MASK   (0x1FU)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TCR2 - SAI Transmit Configuration 2 Register
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0x40000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

TCR3 - SAI Transmit Configuration 3 Register
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_CFR_MASK   (0xF000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

TCR4 - SAI Transmit Configuration 4 Register
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_CHMOD_MASK   (0x20U)
#define	I2S_TCR4_CHMOD_SHIFT   (5U)
#define	I2S_TCR4_CHMOD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

TCR5 - SAI Transmit Configuration 5 Register
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

TDR - SAI Transmit Data Register
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)

TFR - SAI Transmit FIFO Register
#define	I2S_TFR_RFP_MASK   (0x3FU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0x3F0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

TMR - SAI Transmit Mask Register
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

RCSR - SAI Receive Control Register
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RCR1 - SAI Receive Configuration 1 Register
#define	I2S_RCR1_RFW_MASK   (0x1FU)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RCR2 - SAI Receive Configuration 2 Register
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0x40000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

RCR3 - SAI Receive Configuration 3 Register
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_CFR_MASK   (0xF000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

RCR4 - SAI Receive Configuration 4 Register
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

RCR5 - SAI Receive Configuration 5 Register
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

RDR - SAI Receive Data Register
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)

RFR - SAI Receive FIFO Register
#define	I2S_RFR_RFP_MASK   (0x3FU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define	I2S_RFR_WFP_MASK   (0x3F0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

RMR - SAI Receive Mask Register
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

VERID - Version ID
#define	I2S_VERID_FEATURE_MASK   (0xFFFFU)
#define	I2S_VERID_FEATURE_SHIFT   (0U)
#define	I2S_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define	I2S_VERID_MINOR_MASK   (0xFF0000U)
#define	I2S_VERID_MINOR_SHIFT   (16U)
#define	I2S_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define	I2S_VERID_MAJOR_MASK   (0xFF000000U)
#define	I2S_VERID_MAJOR_SHIFT   (24U)
#define	I2S_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
#define	LPI2C_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPI2C_VERID_FEATURE_SHIFT   (0U)
#define	LPI2C_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define	LPI2C_VERID_MINOR_MASK   (0xFF0000U)
#define	LPI2C_VERID_MINOR_SHIFT   (16U)
#define	LPI2C_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define	LPI2C_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPI2C_VERID_MAJOR_SHIFT   (24U)
#define	LPI2C_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
#define	LPSPI_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPSPI_VERID_FEATURE_SHIFT   (0U)
#define	LPSPI_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define	LPSPI_VERID_MINOR_MASK   (0xFF0000U)
#define	LPSPI_VERID_MINOR_SHIFT   (16U)
#define	LPSPI_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define	LPSPI_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPSPI_VERID_MAJOR_SHIFT   (24U)
#define	LPSPI_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

PARAM - Parameter
#define	I2S_PARAM_DATALINE_MASK   (0xFU)
#define	I2S_PARAM_DATALINE_SHIFT   (0U)
#define	I2S_PARAM_DATALINE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define	I2S_PARAM_FIFO_MASK   (0xF00U)
#define	I2S_PARAM_FIFO_SHIFT   (8U)
#define	I2S_PARAM_FIFO(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define	I2S_PARAM_FRAME_MASK   (0xF0000U)
#define	I2S_PARAM_FRAME_SHIFT   (16U)
#define	I2S_PARAM_FRAME(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
#define	LPI2C_PARAM_MTXFIFO_MASK   (0xFU)
#define	LPI2C_PARAM_MTXFIFO_SHIFT   (0U)
#define	LPI2C_PARAM_MTXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define	LPI2C_PARAM_MRXFIFO_MASK   (0xF00U)
#define	LPI2C_PARAM_MRXFIFO_SHIFT   (8U)
#define	LPI2C_PARAM_MRXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
#define	LPSPI_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPSPI_PARAM_TXFIFO_SHIFT   (0U)
#define	LPSPI_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define	LPSPI_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPSPI_PARAM_RXFIFO_SHIFT   (8U)
#define	LPSPI_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define	LPSPI_PARAM_PCSNUM_MASK   (0xFF0000U)
#define	LPSPI_PARAM_PCSNUM_SHIFT   (16U)
#define	LPSPI_PARAM_PCSNUM(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

TCSR - Transmit Control
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TCR1 - Transmit Configuration 1
#define	I2S_TCR1_TFW_MASK   (0x1FU)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TCR2 - Transmit Configuration 2
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BYP_MASK   (0x800000U)
#define	I2S_TCR2_BYP_SHIFT   (23U)
#define	I2S_TCR2_BYP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0x40000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

TCR3 - Transmit Configuration 3
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_CFR_MASK   (0xF000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

TCR4 - Transmit Configuration 4
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_CHMOD_MASK   (0x20U)
#define	I2S_TCR4_CHMOD_SHIFT   (5U)
#define	I2S_TCR4_CHMOD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

TCR5 - Transmit Configuration 5
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

TDR - Transmit Data
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
#define	LPSPI_TDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_TDR_DATA_SHIFT   (0U)
#define	LPSPI_TDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

TFR - Transmit FIFO
#define	I2S_TFR_RFP_MASK   (0x3FU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0x3F0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

TMR - Transmit Mask
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

RCSR - Receive Control
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RCR1 - Receive Configuration 1
#define	I2S_RCR1_RFW_MASK   (0x1FU)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RCR2 - Receive Configuration 2
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BYP_MASK   (0x800000U)
#define	I2S_RCR2_BYP_SHIFT   (23U)
#define	I2S_RCR2_BYP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0x40000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

RCR3 - Receive Configuration 3
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_CFR_MASK   (0xF000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

RCR4 - Receive Configuration 4
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

RCR5 - Receive Configuration 5
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

RDR - Receive Data
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
#define	LPSPI_RDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_RDR_DATA_SHIFT   (0U)
#define	LPSPI_RDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

RFR - Receive FIFO
#define	I2S_RFR_RFP_MASK   (0x3FU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define	I2S_RFR_WFP_MASK   (0x3F0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

RMR - Receive Mask
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

VERID - Version ID
#define	I2S_VERID_FEATURE_MASK   (0xFFFFU)
#define	I2S_VERID_FEATURE_SHIFT   (0U)
#define	I2S_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define	I2S_VERID_MINOR_MASK   (0xFF0000U)
#define	I2S_VERID_MINOR_SHIFT   (16U)
#define	I2S_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define	I2S_VERID_MAJOR_MASK   (0xFF000000U)
#define	I2S_VERID_MAJOR_SHIFT   (24U)
#define	I2S_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
#define	LPI2C_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPI2C_VERID_FEATURE_SHIFT   (0U)
#define	LPI2C_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define	LPI2C_VERID_MINOR_MASK   (0xFF0000U)
#define	LPI2C_VERID_MINOR_SHIFT   (16U)
#define	LPI2C_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define	LPI2C_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPI2C_VERID_MAJOR_SHIFT   (24U)
#define	LPI2C_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
#define	LPSPI_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPSPI_VERID_FEATURE_SHIFT   (0U)
#define	LPSPI_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define	LPSPI_VERID_MINOR_MASK   (0xFF0000U)
#define	LPSPI_VERID_MINOR_SHIFT   (16U)
#define	LPSPI_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define	LPSPI_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPSPI_VERID_MAJOR_SHIFT   (24U)
#define	LPSPI_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

PARAM - Parameter
#define	I2S_PARAM_DATALINE_MASK   (0xFU)
#define	I2S_PARAM_DATALINE_SHIFT   (0U)
#define	I2S_PARAM_DATALINE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define	I2S_PARAM_FIFO_MASK   (0xF00U)
#define	I2S_PARAM_FIFO_SHIFT   (8U)
#define	I2S_PARAM_FIFO(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define	I2S_PARAM_FRAME_MASK   (0xF0000U)
#define	I2S_PARAM_FRAME_SHIFT   (16U)
#define	I2S_PARAM_FRAME(x)   (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
#define	LPI2C_PARAM_MTXFIFO_MASK   (0xFU)
#define	LPI2C_PARAM_MTXFIFO_SHIFT   (0U)
#define	LPI2C_PARAM_MTXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define	LPI2C_PARAM_MRXFIFO_MASK   (0xF00U)
#define	LPI2C_PARAM_MRXFIFO_SHIFT   (8U)
#define	LPI2C_PARAM_MRXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
#define	LPSPI_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPSPI_PARAM_TXFIFO_SHIFT   (0U)
#define	LPSPI_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define	LPSPI_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPSPI_PARAM_RXFIFO_SHIFT   (8U)
#define	LPSPI_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define	LPSPI_PARAM_PCSNUM_MASK   (0xFF0000U)
#define	LPSPI_PARAM_PCSNUM_SHIFT   (16U)
#define	LPSPI_PARAM_PCSNUM(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

TCSR - Transmit Control
#define	I2S_TCSR_FRDE_MASK   (0x1U)
#define	I2S_TCSR_FRDE_SHIFT   (0U)
#define	I2S_TCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define	I2S_TCSR_FWDE_MASK   (0x2U)
#define	I2S_TCSR_FWDE_SHIFT   (1U)
#define	I2S_TCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define	I2S_TCSR_FRIE_MASK   (0x100U)
#define	I2S_TCSR_FRIE_SHIFT   (8U)
#define	I2S_TCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define	I2S_TCSR_FWIE_MASK   (0x200U)
#define	I2S_TCSR_FWIE_SHIFT   (9U)
#define	I2S_TCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define	I2S_TCSR_FEIE_MASK   (0x400U)
#define	I2S_TCSR_FEIE_SHIFT   (10U)
#define	I2S_TCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define	I2S_TCSR_SEIE_MASK   (0x800U)
#define	I2S_TCSR_SEIE_SHIFT   (11U)
#define	I2S_TCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define	I2S_TCSR_WSIE_MASK   (0x1000U)
#define	I2S_TCSR_WSIE_SHIFT   (12U)
#define	I2S_TCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define	I2S_TCSR_FRF_MASK   (0x10000U)
#define	I2S_TCSR_FRF_SHIFT   (16U)
#define	I2S_TCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define	I2S_TCSR_FWF_MASK   (0x20000U)
#define	I2S_TCSR_FWF_SHIFT   (17U)
#define	I2S_TCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define	I2S_TCSR_FEF_MASK   (0x40000U)
#define	I2S_TCSR_FEF_SHIFT   (18U)
#define	I2S_TCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define	I2S_TCSR_SEF_MASK   (0x80000U)
#define	I2S_TCSR_SEF_SHIFT   (19U)
#define	I2S_TCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define	I2S_TCSR_WSF_MASK   (0x100000U)
#define	I2S_TCSR_WSF_SHIFT   (20U)
#define	I2S_TCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define	I2S_TCSR_SR_MASK   (0x1000000U)
#define	I2S_TCSR_SR_SHIFT   (24U)
#define	I2S_TCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define	I2S_TCSR_FR_MASK   (0x2000000U)
#define	I2S_TCSR_FR_SHIFT   (25U)
#define	I2S_TCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define	I2S_TCSR_BCE_MASK   (0x10000000U)
#define	I2S_TCSR_BCE_SHIFT   (28U)
#define	I2S_TCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define	I2S_TCSR_DBGE_MASK   (0x20000000U)
#define	I2S_TCSR_DBGE_SHIFT   (29U)
#define	I2S_TCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define	I2S_TCSR_STOPE_MASK   (0x40000000U)
#define	I2S_TCSR_STOPE_SHIFT   (30U)
#define	I2S_TCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define	I2S_TCSR_TE_MASK   (0x80000000U)
#define	I2S_TCSR_TE_SHIFT   (31U)
#define	I2S_TCSR_TE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TCR1 - Transmit Configuration 1
#define	I2S_TCR1_TFW_MASK   (0x1FU)
#define	I2S_TCR1_TFW_SHIFT   (0U)
#define	I2S_TCR1_TFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TCR2 - Transmit Configuration 2
#define	I2S_TCR2_DIV_MASK   (0xFFU)
#define	I2S_TCR2_DIV_SHIFT   (0U)
#define	I2S_TCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define	I2S_TCR2_BYP_MASK   (0x800000U)
#define	I2S_TCR2_BYP_SHIFT   (23U)
#define	I2S_TCR2_BYP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
#define	I2S_TCR2_BCD_MASK   (0x1000000U)
#define	I2S_TCR2_BCD_SHIFT   (24U)
#define	I2S_TCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define	I2S_TCR2_BCP_MASK   (0x2000000U)
#define	I2S_TCR2_BCP_SHIFT   (25U)
#define	I2S_TCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define	I2S_TCR2_MSEL_MASK   (0xC000000U)
#define	I2S_TCR2_MSEL_SHIFT   (26U)
#define	I2S_TCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define	I2S_TCR2_BCI_MASK   (0x10000000U)
#define	I2S_TCR2_BCI_SHIFT   (28U)
#define	I2S_TCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define	I2S_TCR2_BCS_MASK   (0x20000000U)
#define	I2S_TCR2_BCS_SHIFT   (29U)
#define	I2S_TCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define	I2S_TCR2_SYNC_MASK   (0x40000000U)
#define	I2S_TCR2_SYNC_SHIFT   (30U)
#define	I2S_TCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

TCR3 - Transmit Configuration 3
#define	I2S_TCR3_WDFL_MASK   (0x1FU)
#define	I2S_TCR3_WDFL_SHIFT   (0U)
#define	I2S_TCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define	I2S_TCR3_TCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_TCE_SHIFT   (16U)
#define	I2S_TCR3_TCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_TCR3_CFR_MASK   (0xF000000U)
#define	I2S_TCR3_CFR_SHIFT   (24U)
#define	I2S_TCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

TCR4 - Transmit Configuration 4
#define	I2S_TCR4_FSD_MASK   (0x1U)
#define	I2S_TCR4_FSD_SHIFT   (0U)
#define	I2S_TCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define	I2S_TCR4_FSP_MASK   (0x2U)
#define	I2S_TCR4_FSP_SHIFT   (1U)
#define	I2S_TCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define	I2S_TCR4_ONDEM_MASK   (0x4U)
#define	I2S_TCR4_ONDEM_SHIFT   (2U)
#define	I2S_TCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define	I2S_TCR4_FSE_MASK   (0x8U)
#define	I2S_TCR4_FSE_SHIFT   (3U)
#define	I2S_TCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define	I2S_TCR4_MF_MASK   (0x10U)
#define	I2S_TCR4_MF_SHIFT   (4U)
#define	I2S_TCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define	I2S_TCR4_CHMOD_MASK   (0x20U)
#define	I2S_TCR4_CHMOD_SHIFT   (5U)
#define	I2S_TCR4_CHMOD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define	I2S_TCR4_SYWD_MASK   (0x1F00U)
#define	I2S_TCR4_SYWD_SHIFT   (8U)
#define	I2S_TCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define	I2S_TCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_TCR4_FRSZ_SHIFT   (16U)
#define	I2S_TCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define	I2S_TCR4_FPACK_MASK   (0x3000000U)
#define	I2S_TCR4_FPACK_SHIFT   (24U)
#define	I2S_TCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define	I2S_TCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_TCR4_FCOMB_SHIFT   (26U)
#define	I2S_TCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define	I2S_TCR4_FCONT_MASK   (0x10000000U)
#define	I2S_TCR4_FCONT_SHIFT   (28U)
#define	I2S_TCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

TCR5 - Transmit Configuration 5
#define	I2S_TCR5_FBT_MASK   (0x1F00U)
#define	I2S_TCR5_FBT_SHIFT   (8U)
#define	I2S_TCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define	I2S_TCR5_W0W_MASK   (0x1F0000U)
#define	I2S_TCR5_W0W_SHIFT   (16U)
#define	I2S_TCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define	I2S_TCR5_WNW_MASK   (0x1F000000U)
#define	I2S_TCR5_WNW_SHIFT   (24U)
#define	I2S_TCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

TDR - Transmit Data
#define	I2S_TDR_TDR_MASK   (0xFFFFFFFFU)
#define	I2S_TDR_TDR_SHIFT   (0U)
#define	I2S_TDR_TDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
#define	LPSPI_TDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_TDR_DATA_SHIFT   (0U)
#define	LPSPI_TDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

TFR - Transmit FIFO
#define	I2S_TFR_RFP_MASK   (0x3FU)
#define	I2S_TFR_RFP_SHIFT   (0U)
#define	I2S_TFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define	I2S_TFR_WFP_MASK   (0x3F0000U)
#define	I2S_TFR_WFP_SHIFT   (16U)
#define	I2S_TFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define	I2S_TFR_WCP_MASK   (0x80000000U)
#define	I2S_TFR_WCP_SHIFT   (31U)
#define	I2S_TFR_WCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

TMR - Transmit Mask
#define	I2S_TMR_TWM_MASK   (0xFFFFFFFFU)
#define	I2S_TMR_TWM_SHIFT   (0U)
#define	I2S_TMR_TWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

RCSR - Receive Control
#define	I2S_RCSR_FRDE_MASK   (0x1U)
#define	I2S_RCSR_FRDE_SHIFT   (0U)
#define	I2S_RCSR_FRDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define	I2S_RCSR_FWDE_MASK   (0x2U)
#define	I2S_RCSR_FWDE_SHIFT   (1U)
#define	I2S_RCSR_FWDE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define	I2S_RCSR_FRIE_MASK   (0x100U)
#define	I2S_RCSR_FRIE_SHIFT   (8U)
#define	I2S_RCSR_FRIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define	I2S_RCSR_FWIE_MASK   (0x200U)
#define	I2S_RCSR_FWIE_SHIFT   (9U)
#define	I2S_RCSR_FWIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define	I2S_RCSR_FEIE_MASK   (0x400U)
#define	I2S_RCSR_FEIE_SHIFT   (10U)
#define	I2S_RCSR_FEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define	I2S_RCSR_SEIE_MASK   (0x800U)
#define	I2S_RCSR_SEIE_SHIFT   (11U)
#define	I2S_RCSR_SEIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define	I2S_RCSR_WSIE_MASK   (0x1000U)
#define	I2S_RCSR_WSIE_SHIFT   (12U)
#define	I2S_RCSR_WSIE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define	I2S_RCSR_FRF_MASK   (0x10000U)
#define	I2S_RCSR_FRF_SHIFT   (16U)
#define	I2S_RCSR_FRF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define	I2S_RCSR_FWF_MASK   (0x20000U)
#define	I2S_RCSR_FWF_SHIFT   (17U)
#define	I2S_RCSR_FWF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define	I2S_RCSR_FEF_MASK   (0x40000U)
#define	I2S_RCSR_FEF_SHIFT   (18U)
#define	I2S_RCSR_FEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define	I2S_RCSR_SEF_MASK   (0x80000U)
#define	I2S_RCSR_SEF_SHIFT   (19U)
#define	I2S_RCSR_SEF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define	I2S_RCSR_WSF_MASK   (0x100000U)
#define	I2S_RCSR_WSF_SHIFT   (20U)
#define	I2S_RCSR_WSF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define	I2S_RCSR_SR_MASK   (0x1000000U)
#define	I2S_RCSR_SR_SHIFT   (24U)
#define	I2S_RCSR_SR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define	I2S_RCSR_FR_MASK   (0x2000000U)
#define	I2S_RCSR_FR_SHIFT   (25U)
#define	I2S_RCSR_FR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define	I2S_RCSR_BCE_MASK   (0x10000000U)
#define	I2S_RCSR_BCE_SHIFT   (28U)
#define	I2S_RCSR_BCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define	I2S_RCSR_DBGE_MASK   (0x20000000U)
#define	I2S_RCSR_DBGE_SHIFT   (29U)
#define	I2S_RCSR_DBGE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define	I2S_RCSR_STOPE_MASK   (0x40000000U)
#define	I2S_RCSR_STOPE_SHIFT   (30U)
#define	I2S_RCSR_STOPE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define	I2S_RCSR_RE_MASK   (0x80000000U)
#define	I2S_RCSR_RE_SHIFT   (31U)
#define	I2S_RCSR_RE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RCR1 - Receive Configuration 1
#define	I2S_RCR1_RFW_MASK   (0x1FU)
#define	I2S_RCR1_RFW_SHIFT   (0U)
#define	I2S_RCR1_RFW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RCR2 - Receive Configuration 2
#define	I2S_RCR2_DIV_MASK   (0xFFU)
#define	I2S_RCR2_DIV_SHIFT   (0U)
#define	I2S_RCR2_DIV(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define	I2S_RCR2_BYP_MASK   (0x800000U)
#define	I2S_RCR2_BYP_SHIFT   (23U)
#define	I2S_RCR2_BYP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
#define	I2S_RCR2_BCD_MASK   (0x1000000U)
#define	I2S_RCR2_BCD_SHIFT   (24U)
#define	I2S_RCR2_BCD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define	I2S_RCR2_BCP_MASK   (0x2000000U)
#define	I2S_RCR2_BCP_SHIFT   (25U)
#define	I2S_RCR2_BCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define	I2S_RCR2_MSEL_MASK   (0xC000000U)
#define	I2S_RCR2_MSEL_SHIFT   (26U)
#define	I2S_RCR2_MSEL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define	I2S_RCR2_BCI_MASK   (0x10000000U)
#define	I2S_RCR2_BCI_SHIFT   (28U)
#define	I2S_RCR2_BCI(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define	I2S_RCR2_BCS_MASK   (0x20000000U)
#define	I2S_RCR2_BCS_SHIFT   (29U)
#define	I2S_RCR2_BCS(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define	I2S_RCR2_SYNC_MASK   (0x40000000U)
#define	I2S_RCR2_SYNC_SHIFT   (30U)
#define	I2S_RCR2_SYNC(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

RCR3 - Receive Configuration 3
#define	I2S_RCR3_WDFL_MASK   (0x1FU)
#define	I2S_RCR3_WDFL_SHIFT   (0U)
#define	I2S_RCR3_WDFL(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define	I2S_RCR3_RCE_MASK   (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_RCE_SHIFT   (16U)
#define	I2S_RCR3_RCE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define	I2S_RCR3_CFR_MASK   (0xF000000U)
#define	I2S_RCR3_CFR_SHIFT   (24U)
#define	I2S_RCR3_CFR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

RCR4 - Receive Configuration 4
#define	I2S_RCR4_FSD_MASK   (0x1U)
#define	I2S_RCR4_FSD_SHIFT   (0U)
#define	I2S_RCR4_FSD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define	I2S_RCR4_FSP_MASK   (0x2U)
#define	I2S_RCR4_FSP_SHIFT   (1U)
#define	I2S_RCR4_FSP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define	I2S_RCR4_ONDEM_MASK   (0x4U)
#define	I2S_RCR4_ONDEM_SHIFT   (2U)
#define	I2S_RCR4_ONDEM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define	I2S_RCR4_FSE_MASK   (0x8U)
#define	I2S_RCR4_FSE_SHIFT   (3U)
#define	I2S_RCR4_FSE(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define	I2S_RCR4_MF_MASK   (0x10U)
#define	I2S_RCR4_MF_SHIFT   (4U)
#define	I2S_RCR4_MF(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define	I2S_RCR4_SYWD_MASK   (0x1F00U)
#define	I2S_RCR4_SYWD_SHIFT   (8U)
#define	I2S_RCR4_SYWD(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define	I2S_RCR4_FRSZ_MASK   (0x1F0000U)
#define	I2S_RCR4_FRSZ_SHIFT   (16U)
#define	I2S_RCR4_FRSZ(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define	I2S_RCR4_FPACK_MASK   (0x3000000U)
#define	I2S_RCR4_FPACK_SHIFT   (24U)
#define	I2S_RCR4_FPACK(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define	I2S_RCR4_FCOMB_MASK   (0xC000000U)
#define	I2S_RCR4_FCOMB_SHIFT   (26U)
#define	I2S_RCR4_FCOMB(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define	I2S_RCR4_FCONT_MASK   (0x10000000U)
#define	I2S_RCR4_FCONT_SHIFT   (28U)
#define	I2S_RCR4_FCONT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

RCR5 - Receive Configuration 5
#define	I2S_RCR5_FBT_MASK   (0x1F00U)
#define	I2S_RCR5_FBT_SHIFT   (8U)
#define	I2S_RCR5_FBT(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define	I2S_RCR5_W0W_MASK   (0x1F0000U)
#define	I2S_RCR5_W0W_SHIFT   (16U)
#define	I2S_RCR5_W0W(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define	I2S_RCR5_WNW_MASK   (0x1F000000U)
#define	I2S_RCR5_WNW_SHIFT   (24U)
#define	I2S_RCR5_WNW(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

RDR - Receive Data
#define	I2S_RDR_RDR_MASK   (0xFFFFFFFFU)
#define	I2S_RDR_RDR_SHIFT   (0U)
#define	I2S_RDR_RDR(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
#define	LPSPI_RDR_DATA_MASK   (0xFFFFFFFFU)
#define	LPSPI_RDR_DATA_SHIFT   (0U)
#define	LPSPI_RDR_DATA(x)   (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

RFR - Receive FIFO
#define	I2S_RFR_RFP_MASK   (0x3FU)
#define	I2S_RFR_RFP_SHIFT   (0U)
#define	I2S_RFR_RFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define	I2S_RFR_RCP_MASK   (0x8000U)
#define	I2S_RFR_RCP_SHIFT   (15U)
#define	I2S_RFR_RCP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define	I2S_RFR_WFP_MASK   (0x3F0000U)
#define	I2S_RFR_WFP_SHIFT   (16U)
#define	I2S_RFR_WFP(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

RMR - Receive Mask
#define	I2S_RMR_RWM_MASK   (0xFFFFFFFFU)
#define	I2S_RMR_RWM_SHIFT   (0U)
#define	I2S_RMR_RWM(x)   (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

Detailed Description

Macro Definition Documentation

I2S_PARAM_DATALINE [1/3]

#define I2S_PARAM_DATALINE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

DATALINE - Number of Datalines

I2S_PARAM_DATALINE [2/3]

#define I2S_PARAM_DATALINE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

DATALINE - Number of Datalines

I2S_PARAM_DATALINE [3/3]

#define I2S_PARAM_DATALINE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)

DATALINE - Number of Datalines

I2S_PARAM_FIFO [1/3]

#define I2S_PARAM_FIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

FIFO - FIFO Size

I2S_PARAM_FIFO [2/3]

#define I2S_PARAM_FIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

FIFO - FIFO Size

I2S_PARAM_FIFO [3/3]

#define I2S_PARAM_FIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)

FIFO - FIFO Size

I2S_PARAM_FRAME [1/3]

#define I2S_PARAM_FRAME

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)

FRAME - Frame Size

I2S_PARAM_FRAME [2/3]

#define I2S_PARAM_FRAME

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)

FRAME - Frame Size

I2S_PARAM_FRAME [3/3]

#define I2S_PARAM_FRAME

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)

FRAME - Frame Size

I2S_RCR1_RFW [1/3]

#define I2S_RCR1_RFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RFW - Receive FIFO Watermark

I2S_RCR1_RFW [2/3]

#define I2S_RCR1_RFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RFW - Receive FIFO Watermark

I2S_RCR1_RFW [3/3]

#define I2S_RCR1_RFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)

RFW - Receive FIFO Watermark

I2S_RCR2_BCD [1/3]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCD [2/3]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCD [3/3]

#define I2S_RCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_RCR2_BCI [1/3]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCI [2/3]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCI [3/3]

#define I2S_RCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_RCR2_BCP [1/3]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCP [2/3]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCP [3/3]

#define I2S_RCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_RCR2_BCS [1/3]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BCS [2/3]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BCS [3/3]

#define I2S_RCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_RCR2_BYP [1/2]

#define I2S_RCR2_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)

BYP - Bit Clock Bypass 0b0..Internal bit clock is generated from bit clock divider. 0b1..Internal bit clock is divide by one of the audio master clock.

I2S_RCR2_BYP [2/2]

#define I2S_RCR2_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)

BYP - Bit Clock Bypass 0b0..Internal bit clock is generated from bit clock divider. 0b1..Internal bit clock is divide by one of the audio master clock.

I2S_RCR2_DIV [1/3]

#define I2S_RCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_RCR2_DIV [2/3]

#define I2S_RCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_RCR2_DIV [3/3]

#define I2S_RCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_RCR2_MSEL [1/3]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_MSEL [2/3]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_MSEL [3/3]

#define I2S_RCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_RCR2_SYNC [1/3]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with transmitter.

I2S_RCR2_SYNC [2/3]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with transmitter.

I2S_RCR2_SYNC [3/3]

#define I2S_RCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with transmitter.

I2S_RCR3_CFR [1/3]

#define I2S_RCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_RCR3_CFR [2/3]

#define I2S_RCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_RCR3_CFR [3/3]

#define I2S_RCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_RCR3_RCE [1/3]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

RCE - Receive Channel Enable

I2S_RCR3_RCE [2/3]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

RCE - Receive Channel Enable

I2S_RCR3_RCE [3/3]

#define I2S_RCR3_RCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

RCE - Receive Channel Enable

I2S_RCR3_WDFL [1/3]

#define I2S_RCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_RCR3_WDFL [2/3]

#define I2S_RCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_RCR3_WDFL [3/3]

#define I2S_RCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_RCR4_FCOMB [1/3]

#define I2S_RCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).

I2S_RCR4_FCOMB [2/3]

#define I2S_RCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).

I2S_RCR4_FCOMB [3/3]

#define I2S_RCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). 0b10..FIFO combine mode enabled on FIFO reads (by software). 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).

I2S_RCR4_FCONT [1/3]

#define I2S_RCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_RCR4_FCONT [2/3]

#define I2S_RCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_RCR4_FCONT [3/3]

#define I2S_RCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_RCR4_FPACK [1/3]

#define I2S_RCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_RCR4_FPACK [2/3]

#define I2S_RCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_RCR4_FPACK [3/3]

#define I2S_RCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved. 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_RCR4_FRSZ [1/3]

#define I2S_RCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)

FRSZ - Frame Size

I2S_RCR4_FRSZ [2/3]

#define I2S_RCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)

FRSZ - Frame Size

I2S_RCR4_FRSZ [3/3]

#define I2S_RCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)

FRSZ - Frame Size

I2S_RCR4_FSD [1/3]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSD [2/3]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSD [3/3]

#define I2S_RCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame Sync is generated externally in Slave mode. 0b1..Frame Sync is generated internally in Master mode.

I2S_RCR4_FSE [1/3]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSE [2/3]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSE [3/3]

#define I2S_RCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_RCR4_FSP [1/3]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_FSP [2/3]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_FSP [3/3]

#define I2S_RCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_RCR4_MF [1/3]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_MF [2/3]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_MF [3/3]

#define I2S_RCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)

MF - MSB First 0b0..LSB is received first. 0b1..MSB is received first.

I2S_RCR4_ONDEM [1/3]

#define I2S_RCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_RCR4_ONDEM [2/3]

#define I2S_RCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_RCR4_ONDEM [3/3]

#define I2S_RCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_RCR4_SYWD [1/3]

#define I2S_RCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)

SYWD - Sync Width

I2S_RCR4_SYWD [2/3]

#define I2S_RCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)

SYWD - Sync Width

I2S_RCR4_SYWD [3/3]

#define I2S_RCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)

SYWD - Sync Width

I2S_RCR5_FBT [1/3]

#define I2S_RCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_RCR5_FBT [2/3]

#define I2S_RCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_RCR5_FBT [3/3]

#define I2S_RCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_RCR5_W0W [1/3]

#define I2S_RCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)

W0W - Word 0 Width

I2S_RCR5_W0W [2/3]

#define I2S_RCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)

W0W - Word 0 Width

I2S_RCR5_W0W [3/3]

#define I2S_RCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)

W0W - Word 0 Width

I2S_RCR5_WNW [1/3]

#define I2S_RCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

WNW - Word N Width

I2S_RCR5_WNW [2/3]

#define I2S_RCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

WNW - Word N Width

I2S_RCR5_WNW [3/3]

#define I2S_RCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)

WNW - Word N Width

I2S_RCSR_BCE [1/3]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_BCE [2/3]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_BCE [3/3]

#define I2S_RCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Receive bit clock is disabled. 0b1..Receive bit clock is enabled.

I2S_RCSR_DBGE [1/3]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_DBGE [2/3]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_DBGE [3/3]

#define I2S_RCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Receiver is disabled in Debug mode, after completing the current frame. 0b1..Receiver is enabled in Debug mode.

I2S_RCSR_FEF [1/3]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEF [2/3]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEF [3/3]

#define I2S_RCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Receive overflow not detected. 0b1..Receive overflow detected.

I2S_RCSR_FEIE [1/3]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FEIE [2/3]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FEIE [3/3]

#define I2S_RCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FR [1/3]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FR [2/3]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FR [3/3]

#define I2S_RCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_RCSR_FRDE [1/3]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRDE [2/3]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRDE [3/3]

#define I2S_RCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FRF [1/3]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRF [2/3]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRF [3/3]

#define I2S_RCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Receive FIFO watermark not reached. 0b1..Receive FIFO watermark has been reached.

I2S_RCSR_FRIE [1/3]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FRIE [2/3]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FRIE [3/3]

#define I2S_RCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWDE [1/3]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWDE [2/3]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWDE [3/3]

#define I2S_RCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_RCSR_FWF [1/3]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWF [2/3]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWF [3/3]

#define I2S_RCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled receive FIFO is full. 0b1..Enabled receive FIFO is full.

I2S_RCSR_FWIE [1/3]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWIE [2/3]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_FWIE [3/3]

#define I2S_RCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_RCSR_RE [1/3]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_RE [2/3]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_RE [3/3]

#define I2S_RCSR_RE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)

RE - Receiver Enable 0b0..Receiver is disabled. 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.

I2S_RCSR_SEF [1/3]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEF [2/3]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEF [3/3]

#define I2S_RCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_RCSR_SEIE [1/3]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SEIE [2/3]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SEIE [3/3]

#define I2S_RCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_SR [1/3]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_SR [2/3]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_SR [3/3]

#define I2S_RCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_RCSR_STOPE [1/3]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_STOPE [2/3]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_STOPE [3/3]

#define I2S_RCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Receiver disabled in Stop mode. 0b1..Receiver enabled in Stop mode.

I2S_RCSR_WSF [1/3]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSF [2/3]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSF [3/3]

#define I2S_RCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_RCSR_WSIE [1/3]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_WSIE [2/3]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RCSR_WSIE [3/3]

#define I2S_RCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_RDR_RDR [1/3]

#define I2S_RDR_RDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)

RDR - Receive Data Register

I2S_RDR_RDR [2/3]

#define I2S_RDR_RDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)

RDR - Receive Data Register

I2S_RDR_RDR [3/3]

#define I2S_RDR_RDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)

RDR - Receive Data Register

I2S_RFR_RCP [1/3]

#define I2S_RFR_RCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.

I2S_RFR_RCP [2/3]

#define I2S_RFR_RCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.

I2S_RFR_RCP [3/3]

#define I2S_RFR_RCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)

RCP - Receive Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.

I2S_RFR_RFP [1/3]

#define I2S_RFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_RFR_RFP [2/3]

#define I2S_RFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_RFR_RFP [3/3]

#define I2S_RFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_RFR_WFP [1/3]

#define I2S_RFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_RFR_WFP [2/3]

#define I2S_RFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_RFR_WFP [3/3]

#define I2S_RFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_RMR_RWM [1/3]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RMR_RWM [2/3]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_RMR_RWM [3/3]

#define I2S_RMR_RWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)

RWM - Receive Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked.

I2S_TCR1_TFW [1/3]

#define I2S_TCR1_TFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TFW - Transmit FIFO Watermark

I2S_TCR1_TFW [2/3]

#define I2S_TCR1_TFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TFW - Transmit FIFO Watermark

I2S_TCR1_TFW [3/3]

#define I2S_TCR1_TFW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)

TFW - Transmit FIFO Watermark

I2S_TCR2_BCD [1/3]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCD [2/3]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCD [3/3]

#define I2S_TCR2_BCD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)

BCD - Bit Clock Direction 0b0..Bit clock is generated externally in Slave mode. 0b1..Bit clock is generated internally in Master mode.

I2S_TCR2_BCI [1/3]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCI [2/3]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCI [3/3]

#define I2S_TCR2_BCI

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)

BCI - Bit Clock Input 0b0..No effect. 0b1..Internal logic is clocked as if bit clock was externally generated.

I2S_TCR2_BCP [1/3]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCP [2/3]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCP [3/3]

#define I2S_TCR2_BCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)

BCP - Bit Clock Polarity 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.

I2S_TCR2_BCS [1/3]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BCS [2/3]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BCS [3/3]

#define I2S_TCR2_BCS

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)

BCS - Bit Clock Swap 0b0..Use the normal bit clock source. 0b1..Swap the bit clock source.

I2S_TCR2_BYP [1/2]

#define I2S_TCR2_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)

BYP - Bit Clock Bypass 0b0..Internal bit clock is generated from bit clock divider. 0b1..Internal bit clock is divide by one of the audio master clock.

I2S_TCR2_BYP [2/2]

#define I2S_TCR2_BYP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)

BYP - Bit Clock Bypass 0b0..Internal bit clock is generated from bit clock divider. 0b1..Internal bit clock is divide by one of the audio master clock.

I2S_TCR2_DIV [1/3]

#define I2S_TCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_TCR2_DIV [2/3]

#define I2S_TCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_TCR2_DIV [3/3]

#define I2S_TCR2_DIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)

DIV - Bit Clock Divide

I2S_TCR2_MSEL [1/3]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_MSEL [2/3]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_MSEL [3/3]

#define I2S_TCR2_MSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)

MSEL - MCLK Select 0b00..Bus Clock selected. 0b01..Master Clock (MCLK) 1 option selected. 0b10..Master Clock (MCLK) 2 option selected. 0b11..Master Clock (MCLK) 3 option selected.

I2S_TCR2_SYNC [1/3]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with receiver.

I2S_TCR2_SYNC [2/3]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with receiver.

I2S_TCR2_SYNC [3/3]

#define I2S_TCR2_SYNC

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)

SYNC - Synchronous Mode 0b0..Asynchronous mode. 0b1..Synchronous with receiver.

I2S_TCR3_CFR [1/3]

#define I2S_TCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_TCR3_CFR [2/3]

#define I2S_TCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_TCR3_CFR [3/3]

#define I2S_TCR3_CFR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)

CFR - Channel FIFO Reset

I2S_TCR3_TCE [1/3]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

TCE - Transmit Channel Enable

I2S_TCR3_TCE [2/3]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

TCE - Transmit Channel Enable

I2S_TCR3_TCE [3/3]

#define I2S_TCR3_TCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */

TCE - Transmit Channel Enable

I2S_TCR3_WDFL [1/3]

#define I2S_TCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_TCR3_WDFL [2/3]

#define I2S_TCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_TCR3_WDFL [3/3]

#define I2S_TCR3_WDFL

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)

WDFL - Word Flag Configuration

I2S_TCR4_CHMOD [1/3]

#define I2S_TCR4_CHMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)

CHMOD - Channel Mode 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.

I2S_TCR4_CHMOD [2/3]

#define I2S_TCR4_CHMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)

CHMOD - Channel Mode 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.

I2S_TCR4_CHMOD [3/3]

#define I2S_TCR4_CHMOD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)

CHMOD - Channel Mode 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.

I2S_TCR4_FCOMB [1/3]

#define I2S_TCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).

I2S_TCR4_FCOMB [2/3]

#define I2S_TCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).

I2S_TCR4_FCOMB [3/3]

#define I2S_TCR4_FCOMB

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)

FCOMB - FIFO Combine Mode 0b00..FIFO combine mode disabled. 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0b10..FIFO combine mode enabled on FIFO writes (by software). 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).

I2S_TCR4_FCONT [1/3]

#define I2S_TCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_TCR4_FCONT [2/3]

#define I2S_TCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_TCR4_FCONT [3/3]

#define I2S_TCR4_FCONT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)

FCONT - FIFO Continue on Error 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.

I2S_TCR4_FPACK [1/3]

#define I2S_TCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled 0b01..Reserved 0b10..8-bit FIFO packing is enabled 0b11..16-bit FIFO packing is enabled

I2S_TCR4_FPACK [2/3]

#define I2S_TCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled. 0b01..Reserved 0b10..8-bit FIFO packing is enabled. 0b11..16-bit FIFO packing is enabled.

I2S_TCR4_FPACK [3/3]

#define I2S_TCR4_FPACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)

FPACK - FIFO Packing Mode 0b00..FIFO packing is disabled. 0b01..Reserved 0b10..8-bit FIFO packing is enabled. 0b11..16-bit FIFO packing is enabled.

I2S_TCR4_FRSZ [1/3]

#define I2S_TCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)

FRSZ - Frame size

I2S_TCR4_FRSZ [2/3]

#define I2S_TCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)

FRSZ - Frame size

I2S_TCR4_FRSZ [3/3]

#define I2S_TCR4_FRSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)

FRSZ - Frame size

I2S_TCR4_FSD [1/3]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSD [2/3]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSD [3/3]

#define I2S_TCR4_FSD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)

FSD - Frame Sync Direction 0b0..Frame sync is generated externally in Slave mode. 0b1..Frame sync is generated internally in Master mode.

I2S_TCR4_FSE [1/3]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSE [2/3]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSE [3/3]

#define I2S_TCR4_FSE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)

FSE - Frame Sync Early 0b0..Frame sync asserts with the first bit of the frame. 0b1..Frame sync asserts one bit before the first bit of the frame.

I2S_TCR4_FSP [1/3]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_FSP [2/3]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_FSP [3/3]

#define I2S_TCR4_FSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)

FSP - Frame Sync Polarity 0b0..Frame sync is active high. 0b1..Frame sync is active low.

I2S_TCR4_MF [1/3]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_MF [2/3]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_MF [3/3]

#define I2S_TCR4_MF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)

MF - MSB First 0b0..LSB is transmitted first. 0b1..MSB is transmitted first.

I2S_TCR4_ONDEM [1/3]

#define I2S_TCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_TCR4_ONDEM [2/3]

#define I2S_TCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_TCR4_ONDEM [3/3]

#define I2S_TCR4_ONDEM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)

ONDEM - On Demand Mode 0b0..Internal frame sync is generated continuously. 0b1..Internal frame sync is generated when the FIFO warning flag is clear.

I2S_TCR4_SYWD [1/3]

#define I2S_TCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

SYWD - Sync Width

I2S_TCR4_SYWD [2/3]

#define I2S_TCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

SYWD - Sync Width

I2S_TCR4_SYWD [3/3]

#define I2S_TCR4_SYWD

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)

SYWD - Sync Width

I2S_TCR5_FBT [1/3]

#define I2S_TCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_TCR5_FBT [2/3]

#define I2S_TCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_TCR5_FBT [3/3]

#define I2S_TCR5_FBT

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)

FBT - First Bit Shifted

I2S_TCR5_W0W [1/3]

#define I2S_TCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)

W0W - Word 0 Width

I2S_TCR5_W0W [2/3]

#define I2S_TCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)

W0W - Word 0 Width

I2S_TCR5_W0W [3/3]

#define I2S_TCR5_W0W

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)

W0W - Word 0 Width

I2S_TCR5_WNW [1/3]

#define I2S_TCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

WNW - Word N Width

I2S_TCR5_WNW [2/3]

#define I2S_TCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

WNW - Word N Width

I2S_TCR5_WNW [3/3]

#define I2S_TCR5_WNW

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)

WNW - Word N Width

I2S_TCSR_BCE [1/3]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_BCE [2/3]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_BCE [3/3]

#define I2S_TCSR_BCE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)

BCE - Bit Clock Enable 0b0..Transmit bit clock is disabled. 0b1..Transmit bit clock is enabled.

I2S_TCSR_DBGE [1/3]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_DBGE [2/3]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_DBGE [3/3]

#define I2S_TCSR_DBGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)

DBGE - Debug Enable 0b0..Transmitter is disabled in Debug mode, after completing the current frame. 0b1..Transmitter is enabled in Debug mode.

I2S_TCSR_FEF [1/3]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEF [2/3]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEF [3/3]

#define I2S_TCSR_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)

FEF - FIFO Error Flag 0b0..Transmit underrun not detected. 0b1..Transmit underrun detected.

I2S_TCSR_FEIE [1/3]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FEIE [2/3]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FEIE [3/3]

#define I2S_TCSR_FEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)

FEIE - FIFO Error Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FR [1/3]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FR [2/3]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FR [3/3]

#define I2S_TCSR_FR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)

FR - FIFO Reset 0b0..No effect. 0b1..FIFO reset.

I2S_TCSR_FRDE [1/3]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRDE [2/3]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRDE [3/3]

#define I2S_TCSR_FRDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)

FRDE - FIFO Request DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FRF [1/3]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRF [2/3]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRF [3/3]

#define I2S_TCSR_FRF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)

FRF - FIFO Request Flag 0b0..Transmit FIFO watermark has not been reached. 0b1..Transmit FIFO watermark has been reached.

I2S_TCSR_FRIE [1/3]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FRIE [2/3]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FRIE [3/3]

#define I2S_TCSR_FRIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)

FRIE - FIFO Request Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWDE [1/3]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWDE [2/3]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWDE [3/3]

#define I2S_TCSR_FWDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)

FWDE - FIFO Warning DMA Enable 0b0..Disables the DMA request. 0b1..Enables the DMA request.

I2S_TCSR_FWF [1/3]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWF [2/3]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWF [3/3]

#define I2S_TCSR_FWF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)

FWF - FIFO Warning Flag 0b0..No enabled transmit FIFO is empty. 0b1..Enabled transmit FIFO is empty.

I2S_TCSR_FWIE [1/3]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWIE [2/3]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_FWIE [3/3]

#define I2S_TCSR_FWIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)

FWIE - FIFO Warning Interrupt Enable 0b0..Disables the interrupt. 0b1..Enables the interrupt.

I2S_TCSR_SEF [1/3]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEF [2/3]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEF [3/3]

#define I2S_TCSR_SEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)

SEF - Sync Error Flag 0b0..Sync error not detected. 0b1..Frame sync error detected.

I2S_TCSR_SEIE [1/3]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SEIE [2/3]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SEIE [3/3]

#define I2S_TCSR_SEIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)

SEIE - Sync Error Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_SR [1/3]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_SR [2/3]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_SR [3/3]

#define I2S_TCSR_SR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)

SR - Software Reset 0b0..No effect. 0b1..Software reset.

I2S_TCSR_STOPE [1/3]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_STOPE [2/3]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_STOPE [3/3]

#define I2S_TCSR_STOPE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)

STOPE - Stop Enable 0b0..Transmitter disabled in Stop mode. 0b1..Transmitter enabled in Stop mode.

I2S_TCSR_TE [1/3]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_TE [2/3]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_TE [3/3]

#define I2S_TCSR_TE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter is disabled. 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.

I2S_TCSR_WSF [1/3]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSF [2/3]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSF [3/3]

#define I2S_TCSR_WSF

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)

WSF - Word Start Flag 0b0..Start of word not detected. 0b1..Start of word detected.

I2S_TCSR_WSIE [1/3]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_WSIE [2/3]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TCSR_WSIE [3/3]

#define I2S_TCSR_WSIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)

WSIE - Word Start Interrupt Enable 0b0..Disables interrupt. 0b1..Enables interrupt.

I2S_TDR_TDR [1/3]

#define I2S_TDR_TDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)

TDR - Transmit Data Register

I2S_TDR_TDR [2/3]

#define I2S_TDR_TDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)

TDR - Transmit Data Register

I2S_TDR_TDR [3/3]

#define I2S_TDR_TDR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)

TDR - Transmit Data Register

I2S_TFR_RFP [1/3]

#define I2S_TFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_TFR_RFP [2/3]

#define I2S_TFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_TFR_RFP [3/3]

#define I2S_TFR_RFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)

RFP - Read FIFO Pointer

I2S_TFR_WCP [1/3]

#define I2S_TFR_WCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.

I2S_TFR_WCP [2/3]

#define I2S_TFR_WCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.

I2S_TFR_WCP [3/3]

#define I2S_TFR_WCP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)

WCP - Write Channel Pointer 0b0..No effect. 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.

I2S_TFR_WFP [1/3]

#define I2S_TFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_TFR_WFP [2/3]

#define I2S_TFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_TFR_WFP [3/3]

#define I2S_TFR_WFP

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)

WFP - Write FIFO Pointer

I2S_TMR_TWM [1/3]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.

I2S_TMR_TWM [2/3]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.

I2S_TMR_TWM [3/3]

#define I2S_TMR_TWM

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)

TWM - Transmit Word Mask 0b00000000000000000000000000000000..Word N is enabled. 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.

I2S_VERID_FEATURE [1/3]

#define I2S_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard feature set.

I2S_VERID_FEATURE [2/3]

#define I2S_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard feature set.

I2S_VERID_FEATURE [3/3]

#define I2S_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard feature set.

I2S_VERID_MAJOR [1/3]

#define I2S_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)

MAJOR - Major Version Number

I2S_VERID_MAJOR [2/3]

#define I2S_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)

MAJOR - Major Version Number

I2S_VERID_MAJOR [3/3]

#define I2S_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)

MAJOR - Major Version Number

I2S_VERID_MINOR [1/3]

#define I2S_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

MINOR - Minor Version Number

I2S_VERID_MINOR [2/3]

#define I2S_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

MINOR - Minor Version Number

I2S_VERID_MINOR [3/3]

#define I2S_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPI2C_PARAM_MRXFIFO [1/2]

#define LPI2C_PARAM_MRXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

LPI2C_PARAM_MRXFIFO [2/2]

#define LPI2C_PARAM_MRXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)

MRXFIFO - Master Receive FIFO Size

LPI2C_PARAM_MTXFIFO [1/2]

#define LPI2C_PARAM_MTXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

LPI2C_PARAM_MTXFIFO [2/2]

#define LPI2C_PARAM_MTXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)

MTXFIFO - Master Transmit FIFO Size

LPI2C_VERID_FEATURE [1/2]

#define LPI2C_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

LPI2C_VERID_FEATURE [2/2]

#define LPI2C_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000010..Master only, with standard feature set 0b0000000000000011..Master and slave, with standard feature set

LPI2C_VERID_MAJOR [1/2]

#define LPI2C_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPI2C_VERID_MAJOR [2/2]

#define LPI2C_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPI2C_VERID_MINOR [1/2]

#define LPI2C_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPI2C_VERID_MINOR [2/2]

#define LPI2C_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPSPI_PARAM_PCSNUM [1/2]

#define LPSPI_PARAM_PCSNUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

PCSNUM - PCS Number

LPSPI_PARAM_PCSNUM [2/2]

#define LPSPI_PARAM_PCSNUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)

PCSNUM - PCS Number

LPSPI_PARAM_RXFIFO [1/2]

#define LPSPI_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPSPI_PARAM_RXFIFO [2/2]

#define LPSPI_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPSPI_PARAM_TXFIFO [1/2]

#define LPSPI_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPSPI_PARAM_TXFIFO [2/2]

#define LPSPI_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPSPI_RDR_DATA [1/2]

#define LPSPI_RDR_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

DATA - Receive Data

LPSPI_RDR_DATA [2/2]

#define LPSPI_RDR_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)

DATA - Receive Data

LPSPI_TDR_DATA [1/2]

#define LPSPI_TDR_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

DATA - Transmit Data

LPSPI_TDR_DATA [2/2]

#define LPSPI_TDR_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)

DATA - Transmit Data

LPSPI_VERID_FEATURE [1/2]

#define LPSPI_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

FEATURE - Module Identification Number 0b0000000000000100..Standard feature set supporting a 32-bit shift register.

LPSPI_VERID_FEATURE [2/2]

#define LPSPI_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)

FEATURE - Module Identification Number 0b0000000000000100..Standard feature set supporting a 32-bit shift register.

LPSPI_VERID_MAJOR [1/2]

#define LPSPI_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPSPI_VERID_MAJOR [2/2]

#define LPSPI_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPSPI_VERID_MINOR [1/2]

#define LPSPI_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPSPI_VERID_MINOR [2/2]

#define LPSPI_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)

MINOR - Minor Version Number