RTEMS 6.1-rc5
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Macros
GPC Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » GPC Peripheral Access Layer

Macros

#define GPC_IMR_COUNT   (4U)
 
#define GPC_ISR_COUNT   (4U)
 

CNTR - GPC Interface control register

#define GPC_CNTR_MEGA_PDN_REQ_MASK   (0x4U)
 
#define GPC_CNTR_MEGA_PDN_REQ_SHIFT   (2U)
 
#define GPC_CNTR_MEGA_PDN_REQ(x)   (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)
 
#define GPC_CNTR_MEGA_PUP_REQ_MASK   (0x8U)
 
#define GPC_CNTR_MEGA_PUP_REQ_SHIFT   (3U)
 
#define GPC_CNTR_MEGA_PUP_REQ(x)   (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)
 
#define GPC_CNTR_PDRAM0_PGE_MASK   (0x400000U)
 
#define GPC_CNTR_PDRAM0_PGE_SHIFT   (22U)
 
#define GPC_CNTR_PDRAM0_PGE(x)   (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)
 

IMR - IRQ masking register 1..IRQ masking register 4

#define GPC_IMR_IMR1_MASK   (0xFFFFFFFFU)
 
#define GPC_IMR_IMR1_SHIFT   (0U)
 
#define GPC_IMR_IMR1(x)   (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
 
#define GPC_IMR_IMR2_MASK   (0xFFFFFFFFU)
 
#define GPC_IMR_IMR2_SHIFT   (0U)
 
#define GPC_IMR_IMR2(x)   (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK)
 
#define GPC_IMR_IMR3_MASK   (0xFFFFFFFFU)
 
#define GPC_IMR_IMR3_SHIFT   (0U)
 
#define GPC_IMR_IMR3(x)   (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK)
 
#define GPC_IMR_IMR4_MASK   (0xFFFFFFFFU)
 
#define GPC_IMR_IMR4_SHIFT   (0U)
 
#define GPC_IMR_IMR4(x)   (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
 

ISR - IRQ status resister 1..IRQ status resister 4

#define GPC_ISR_ISR1_MASK   (0xFFFFFFFFU)
 
#define GPC_ISR_ISR1_SHIFT   (0U)
 
#define GPC_ISR_ISR1(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK)
 
#define GPC_ISR_ISR2_MASK   (0xFFFFFFFFU)
 
#define GPC_ISR_ISR2_SHIFT   (0U)
 
#define GPC_ISR_ISR2(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK)
 
#define GPC_ISR_ISR3_MASK   (0xFFFFFFFFU)
 
#define GPC_ISR_ISR3_SHIFT   (0U)
 
#define GPC_ISR_ISR3(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK)
 
#define GPC_ISR_ISR4_MASK   (0xFFFFFFFFU)
 
#define GPC_ISR_ISR4_SHIFT   (0U)
 
#define GPC_ISR_ISR4(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK)
 

IMR5 - IRQ masking register 5

#define GPC_IMR5_IMR5_MASK   (0xFFFFFFFFU)
 
#define GPC_IMR5_IMR5_SHIFT   (0U)
 
#define GPC_IMR5_IMR5(x)   (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK)
 

ISR5 - IRQ status resister 5

#define GPC_ISR5_ISR5_MASK   (0xFFFFFFFFU)
 
#define GPC_ISR5_ISR5_SHIFT   (0U)
 
#define GPC_ISR5_ISR5(x)   (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR5_SHIFT)) & GPC_ISR5_ISR5_MASK)
 

Detailed Description

Macro Definition Documentation

◆ GPC_CNTR_MEGA_PDN_REQ

#define GPC_CNTR_MEGA_PDN_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK)

MEGA_PDN_REQ 0b0..No Request 0b1..Request power down sequence

◆ GPC_CNTR_MEGA_PUP_REQ

#define GPC_CNTR_MEGA_PUP_REQ (   x)    (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK)

MEGA_PUP_REQ 0b0..No Request 0b1..Request power up sequence

◆ GPC_CNTR_PDRAM0_PGE

#define GPC_CNTR_PDRAM0_PGE (   x)    (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK)

PDRAM0_PGE 0b1..FlexRAM PDRAM0 domain will be powered down when the CPU core is powered down.. 0b0..FlexRAM PDRAM0 domain will keep power even if the CPU core is powered down.

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