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#define | EXTI_PROPERTY_SHIFT 24U |
| EXTI Line property definition.
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#define | EXTI_DIRECT (0x01UL << EXTI_PROPERTY_SHIFT) |
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#define | EXTI_CONFIG (0x02UL << EXTI_PROPERTY_SHIFT) |
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#define | EXTI_GPIO ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) |
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#define | EXTI_RESERVED (0x08UL << EXTI_PROPERTY_SHIFT) |
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#define | EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) |
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#define | EXTI_EVENT_PRESENCE_SHIFT 28U |
| EXTI Event presence definition.
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#define | EXTI_EVENT (0x01UL << EXTI_EVENT_PRESENCE_SHIFT) |
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#define | EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT) |
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#define | EXTI_REG_SHIFT 16U |
| EXTI Register and bit usage.
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#define | EXTI_REG1 (0x00UL << EXTI_REG_SHIFT) |
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#define | EXTI_REG2 (0x01UL << EXTI_REG_SHIFT) |
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#define | EXTI_REG3 (0x02UL << EXTI_REG_SHIFT) |
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#define | EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2 | EXTI_REG3) |
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#define | EXTI_PIN_MASK 0x0000001FUL |
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#define | EXTI_TARGET_SHIFT 20U |
| EXTI Target and bit usage.
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#define | EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT) |
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#define | EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT) |
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#define | EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT) |
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#define | EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1) |
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#define | EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1 |
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#define | EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK |
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#define | EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) |
| EXTI Mask for interrupt & event mode.
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#define | EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) |
| EXTI Mask for trigger possibilities.
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#define | EXTI_LINE_NB 88UL |
| EXTI Line number.
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