DMA Request selection. More...

Macros
#define	DMA_REQUEST_MEM2MEM 0U

#define	DMA_REQUEST_GENERATOR0 1U

#define	DMA_REQUEST_GENERATOR1 2U

#define	DMA_REQUEST_GENERATOR2 3U

#define	DMA_REQUEST_GENERATOR3 4U

#define	DMA_REQUEST_GENERATOR4 5U

#define	DMA_REQUEST_GENERATOR5 6U

#define	DMA_REQUEST_GENERATOR6 7U

#define	DMA_REQUEST_GENERATOR7 8U

#define	DMA_REQUEST_ADC1 9U

#define	DMA_REQUEST_ADC2 10U

#define	DMA_REQUEST_TIM1_CH1 11U

#define	DMA_REQUEST_TIM1_CH2 12U

#define	DMA_REQUEST_TIM1_CH3 13U

#define	DMA_REQUEST_TIM1_CH4 14U

#define	DMA_REQUEST_TIM1_UP 15U

#define	DMA_REQUEST_TIM1_TRIG 16U

#define	DMA_REQUEST_TIM1_COM 17U

#define	DMA_REQUEST_TIM2_CH1 18U

#define	DMA_REQUEST_TIM2_CH2 19U

#define	DMA_REQUEST_TIM2_CH3 20U

#define	DMA_REQUEST_TIM2_CH4 21U

#define	DMA_REQUEST_TIM2_UP 22U

#define	DMA_REQUEST_TIM3_CH1 23U

#define	DMA_REQUEST_TIM3_CH2 24U

#define	DMA_REQUEST_TIM3_CH3 25U

#define	DMA_REQUEST_TIM3_CH4 26U

#define	DMA_REQUEST_TIM3_UP 27U

#define	DMA_REQUEST_TIM3_TRIG 28U

#define	DMA_REQUEST_TIM4_CH1 29U

#define	DMA_REQUEST_TIM4_CH2 30U

#define	DMA_REQUEST_TIM4_CH3 31U

#define	DMA_REQUEST_TIM4_UP 32U

#define	DMA_REQUEST_I2C1_RX 33U

#define	DMA_REQUEST_I2C1_TX 34U

#define	DMA_REQUEST_I2C2_RX 35U

#define	DMA_REQUEST_I2C2_TX 36U

#define	DMA_REQUEST_SPI1_RX 37U

#define	DMA_REQUEST_SPI1_TX 38U

#define	DMA_REQUEST_SPI2_RX 39U

#define	DMA_REQUEST_SPI2_TX 40U

#define	DMA_REQUEST_USART1_RX 41U

#define	DMA_REQUEST_USART1_TX 42U

#define	DMA_REQUEST_USART2_RX 43U

#define	DMA_REQUEST_USART2_TX 44U

#define	DMA_REQUEST_USART3_RX 45U

#define	DMA_REQUEST_USART3_TX 46U

#define	DMA_REQUEST_TIM8_CH1 47U

#define	DMA_REQUEST_TIM8_CH2 48U

#define	DMA_REQUEST_TIM8_CH3 49U

#define	DMA_REQUEST_TIM8_CH4 50U

#define	DMA_REQUEST_TIM8_UP 51U

#define	DMA_REQUEST_TIM8_TRIG 52U

#define	DMA_REQUEST_TIM8_COM 53U

#define	DMA_REQUEST_TIM5_CH1 55U

#define	DMA_REQUEST_TIM5_CH2 56U

#define	DMA_REQUEST_TIM5_CH3 57U

#define	DMA_REQUEST_TIM5_CH4 58U

#define	DMA_REQUEST_TIM5_UP 59U

#define	DMA_REQUEST_TIM5_TRIG 60U

#define	DMA_REQUEST_SPI3_RX 61U

#define	DMA_REQUEST_SPI3_TX 62U

#define	DMA_REQUEST_UART4_RX 63U

#define	DMA_REQUEST_UART4_TX 64U

#define	DMA_REQUEST_UART5_RX 65U

#define	DMA_REQUEST_UART5_TX 66U

#define	DMA_REQUEST_DAC1_CH1 67U

#define	DMA_REQUEST_DAC1_CH2 68U

#define	DMA_REQUEST_TIM6_UP 69U

#define	DMA_REQUEST_TIM7_UP 70U

#define	DMA_REQUEST_USART6_RX 71U

#define	DMA_REQUEST_USART6_TX 72U

#define	DMA_REQUEST_I2C3_RX 73U

#define	DMA_REQUEST_I2C3_TX 74U

#define	DMA_REQUEST_DCMI 75U

#define	DMA_REQUEST_CRYP_IN 76U

#define	DMA_REQUEST_CRYP_OUT 77U

#define	DMA_REQUEST_HASH_IN 78U

#define	DMA_REQUEST_UART7_RX 79U

#define	DMA_REQUEST_UART7_TX 80U

#define	DMA_REQUEST_UART8_RX 81U

#define	DMA_REQUEST_UART8_TX 82U

#define	DMA_REQUEST_SPI4_RX 83U

#define	DMA_REQUEST_SPI4_TX 84U

#define	DMA_REQUEST_SPI5_RX 85U

#define	DMA_REQUEST_SPI5_TX 86U

#define	DMA_REQUEST_SAI1_A 87U

#define	DMA_REQUEST_SAI1_B 88U

#define	DMA_REQUEST_SWPMI_RX 91U

#define	DMA_REQUEST_SWPMI_TX 92U

#define	DMA_REQUEST_SPDIF_RX_DT 93U

#define	DMA_REQUEST_SPDIF_RX_CS 94U

#define	DMA_REQUEST_DFSDM1_FLT0 101U

#define	DMA_REQUEST_DFSDM1_FLT1 102U

#define	DMA_REQUEST_DFSDM1_FLT2 103U

#define	DMA_REQUEST_DFSDM1_FLT3 104U

#define	DMA_REQUEST_TIM15_CH1 105U

#define	DMA_REQUEST_TIM15_UP 106U

#define	DMA_REQUEST_TIM15_TRIG 107U

#define	DMA_REQUEST_TIM15_COM 108U

#define	DMA_REQUEST_TIM16_CH1 109U

#define	DMA_REQUEST_TIM16_UP 110U

#define	DMA_REQUEST_TIM17_CH1 111U

#define	DMA_REQUEST_TIM17_UP 112U

#define	BDMA_REQUEST_MEM2MEM 0U

#define	BDMA_REQUEST_GENERATOR0 1U

#define	BDMA_REQUEST_GENERATOR1 2U

#define	BDMA_REQUEST_GENERATOR2 3U

#define	BDMA_REQUEST_GENERATOR3 4U

#define	BDMA_REQUEST_GENERATOR4 5U

#define	BDMA_REQUEST_GENERATOR5 6U

#define	BDMA_REQUEST_GENERATOR6 7U

#define	BDMA_REQUEST_GENERATOR7 8U

#define	BDMA_REQUEST_LPUART1_RX 9U

#define	BDMA_REQUEST_LPUART1_TX 10U

#define	BDMA_REQUEST_SPI6_RX 11U

#define	BDMA_REQUEST_SPI6_TX 12U

#define	BDMA_REQUEST_I2C4_RX 13U

#define	BDMA_REQUEST_I2C4_TX 14U

Detailed Description

DMA Request selection.

Macro Definition Documentation

◆ BDMA_REQUEST_GENERATOR0

#define BDMA_REQUEST_GENERATOR0 1U

DMAMUX2 request generator 0

◆ BDMA_REQUEST_GENERATOR1

#define BDMA_REQUEST_GENERATOR1 2U

DMAMUX2 request generator 1

◆ BDMA_REQUEST_GENERATOR2

#define BDMA_REQUEST_GENERATOR2 3U

DMAMUX2 request generator 2

◆ BDMA_REQUEST_GENERATOR3

#define BDMA_REQUEST_GENERATOR3 4U

DMAMUX2 request generator 3

◆ BDMA_REQUEST_GENERATOR4

#define BDMA_REQUEST_GENERATOR4 5U

DMAMUX2 request generator 4

◆ BDMA_REQUEST_GENERATOR5

#define BDMA_REQUEST_GENERATOR5 6U

DMAMUX2 request generator 5

◆ BDMA_REQUEST_GENERATOR6

#define BDMA_REQUEST_GENERATOR6 7U

DMAMUX2 request generator 6

◆ BDMA_REQUEST_GENERATOR7

#define BDMA_REQUEST_GENERATOR7 8U

DMAMUX2 request generator 7

◆ BDMA_REQUEST_I2C4_RX

#define BDMA_REQUEST_I2C4_RX 13U

DMAMUX2 I2C4 RX request

◆ BDMA_REQUEST_I2C4_TX

#define BDMA_REQUEST_I2C4_TX 14U

DMAMUX2 I2C4 TX request

◆ BDMA_REQUEST_LPUART1_RX

#define BDMA_REQUEST_LPUART1_RX 9U

DMAMUX2 LP_UART1_RX request

◆ BDMA_REQUEST_LPUART1_TX

#define BDMA_REQUEST_LPUART1_TX 10U

DMAMUX2 LP_UART1_TX request

◆ BDMA_REQUEST_MEM2MEM

#define BDMA_REQUEST_MEM2MEM 0U

memory to memory transfer

◆ BDMA_REQUEST_SPI6_RX

#define BDMA_REQUEST_SPI6_RX 11U

DMAMUX2 SPI6 RX request

◆ BDMA_REQUEST_SPI6_TX

#define BDMA_REQUEST_SPI6_TX 12U

DMAMUX2 SPI6 TX request

◆ DMA_REQUEST_ADC1

#define DMA_REQUEST_ADC1 9U

DMAMUX1 ADC1 request

◆ DMA_REQUEST_ADC2

#define DMA_REQUEST_ADC2 10U

DMAMUX1 ADC2 request

◆ DMA_REQUEST_CRYP_IN

#define DMA_REQUEST_CRYP_IN 76U

DMAMUX1 CRYP IN request

◆ DMA_REQUEST_CRYP_OUT

#define DMA_REQUEST_CRYP_OUT 77U

DMAMUX1 CRYP OUT request

◆ DMA_REQUEST_DAC1_CH1

#define DMA_REQUEST_DAC1_CH1 67U

DMAMUX1 DAC1 Channel 1 request

◆ DMA_REQUEST_DAC1_CH2

#define DMA_REQUEST_DAC1_CH2 68U

DMAMUX1 DAC1 Channel 2 request

◆ DMA_REQUEST_DCMI

#define DMA_REQUEST_DCMI 75U

DMAMUX1 DCMI request

◆ DMA_REQUEST_DFSDM1_FLT0

#define DMA_REQUEST_DFSDM1_FLT0 101U

DMAMUX1 DFSDM Filter0 request

◆ DMA_REQUEST_DFSDM1_FLT1

#define DMA_REQUEST_DFSDM1_FLT1 102U

DMAMUX1 DFSDM Filter1 request

◆ DMA_REQUEST_DFSDM1_FLT2

#define DMA_REQUEST_DFSDM1_FLT2 103U

DMAMUX1 DFSDM Filter2 request

◆ DMA_REQUEST_DFSDM1_FLT3

#define DMA_REQUEST_DFSDM1_FLT3 104U

DMAMUX1 DFSDM Filter3 request

◆ DMA_REQUEST_GENERATOR0

#define DMA_REQUEST_GENERATOR0 1U

DMAMUX1 request generator 0

◆ DMA_REQUEST_GENERATOR1

#define DMA_REQUEST_GENERATOR1 2U

DMAMUX1 request generator 1

◆ DMA_REQUEST_GENERATOR2

#define DMA_REQUEST_GENERATOR2 3U

DMAMUX1 request generator 2

◆ DMA_REQUEST_GENERATOR3

#define DMA_REQUEST_GENERATOR3 4U

DMAMUX1 request generator 3

◆ DMA_REQUEST_GENERATOR4

#define DMA_REQUEST_GENERATOR4 5U

DMAMUX1 request generator 4

◆ DMA_REQUEST_GENERATOR5

#define DMA_REQUEST_GENERATOR5 6U

DMAMUX1 request generator 5

◆ DMA_REQUEST_GENERATOR6

#define DMA_REQUEST_GENERATOR6 7U

DMAMUX1 request generator 6

◆ DMA_REQUEST_GENERATOR7

#define DMA_REQUEST_GENERATOR7 8U

DMAMUX1 request generator 7

◆ DMA_REQUEST_HASH_IN

#define DMA_REQUEST_HASH_IN 78U

DMAMUX1 HASH IN request

◆ DMA_REQUEST_I2C1_RX

#define DMA_REQUEST_I2C1_RX 33U

DMAMUX1 I2C1 RX request

◆ DMA_REQUEST_I2C1_TX

#define DMA_REQUEST_I2C1_TX 34U

DMAMUX1 I2C1 TX request

◆ DMA_REQUEST_I2C2_RX

#define DMA_REQUEST_I2C2_RX 35U

DMAMUX1 I2C2 RX request

◆ DMA_REQUEST_I2C2_TX

#define DMA_REQUEST_I2C2_TX 36U

DMAMUX1 I2C2 TX request

◆ DMA_REQUEST_I2C3_RX

#define DMA_REQUEST_I2C3_RX 73U

DMAMUX1 I2C3 RX request

◆ DMA_REQUEST_I2C3_TX

#define DMA_REQUEST_I2C3_TX 74U

DMAMUX1 I2C3 TX request

◆ DMA_REQUEST_MEM2MEM

#define DMA_REQUEST_MEM2MEM 0U

memory to memory transfer

◆ DMA_REQUEST_SAI1_A

#define DMA_REQUEST_SAI1_A 87U

DMAMUX1 SAI1 A request

◆ DMA_REQUEST_SAI1_B

#define DMA_REQUEST_SAI1_B 88U

DMAMUX1 SAI1 B request

◆ DMA_REQUEST_SPDIF_RX_CS

#define DMA_REQUEST_SPDIF_RX_CS 94U

DMAMUX1 SPDIF RXCS request

◆ DMA_REQUEST_SPDIF_RX_DT

#define DMA_REQUEST_SPDIF_RX_DT 93U

DMAMUX1 SPDIF RXDT request

◆ DMA_REQUEST_SPI1_RX

#define DMA_REQUEST_SPI1_RX 37U

DMAMUX1 SPI1 RX request

◆ DMA_REQUEST_SPI1_TX

#define DMA_REQUEST_SPI1_TX 38U

DMAMUX1 SPI1 TX request

◆ DMA_REQUEST_SPI2_RX

#define DMA_REQUEST_SPI2_RX 39U

DMAMUX1 SPI2 RX request

◆ DMA_REQUEST_SPI2_TX

#define DMA_REQUEST_SPI2_TX 40U

DMAMUX1 SPI2 TX request

◆ DMA_REQUEST_SPI3_RX

#define DMA_REQUEST_SPI3_RX 61U

DMAMUX1 SPI3 RX request

◆ DMA_REQUEST_SPI3_TX

#define DMA_REQUEST_SPI3_TX 62U

DMAMUX1 SPI3 TX request

◆ DMA_REQUEST_SPI4_RX

#define DMA_REQUEST_SPI4_RX 83U

DMAMUX1 SPI4 RX request

◆ DMA_REQUEST_SPI4_TX

#define DMA_REQUEST_SPI4_TX 84U

DMAMUX1 SPI4 TX request

◆ DMA_REQUEST_SPI5_RX

#define DMA_REQUEST_SPI5_RX 85U

DMAMUX1 SPI5 RX request

◆ DMA_REQUEST_SPI5_TX

#define DMA_REQUEST_SPI5_TX 86U

DMAMUX1 SPI5 TX request

◆ DMA_REQUEST_SWPMI_RX

#define DMA_REQUEST_SWPMI_RX 91U

DMAMUX1 SWPMI RX request

◆ DMA_REQUEST_SWPMI_TX

#define DMA_REQUEST_SWPMI_TX 92U

DMAMUX1 SWPMI TX request

◆ DMA_REQUEST_TIM15_CH1

#define DMA_REQUEST_TIM15_CH1 105U

DMAMUX1 TIM15 CH1 request

◆ DMA_REQUEST_TIM15_COM

#define DMA_REQUEST_TIM15_COM 108U

DMAMUX1 TIM15 COM request

◆ DMA_REQUEST_TIM15_TRIG

#define DMA_REQUEST_TIM15_TRIG 107U

DMAMUX1 TIM15 TRIG request

◆ DMA_REQUEST_TIM15_UP

#define DMA_REQUEST_TIM15_UP 106U

DMAMUX1 TIM15 UP request

◆ DMA_REQUEST_TIM16_CH1

#define DMA_REQUEST_TIM16_CH1 109U

DMAMUX1 TIM16 CH1 request

◆ DMA_REQUEST_TIM16_UP

#define DMA_REQUEST_TIM16_UP 110U

DMAMUX1 TIM16 UP request

◆ DMA_REQUEST_TIM17_CH1

#define DMA_REQUEST_TIM17_CH1 111U

DMAMUX1 TIM17 CH1 request

◆ DMA_REQUEST_TIM17_UP

#define DMA_REQUEST_TIM17_UP 112U

DMAMUX1 TIM17 UP request

◆ DMA_REQUEST_TIM1_CH1

#define DMA_REQUEST_TIM1_CH1 11U

DMAMUX1 TIM1 CH1 request

◆ DMA_REQUEST_TIM1_CH2

#define DMA_REQUEST_TIM1_CH2 12U

DMAMUX1 TIM1 CH2 request

◆ DMA_REQUEST_TIM1_CH3

#define DMA_REQUEST_TIM1_CH3 13U

DMAMUX1 TIM1 CH3 request

◆ DMA_REQUEST_TIM1_CH4

#define DMA_REQUEST_TIM1_CH4 14U

DMAMUX1 TIM1 CH4 request

◆ DMA_REQUEST_TIM1_COM

#define DMA_REQUEST_TIM1_COM 17U

DMAMUX1 TIM1 COM request

◆ DMA_REQUEST_TIM1_TRIG

#define DMA_REQUEST_TIM1_TRIG 16U

DMAMUX1 TIM1 TRIG request

◆ DMA_REQUEST_TIM1_UP

#define DMA_REQUEST_TIM1_UP 15U

DMAMUX1 TIM1 UP request

◆ DMA_REQUEST_TIM2_CH1

#define DMA_REQUEST_TIM2_CH1 18U

DMAMUX1 TIM2 CH1 request

◆ DMA_REQUEST_TIM2_CH2

#define DMA_REQUEST_TIM2_CH2 19U

DMAMUX1 TIM2 CH2 request

◆ DMA_REQUEST_TIM2_CH3

#define DMA_REQUEST_TIM2_CH3 20U

DMAMUX1 TIM2 CH3 request

◆ DMA_REQUEST_TIM2_CH4

#define DMA_REQUEST_TIM2_CH4 21U

DMAMUX1 TIM2 CH4 request

◆ DMA_REQUEST_TIM2_UP

#define DMA_REQUEST_TIM2_UP 22U

DMAMUX1 TIM2 UP request

◆ DMA_REQUEST_TIM3_CH1

#define DMA_REQUEST_TIM3_CH1 23U

DMAMUX1 TIM3 CH1 request

◆ DMA_REQUEST_TIM3_CH2

#define DMA_REQUEST_TIM3_CH2 24U

DMAMUX1 TIM3 CH2 request

◆ DMA_REQUEST_TIM3_CH3

#define DMA_REQUEST_TIM3_CH3 25U

DMAMUX1 TIM3 CH3 request

◆ DMA_REQUEST_TIM3_CH4

#define DMA_REQUEST_TIM3_CH4 26U

DMAMUX1 TIM3 CH4 request

◆ DMA_REQUEST_TIM3_TRIG

#define DMA_REQUEST_TIM3_TRIG 28U

DMAMUX1 TIM3 TRIG request

◆ DMA_REQUEST_TIM3_UP

#define DMA_REQUEST_TIM3_UP 27U

DMAMUX1 TIM3 UP request

◆ DMA_REQUEST_TIM4_CH1

#define DMA_REQUEST_TIM4_CH1 29U

DMAMUX1 TIM4 CH1 request

◆ DMA_REQUEST_TIM4_CH2

#define DMA_REQUEST_TIM4_CH2 30U

DMAMUX1 TIM4 CH2 request

◆ DMA_REQUEST_TIM4_CH3

#define DMA_REQUEST_TIM4_CH3 31U

DMAMUX1 TIM4 CH3 request

◆ DMA_REQUEST_TIM4_UP

#define DMA_REQUEST_TIM4_UP 32U

DMAMUX1 TIM4 UP request

◆ DMA_REQUEST_TIM5_CH1

#define DMA_REQUEST_TIM5_CH1 55U

DMAMUX1 TIM5 CH1 request

◆ DMA_REQUEST_TIM5_CH2

#define DMA_REQUEST_TIM5_CH2 56U

DMAMUX1 TIM5 CH2 request

◆ DMA_REQUEST_TIM5_CH3

#define DMA_REQUEST_TIM5_CH3 57U

DMAMUX1 TIM5 CH3 request

◆ DMA_REQUEST_TIM5_CH4

#define DMA_REQUEST_TIM5_CH4 58U

DMAMUX1 TIM5 CH4 request

◆ DMA_REQUEST_TIM5_TRIG

#define DMA_REQUEST_TIM5_TRIG 60U

DMAMUX1 TIM5 TRIG request

◆ DMA_REQUEST_TIM5_UP

#define DMA_REQUEST_TIM5_UP 59U

DMAMUX1 TIM5 UP request

◆ DMA_REQUEST_TIM6_UP

#define DMA_REQUEST_TIM6_UP 69U

DMAMUX1 TIM6 UP request

◆ DMA_REQUEST_TIM7_UP

#define DMA_REQUEST_TIM7_UP 70U

DMAMUX1 TIM7 UP request

◆ DMA_REQUEST_TIM8_CH1

#define DMA_REQUEST_TIM8_CH1 47U

DMAMUX1 TIM8 CH1 request

◆ DMA_REQUEST_TIM8_CH2

#define DMA_REQUEST_TIM8_CH2 48U

DMAMUX1 TIM8 CH2 request

◆ DMA_REQUEST_TIM8_CH3

#define DMA_REQUEST_TIM8_CH3 49U

DMAMUX1 TIM8 CH3 request

◆ DMA_REQUEST_TIM8_CH4

#define DMA_REQUEST_TIM8_CH4 50U

DMAMUX1 TIM8 CH4 request

◆ DMA_REQUEST_TIM8_COM

#define DMA_REQUEST_TIM8_COM 53U

DMAMUX1 TIM8 COM request

◆ DMA_REQUEST_TIM8_TRIG

#define DMA_REQUEST_TIM8_TRIG 52U

DMAMUX1 TIM8 TRIG request

◆ DMA_REQUEST_TIM8_UP

#define DMA_REQUEST_TIM8_UP 51U

DMAMUX1 TIM8 UP request

◆ DMA_REQUEST_UART4_RX

#define DMA_REQUEST_UART4_RX 63U

DMAMUX1 UART4 RX request

◆ DMA_REQUEST_UART4_TX

#define DMA_REQUEST_UART4_TX 64U

DMAMUX1 UART4 TX request

◆ DMA_REQUEST_UART5_RX

#define DMA_REQUEST_UART5_RX 65U

DMAMUX1 UART5 RX request

◆ DMA_REQUEST_UART5_TX

#define DMA_REQUEST_UART5_TX 66U

DMAMUX1 UART5 TX request

◆ DMA_REQUEST_UART7_RX

#define DMA_REQUEST_UART7_RX 79U

DMAMUX1 UART7 RX request

◆ DMA_REQUEST_UART7_TX

#define DMA_REQUEST_UART7_TX 80U

DMAMUX1 UART7 TX request

◆ DMA_REQUEST_UART8_RX

#define DMA_REQUEST_UART8_RX 81U

DMAMUX1 UART8 RX request

◆ DMA_REQUEST_UART8_TX

#define DMA_REQUEST_UART8_TX 82U

DMAMUX1 UART8 TX request

◆ DMA_REQUEST_USART1_RX

#define DMA_REQUEST_USART1_RX 41U

DMAMUX1 USART1 RX request

◆ DMA_REQUEST_USART1_TX

#define DMA_REQUEST_USART1_TX 42U

DMAMUX1 USART1 TX request

◆ DMA_REQUEST_USART2_RX

#define DMA_REQUEST_USART2_RX 43U

DMAMUX1 USART2 RX request

◆ DMA_REQUEST_USART2_TX

#define DMA_REQUEST_USART2_TX 44U

DMAMUX1 USART2 TX request

◆ DMA_REQUEST_USART3_RX

#define DMA_REQUEST_USART3_RX 45U

DMAMUX1 USART3 RX request

◆ DMA_REQUEST_USART3_TX

#define DMA_REQUEST_USART3_TX 46U

DMAMUX1 USART3 TX request

◆ DMA_REQUEST_USART6_RX

#define DMA_REQUEST_USART6_RX 71U

DMAMUX1 USART6 RX request

◆ DMA_REQUEST_USART6_TX

#define DMA_REQUEST_USART6_TX 72U

DMAMUX1 USART6 TX request

Macros