RTEMS 6.1-rc5
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Macros
CSU Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » CSU Peripheral Access Layer

Macros

#define CSU_CSL_COUNT   (32U)
 

CSL - Config security level register

#define CSU_CSL_SUR_S2_MASK   (0x1U)
 
#define CSU_CSL_SUR_S2_SHIFT   (0U)
 
#define CSU_CSL_SUR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
 
#define CSU_CSL_SSR_S2_MASK   (0x2U)
 
#define CSU_CSL_SSR_S2_SHIFT   (1U)
 
#define CSU_CSL_SSR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
 
#define CSU_CSL_NUR_S2_MASK   (0x4U)
 
#define CSU_CSL_NUR_S2_SHIFT   (2U)
 
#define CSU_CSL_NUR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
 
#define CSU_CSL_NSR_S2_MASK   (0x8U)
 
#define CSU_CSL_NSR_S2_SHIFT   (3U)
 
#define CSU_CSL_NSR_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
 
#define CSU_CSL_SUW_S2_MASK   (0x10U)
 
#define CSU_CSL_SUW_S2_SHIFT   (4U)
 
#define CSU_CSL_SUW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
 
#define CSU_CSL_SSW_S2_MASK   (0x20U)
 
#define CSU_CSL_SSW_S2_SHIFT   (5U)
 
#define CSU_CSL_SSW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
 
#define CSU_CSL_NUW_S2_MASK   (0x40U)
 
#define CSU_CSL_NUW_S2_SHIFT   (6U)
 
#define CSU_CSL_NUW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
 
#define CSU_CSL_NSW_S2_MASK   (0x80U)
 
#define CSU_CSL_NSW_S2_SHIFT   (7U)
 
#define CSU_CSL_NSW_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
 
#define CSU_CSL_LOCK_S2_MASK   (0x100U)
 
#define CSU_CSL_LOCK_S2_SHIFT   (8U)
 
#define CSU_CSL_LOCK_S2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
 
#define CSU_CSL_SUR_S1_MASK   (0x10000U)
 
#define CSU_CSL_SUR_S1_SHIFT   (16U)
 
#define CSU_CSL_SUR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
 
#define CSU_CSL_SSR_S1_MASK   (0x20000U)
 
#define CSU_CSL_SSR_S1_SHIFT   (17U)
 
#define CSU_CSL_SSR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
 
#define CSU_CSL_NUR_S1_MASK   (0x40000U)
 
#define CSU_CSL_NUR_S1_SHIFT   (18U)
 
#define CSU_CSL_NUR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
 
#define CSU_CSL_NSR_S1_MASK   (0x80000U)
 
#define CSU_CSL_NSR_S1_SHIFT   (19U)
 
#define CSU_CSL_NSR_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
 
#define CSU_CSL_SUW_S1_MASK   (0x100000U)
 
#define CSU_CSL_SUW_S1_SHIFT   (20U)
 
#define CSU_CSL_SUW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
 
#define CSU_CSL_SSW_S1_MASK   (0x200000U)
 
#define CSU_CSL_SSW_S1_SHIFT   (21U)
 
#define CSU_CSL_SSW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
 
#define CSU_CSL_NUW_S1_MASK   (0x400000U)
 
#define CSU_CSL_NUW_S1_SHIFT   (22U)
 
#define CSU_CSL_NUW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
 
#define CSU_CSL_NSW_S1_MASK   (0x800000U)
 
#define CSU_CSL_NSW_S1_SHIFT   (23U)
 
#define CSU_CSL_NSW_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
 
#define CSU_CSL_LOCK_S1_MASK   (0x1000000U)
 
#define CSU_CSL_LOCK_S1_SHIFT   (24U)
 
#define CSU_CSL_LOCK_S1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
 

HP0 - HP0 register

#define CSU_HP0_HP_DMA_MASK   (0x4U)
 
#define CSU_HP0_HP_DMA_SHIFT   (2U)
 
#define CSU_HP0_HP_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
 
#define CSU_HP0_L_DMA_MASK   (0x8U)
 
#define CSU_HP0_L_DMA_SHIFT   (3U)
 
#define CSU_HP0_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
 
#define CSU_HP0_HP_LCDIF_MASK   (0x10U)
 
#define CSU_HP0_HP_LCDIF_SHIFT   (4U)
 
#define CSU_HP0_HP_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
 
#define CSU_HP0_L_LCDIF_MASK   (0x20U)
 
#define CSU_HP0_L_LCDIF_SHIFT   (5U)
 
#define CSU_HP0_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
 
#define CSU_HP0_HP_CSI_MASK   (0x40U)
 
#define CSU_HP0_HP_CSI_SHIFT   (6U)
 
#define CSU_HP0_HP_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
 
#define CSU_HP0_L_CSI_MASK   (0x80U)
 
#define CSU_HP0_L_CSI_SHIFT   (7U)
 
#define CSU_HP0_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
 
#define CSU_HP0_HP_PXP_MASK   (0x100U)
 
#define CSU_HP0_HP_PXP_SHIFT   (8U)
 
#define CSU_HP0_HP_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
 
#define CSU_HP0_L_PXP_MASK   (0x200U)
 
#define CSU_HP0_L_PXP_SHIFT   (9U)
 
#define CSU_HP0_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
 
#define CSU_HP0_HP_DCP_MASK   (0x400U)
 
#define CSU_HP0_HP_DCP_SHIFT   (10U)
 
#define CSU_HP0_HP_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
 
#define CSU_HP0_L_DCP_MASK   (0x800U)
 
#define CSU_HP0_L_DCP_SHIFT   (11U)
 
#define CSU_HP0_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
 
#define CSU_HP0_HP_ENET_MASK   (0x4000U)
 
#define CSU_HP0_HP_ENET_SHIFT   (14U)
 
#define CSU_HP0_HP_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
 
#define CSU_HP0_L_ENET_MASK   (0x8000U)
 
#define CSU_HP0_L_ENET_SHIFT   (15U)
 
#define CSU_HP0_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
 
#define CSU_HP0_HP_USDHC1_MASK   (0x10000U)
 
#define CSU_HP0_HP_USDHC1_SHIFT   (16U)
 
#define CSU_HP0_HP_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
 
#define CSU_HP0_L_USDHC1_MASK   (0x20000U)
 
#define CSU_HP0_L_USDHC1_SHIFT   (17U)
 
#define CSU_HP0_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
 
#define CSU_HP0_HP_USDHC2_MASK   (0x40000U)
 
#define CSU_HP0_HP_USDHC2_SHIFT   (18U)
 
#define CSU_HP0_HP_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
 
#define CSU_HP0_L_USDHC2_MASK   (0x80000U)
 
#define CSU_HP0_L_USDHC2_SHIFT   (19U)
 
#define CSU_HP0_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
 
#define CSU_HP0_HP_TPSMP_MASK   (0x100000U)
 
#define CSU_HP0_HP_TPSMP_SHIFT   (20U)
 
#define CSU_HP0_HP_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
 
#define CSU_HP0_L_TPSMP_MASK   (0x200000U)
 
#define CSU_HP0_L_TPSMP_SHIFT   (21U)
 
#define CSU_HP0_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
 
#define CSU_HP0_HP_USB_MASK   (0x400000U)
 
#define CSU_HP0_HP_USB_SHIFT   (22U)
 
#define CSU_HP0_HP_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
 
#define CSU_HP0_L_USB_MASK   (0x800000U)
 
#define CSU_HP0_L_USB_SHIFT   (23U)
 
#define CSU_HP0_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
 

SA - Secure access register

#define CSU_SA_NSA_DMA_MASK   (0x4U)
 
#define CSU_SA_NSA_DMA_SHIFT   (2U)
 
#define CSU_SA_NSA_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
 
#define CSU_SA_L_DMA_MASK   (0x8U)
 
#define CSU_SA_L_DMA_SHIFT   (3U)
 
#define CSU_SA_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
 
#define CSU_SA_NSA_LCDIF_MASK   (0x10U)
 
#define CSU_SA_NSA_LCDIF_SHIFT   (4U)
 
#define CSU_SA_NSA_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
 
#define CSU_SA_L_LCDIF_MASK   (0x20U)
 
#define CSU_SA_L_LCDIF_SHIFT   (5U)
 
#define CSU_SA_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
 
#define CSU_SA_NSA_CSI_MASK   (0x40U)
 
#define CSU_SA_NSA_CSI_SHIFT   (6U)
 
#define CSU_SA_NSA_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
 
#define CSU_SA_L_CSI_MASK   (0x80U)
 
#define CSU_SA_L_CSI_SHIFT   (7U)
 
#define CSU_SA_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
 
#define CSU_SA_NSA_PXP_MASK   (0x100U)
 
#define CSU_SA_NSA_PXP_SHIFT   (8U)
 
#define CSU_SA_NSA_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
 
#define CSU_SA_L_PXP_MASK   (0x200U)
 
#define CSU_SA_L_PXP_SHIFT   (9U)
 
#define CSU_SA_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
 
#define CSU_SA_NSA_DCP_MASK   (0x400U)
 
#define CSU_SA_NSA_DCP_SHIFT   (10U)
 
#define CSU_SA_NSA_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
 
#define CSU_SA_L_DCP_MASK   (0x800U)
 
#define CSU_SA_L_DCP_SHIFT   (11U)
 
#define CSU_SA_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
 
#define CSU_SA_NSA_ENET_MASK   (0x4000U)
 
#define CSU_SA_NSA_ENET_SHIFT   (14U)
 
#define CSU_SA_NSA_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
 
#define CSU_SA_L_ENET_MASK   (0x8000U)
 
#define CSU_SA_L_ENET_SHIFT   (15U)
 
#define CSU_SA_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
 
#define CSU_SA_NSA_USDHC1_MASK   (0x10000U)
 
#define CSU_SA_NSA_USDHC1_SHIFT   (16U)
 
#define CSU_SA_NSA_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
 
#define CSU_SA_L_USDHC1_MASK   (0x20000U)
 
#define CSU_SA_L_USDHC1_SHIFT   (17U)
 
#define CSU_SA_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
 
#define CSU_SA_NSA_USDHC2_MASK   (0x40000U)
 
#define CSU_SA_NSA_USDHC2_SHIFT   (18U)
 
#define CSU_SA_NSA_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
 
#define CSU_SA_L_USDHC2_MASK   (0x80000U)
 
#define CSU_SA_L_USDHC2_SHIFT   (19U)
 
#define CSU_SA_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
 
#define CSU_SA_NSA_TPSMP_MASK   (0x100000U)
 
#define CSU_SA_NSA_TPSMP_SHIFT   (20U)
 
#define CSU_SA_NSA_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
 
#define CSU_SA_L_TPSMP_MASK   (0x200000U)
 
#define CSU_SA_L_TPSMP_SHIFT   (21U)
 
#define CSU_SA_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
 
#define CSU_SA_NSA_USB_MASK   (0x400000U)
 
#define CSU_SA_NSA_USB_SHIFT   (22U)
 
#define CSU_SA_NSA_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
 
#define CSU_SA_L_USB_MASK   (0x800000U)
 
#define CSU_SA_L_USB_SHIFT   (23U)
 
#define CSU_SA_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
 

HPCONTROL0 - HPCONTROL0 register

#define CSU_HPCONTROL0_HPC_DMA_MASK   (0x4U)
 
#define CSU_HPCONTROL0_HPC_DMA_SHIFT   (2U)
 
#define CSU_HPCONTROL0_HPC_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
 
#define CSU_HPCONTROL0_L_DMA_MASK   (0x8U)
 
#define CSU_HPCONTROL0_L_DMA_SHIFT   (3U)
 
#define CSU_HPCONTROL0_L_DMA(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
 
#define CSU_HPCONTROL0_HPC_LCDIF_MASK   (0x10U)
 
#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT   (4U)
 
#define CSU_HPCONTROL0_HPC_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
 
#define CSU_HPCONTROL0_L_LCDIF_MASK   (0x20U)
 
#define CSU_HPCONTROL0_L_LCDIF_SHIFT   (5U)
 
#define CSU_HPCONTROL0_L_LCDIF(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
 
#define CSU_HPCONTROL0_HPC_CSI_MASK   (0x40U)
 
#define CSU_HPCONTROL0_HPC_CSI_SHIFT   (6U)
 
#define CSU_HPCONTROL0_HPC_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
 
#define CSU_HPCONTROL0_L_CSI_MASK   (0x80U)
 
#define CSU_HPCONTROL0_L_CSI_SHIFT   (7U)
 
#define CSU_HPCONTROL0_L_CSI(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
 
#define CSU_HPCONTROL0_HPC_PXP_MASK   (0x100U)
 
#define CSU_HPCONTROL0_HPC_PXP_SHIFT   (8U)
 
#define CSU_HPCONTROL0_HPC_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
 
#define CSU_HPCONTROL0_L_PXP_MASK   (0x200U)
 
#define CSU_HPCONTROL0_L_PXP_SHIFT   (9U)
 
#define CSU_HPCONTROL0_L_PXP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
 
#define CSU_HPCONTROL0_HPC_DCP_MASK   (0x400U)
 
#define CSU_HPCONTROL0_HPC_DCP_SHIFT   (10U)
 
#define CSU_HPCONTROL0_HPC_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
 
#define CSU_HPCONTROL0_L_DCP_MASK   (0x800U)
 
#define CSU_HPCONTROL0_L_DCP_SHIFT   (11U)
 
#define CSU_HPCONTROL0_L_DCP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
 
#define CSU_HPCONTROL0_HPC_ENET_MASK   (0x4000U)
 
#define CSU_HPCONTROL0_HPC_ENET_SHIFT   (14U)
 
#define CSU_HPCONTROL0_HPC_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
 
#define CSU_HPCONTROL0_L_ENET_MASK   (0x8000U)
 
#define CSU_HPCONTROL0_L_ENET_SHIFT   (15U)
 
#define CSU_HPCONTROL0_L_ENET(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
 
#define CSU_HPCONTROL0_HPC_USDHC1_MASK   (0x10000U)
 
#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT   (16U)
 
#define CSU_HPCONTROL0_HPC_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
 
#define CSU_HPCONTROL0_L_USDHC1_MASK   (0x20000U)
 
#define CSU_HPCONTROL0_L_USDHC1_SHIFT   (17U)
 
#define CSU_HPCONTROL0_L_USDHC1(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
 
#define CSU_HPCONTROL0_HPC_USDHC2_MASK   (0x40000U)
 
#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT   (18U)
 
#define CSU_HPCONTROL0_HPC_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
 
#define CSU_HPCONTROL0_L_USDHC2_MASK   (0x80000U)
 
#define CSU_HPCONTROL0_L_USDHC2_SHIFT   (19U)
 
#define CSU_HPCONTROL0_L_USDHC2(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
 
#define CSU_HPCONTROL0_HPC_TPSMP_MASK   (0x100000U)
 
#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT   (20U)
 
#define CSU_HPCONTROL0_HPC_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
 
#define CSU_HPCONTROL0_L_TPSMP_MASK   (0x200000U)
 
#define CSU_HPCONTROL0_L_TPSMP_SHIFT   (21U)
 
#define CSU_HPCONTROL0_L_TPSMP(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
 
#define CSU_HPCONTROL0_HPC_USB_MASK   (0x400000U)
 
#define CSU_HPCONTROL0_HPC_USB_SHIFT   (22U)
 
#define CSU_HPCONTROL0_HPC_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
 
#define CSU_HPCONTROL0_L_USB_MASK   (0x800000U)
 
#define CSU_HPCONTROL0_L_USB_SHIFT   (23U)
 
#define CSU_HPCONTROL0_L_USB(x)   (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
 

Detailed Description

Macro Definition Documentation

◆ CSU_CSL_LOCK_S1

#define CSU_CSL_LOCK_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)

LOCK_S1 0b0..Not locked. The bits 16-23 can be written by the software. 0b1..The bits 16-23 are locked and can't be written by the software.

◆ CSU_CSL_LOCK_S2

#define CSU_CSL_LOCK_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)

LOCK_S2 0b0..Not locked. Bits 7-0 can be written by the software. 0b1..Bits 7-0 are locked and cannot be written by the software

◆ CSU_CSL_NSR_S1

#define CSU_CSL_NSR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)

NSR_S1 0b0..The non-secure supervisor read access is disabled for the first slave. 0b1..The non-secure supervisor read access is enabled for the first slave.

◆ CSU_CSL_NSR_S2

#define CSU_CSL_NSR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)

NSR_S2 0b0..The non-secure supervisor read access is disabled for the second slave. 0b1..The non-secure supervisor read access is enabled for the second slave.

◆ CSU_CSL_NSW_S1

#define CSU_CSL_NSW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)

NSW_S1 0b0..The non-secure supervisor write access is disabled for the first slave. 0b1..The non-secure supervisor write access is enabled for the first slave

◆ CSU_CSL_NSW_S2

#define CSU_CSL_NSW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)

NSW_S2 0b0..The non-secure supervisor write access is disabled for the second slave. 0b1..The non-secure supervisor write access is enabled for the second slave.

◆ CSU_CSL_NUR_S1

#define CSU_CSL_NUR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)

NUR_S1 0b0..The non-secure user read access is disabled for the first slave. 0b1..The non-secure user read access is enabled for the first slave.

◆ CSU_CSL_NUR_S2

#define CSU_CSL_NUR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)

NUR_S2 0b0..The non-secure user read access is disabled for the second slave. 0b1..The non-secure user read access is enabled for the second slave.

◆ CSU_CSL_NUW_S1

#define CSU_CSL_NUW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)

NUW_S1 0b0..The non-secure user write access is disabled for the first slave. 0b1..The non-secure user write access is enabled for the first slave.

◆ CSU_CSL_NUW_S2

#define CSU_CSL_NUW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)

NUW_S2 0b0..The non-secure user write access is disabled for the second slave. 0b1..The non-secure user write access is enabled for the second slave.

◆ CSU_CSL_SSR_S1

#define CSU_CSL_SSR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)

SSR_S1 0b0..The secure supervisor read access is disabled for the first slave. 0b1..The secure supervisor read access is enabled for the first slave.

◆ CSU_CSL_SSR_S2

#define CSU_CSL_SSR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)

SSR_S2 0b0..The secure supervisor read access is disabled for the second slave. 0b1..The secure supervisor read access is enabled for the second slave.

◆ CSU_CSL_SSW_S1

#define CSU_CSL_SSW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)

SSW_S1 0b0..The secure supervisor write access is disabled for the first slave. 0b1..The secure supervisor write access is enabled for the first slave.

◆ CSU_CSL_SSW_S2

#define CSU_CSL_SSW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)

SSW_S2 0b0..The secure supervisor write access is disabled for the second slave. 0b1..The secure supervisor write access is enabled for the second slave.

◆ CSU_CSL_SUR_S1

#define CSU_CSL_SUR_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)

SUR_S1 0b0..The secure user read access is disabled for the first slave. 0b1..The secure user read access is enabled for the first slave.

◆ CSU_CSL_SUR_S2

#define CSU_CSL_SUR_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)

SUR_S2 0b0..The secure user read access is disabled for the second slave. 0b1..The secure user read access is enabled for the second slave.

◆ CSU_CSL_SUW_S1

#define CSU_CSL_SUW_S1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)

SUW_S1 0b0..The secure user write access is disabled for the first slave. 0b1..The secure user write access is enabled for the first slave.

◆ CSU_CSL_SUW_S2

#define CSU_CSL_SUW_S2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)

SUW_S2 0b0..The secure user write access is disabled for the second slave. 0b1..The secure user write access is enabled for the second slave.

◆ CSU_HP0_HP_CSI

#define CSU_HP0_HP_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)

HP_CSI 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_DCP

#define CSU_HP0_HP_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)

HP_DCP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_DMA

#define CSU_HP0_HP_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)

HP_DMA 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_ENET

#define CSU_HP0_HP_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)

HP_ENET 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_LCDIF

#define CSU_HP0_HP_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)

HP_LCDIF 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_PXP

#define CSU_HP0_HP_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)

HP_PXP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_TPSMP

#define CSU_HP0_HP_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)

HP_TPSMP 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_USB

#define CSU_HP0_HP_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)

HP_USB 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_USDHC1

#define CSU_HP0_HP_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)

HP_USDHC1 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_HP_USDHC2

#define CSU_HP0_HP_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)

HP_USDHC2 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.

◆ CSU_HP0_L_CSI

#define CSU_HP0_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_DCP

#define CSU_HP0_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.

◆ CSU_HP0_L_DMA

#define CSU_HP0_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_ENET

#define CSU_HP0_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_LCDIF

#define CSU_HP0_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_PXP

#define CSU_HP0_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_TPSMP

#define CSU_HP0_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_USB

#define CSU_HP0_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_USDHC1

#define CSU_HP0_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HP0_L_USDHC2

#define CSU_HP0_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_HPC_CSI

#define CSU_HPCONTROL0_HPC_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)

HPC_CSI 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_DCP

#define CSU_HPCONTROL0_HPC_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)

HPC_DCP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_DMA

#define CSU_HPCONTROL0_HPC_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)

HPC_DMA 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_ENET

#define CSU_HPCONTROL0_HPC_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)

HPC_ENET 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_LCDIF

#define CSU_HPCONTROL0_HPC_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)

HPC_LCDIF 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_PXP

#define CSU_HPCONTROL0_HPC_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)

HPC_PXP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_TPSMP

#define CSU_HPCONTROL0_HPC_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)

HPC_TPSMP 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_USB

#define CSU_HPCONTROL0_HPC_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)

HPC_USB 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_USDHC1

#define CSU_HPCONTROL0_HPC_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)

HPC_USDHC1 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_HPC_USDHC2

#define CSU_HPCONTROL0_HPC_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)

HPC_USDHC2 0b0..User mode for the corresponding master 0b1..Supervisor mode for the corresponding master

◆ CSU_HPCONTROL0_L_CSI

#define CSU_HPCONTROL0_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_DCP

#define CSU_HPCONTROL0_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_DMA

#define CSU_HPCONTROL0_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_ENET

#define CSU_HPCONTROL0_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_LCDIF

#define CSU_HPCONTROL0_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_PXP

#define CSU_HPCONTROL0_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_TPSMP

#define CSU_HPCONTROL0_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_USB

#define CSU_HPCONTROL0_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_USDHC1

#define CSU_HPCONTROL0_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_HPCONTROL0_L_USDHC2

#define CSU_HPCONTROL0_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_CSI

#define CSU_SA_L_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)

L_CSI 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_DCP

#define CSU_SA_L_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)

L_DCP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_DMA

#define CSU_SA_L_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)

L_DMA 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_ENET

#define CSU_SA_L_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)

L_ENET 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_LCDIF

#define CSU_SA_L_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)

L_LCDIF 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_PXP

#define CSU_SA_L_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)

L_PXP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_TPSMP

#define CSU_SA_L_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)

L_TPSMP 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_USB

#define CSU_SA_L_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)

L_USB 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_USDHC1

#define CSU_SA_L_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)

L_USDHC1 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_L_USDHC2

#define CSU_SA_L_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)

L_USDHC2 0b0..No lock-the adjacent (next lower) bit can be written by the software. 0b1..Lock-the adjacent (next lower) bit can't be written by the software.

◆ CSU_SA_NSA_CSI

#define CSU_SA_NSA_CSI (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)

NSA_CSI - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_DCP

#define CSU_SA_NSA_DCP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)

NSA_DCP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_DMA

#define CSU_SA_NSA_DMA (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)

NSA_DMA - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_ENET

#define CSU_SA_NSA_ENET (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)

NSA_ENET - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_LCDIF

#define CSU_SA_NSA_LCDIF (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)

NSA_LCDIF - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_PXP

#define CSU_SA_NSA_PXP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)

NSA_PXP - Non-Secure Access Policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_TPSMP

#define CSU_SA_NSA_TPSMP (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)

NSA_TPSMP - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_USB

#define CSU_SA_NSA_USB (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)

NSA_USB - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_USDHC1

#define CSU_SA_NSA_USDHC1 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)

NSA_USDHC1 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

◆ CSU_SA_NSA_USDHC2

#define CSU_SA_NSA_USDHC2 (   x)    (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)

NSA_USDHC2 - Non-secure access policy indicator bit 0b0..Secure access for the corresponding type-1 master 0b1..Non-secure access for the corresponding type-1 master

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