RTEMS 6.1-rc5
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AIPSTZ Register Masks
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » AIPSTZ Peripheral Access Layer

MPR - Master Priviledge Registers

#define AIPSTZ_MPR_MPROT3_MASK   (0xF0000U)
 
#define AIPSTZ_MPR_MPROT3_SHIFT   (16U)
 
#define AIPSTZ_MPR_MPROT3(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
 
#define AIPSTZ_MPR_MPROT2_MASK   (0xF00000U)
 
#define AIPSTZ_MPR_MPROT2_SHIFT   (20U)
 
#define AIPSTZ_MPR_MPROT2(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
 
#define AIPSTZ_MPR_MPROT1_MASK   (0xF000000U)
 
#define AIPSTZ_MPR_MPROT1_SHIFT   (24U)
 
#define AIPSTZ_MPR_MPROT1(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
 
#define AIPSTZ_MPR_MPROT0_MASK   (0xF0000000U)
 
#define AIPSTZ_MPR_MPROT0_SHIFT   (28U)
 
#define AIPSTZ_MPR_MPROT0(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
 

OPACR - Off-Platform Peripheral Access Control Registers

#define AIPSTZ_OPACR_OPAC7_MASK   (0xFU)
 
#define AIPSTZ_OPACR_OPAC7_SHIFT   (0U)
 
#define AIPSTZ_OPACR_OPAC7(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
 
#define AIPSTZ_OPACR_OPAC6_MASK   (0xF0U)
 
#define AIPSTZ_OPACR_OPAC6_SHIFT   (4U)
 
#define AIPSTZ_OPACR_OPAC6(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
 
#define AIPSTZ_OPACR_OPAC5_MASK   (0xF00U)
 
#define AIPSTZ_OPACR_OPAC5_SHIFT   (8U)
 
#define AIPSTZ_OPACR_OPAC5(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
 
#define AIPSTZ_OPACR_OPAC4_MASK   (0xF000U)
 
#define AIPSTZ_OPACR_OPAC4_SHIFT   (12U)
 
#define AIPSTZ_OPACR_OPAC4(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
 
#define AIPSTZ_OPACR_OPAC3_MASK   (0xF0000U)
 
#define AIPSTZ_OPACR_OPAC3_SHIFT   (16U)
 
#define AIPSTZ_OPACR_OPAC3(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
 
#define AIPSTZ_OPACR_OPAC2_MASK   (0xF00000U)
 
#define AIPSTZ_OPACR_OPAC2_SHIFT   (20U)
 
#define AIPSTZ_OPACR_OPAC2(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
 
#define AIPSTZ_OPACR_OPAC1_MASK   (0xF000000U)
 
#define AIPSTZ_OPACR_OPAC1_SHIFT   (24U)
 
#define AIPSTZ_OPACR_OPAC1(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
 
#define AIPSTZ_OPACR_OPAC0_MASK   (0xF0000000U)
 
#define AIPSTZ_OPACR_OPAC0_SHIFT   (28U)
 
#define AIPSTZ_OPACR_OPAC0(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
 

OPACR1 - Off-Platform Peripheral Access Control Registers

#define AIPSTZ_OPACR1_OPAC15_MASK   (0xFU)
 
#define AIPSTZ_OPACR1_OPAC15_SHIFT   (0U)
 
#define AIPSTZ_OPACR1_OPAC15(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
 
#define AIPSTZ_OPACR1_OPAC14_MASK   (0xF0U)
 
#define AIPSTZ_OPACR1_OPAC14_SHIFT   (4U)
 
#define AIPSTZ_OPACR1_OPAC14(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
 
#define AIPSTZ_OPACR1_OPAC13_MASK   (0xF00U)
 
#define AIPSTZ_OPACR1_OPAC13_SHIFT   (8U)
 
#define AIPSTZ_OPACR1_OPAC13(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
 
#define AIPSTZ_OPACR1_OPAC12_MASK   (0xF000U)
 
#define AIPSTZ_OPACR1_OPAC12_SHIFT   (12U)
 
#define AIPSTZ_OPACR1_OPAC12(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
 
#define AIPSTZ_OPACR1_OPAC11_MASK   (0xF0000U)
 
#define AIPSTZ_OPACR1_OPAC11_SHIFT   (16U)
 
#define AIPSTZ_OPACR1_OPAC11(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
 
#define AIPSTZ_OPACR1_OPAC10_MASK   (0xF00000U)
 
#define AIPSTZ_OPACR1_OPAC10_SHIFT   (20U)
 
#define AIPSTZ_OPACR1_OPAC10(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
 
#define AIPSTZ_OPACR1_OPAC9_MASK   (0xF000000U)
 
#define AIPSTZ_OPACR1_OPAC9_SHIFT   (24U)
 
#define AIPSTZ_OPACR1_OPAC9(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
 
#define AIPSTZ_OPACR1_OPAC8_MASK   (0xF0000000U)
 
#define AIPSTZ_OPACR1_OPAC8_SHIFT   (28U)
 
#define AIPSTZ_OPACR1_OPAC8(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
 

OPACR2 - Off-Platform Peripheral Access Control Registers

#define AIPSTZ_OPACR2_OPAC23_MASK   (0xFU)
 
#define AIPSTZ_OPACR2_OPAC23_SHIFT   (0U)
 
#define AIPSTZ_OPACR2_OPAC23(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
 
#define AIPSTZ_OPACR2_OPAC22_MASK   (0xF0U)
 
#define AIPSTZ_OPACR2_OPAC22_SHIFT   (4U)
 
#define AIPSTZ_OPACR2_OPAC22(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
 
#define AIPSTZ_OPACR2_OPAC21_MASK   (0xF00U)
 
#define AIPSTZ_OPACR2_OPAC21_SHIFT   (8U)
 
#define AIPSTZ_OPACR2_OPAC21(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
 
#define AIPSTZ_OPACR2_OPAC20_MASK   (0xF000U)
 
#define AIPSTZ_OPACR2_OPAC20_SHIFT   (12U)
 
#define AIPSTZ_OPACR2_OPAC20(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
 
#define AIPSTZ_OPACR2_OPAC19_MASK   (0xF0000U)
 
#define AIPSTZ_OPACR2_OPAC19_SHIFT   (16U)
 
#define AIPSTZ_OPACR2_OPAC19(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
 
#define AIPSTZ_OPACR2_OPAC18_MASK   (0xF00000U)
 
#define AIPSTZ_OPACR2_OPAC18_SHIFT   (20U)
 
#define AIPSTZ_OPACR2_OPAC18(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
 
#define AIPSTZ_OPACR2_OPAC17_MASK   (0xF000000U)
 
#define AIPSTZ_OPACR2_OPAC17_SHIFT   (24U)
 
#define AIPSTZ_OPACR2_OPAC17(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
 
#define AIPSTZ_OPACR2_OPAC16_MASK   (0xF0000000U)
 
#define AIPSTZ_OPACR2_OPAC16_SHIFT   (28U)
 
#define AIPSTZ_OPACR2_OPAC16(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
 

OPACR3 - Off-Platform Peripheral Access Control Registers

#define AIPSTZ_OPACR3_OPAC31_MASK   (0xFU)
 
#define AIPSTZ_OPACR3_OPAC31_SHIFT   (0U)
 
#define AIPSTZ_OPACR3_OPAC31(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
 
#define AIPSTZ_OPACR3_OPAC30_MASK   (0xF0U)
 
#define AIPSTZ_OPACR3_OPAC30_SHIFT   (4U)
 
#define AIPSTZ_OPACR3_OPAC30(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
 
#define AIPSTZ_OPACR3_OPAC29_MASK   (0xF00U)
 
#define AIPSTZ_OPACR3_OPAC29_SHIFT   (8U)
 
#define AIPSTZ_OPACR3_OPAC29(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
 
#define AIPSTZ_OPACR3_OPAC28_MASK   (0xF000U)
 
#define AIPSTZ_OPACR3_OPAC28_SHIFT   (12U)
 
#define AIPSTZ_OPACR3_OPAC28(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
 
#define AIPSTZ_OPACR3_OPAC27_MASK   (0xF0000U)
 
#define AIPSTZ_OPACR3_OPAC27_SHIFT   (16U)
 
#define AIPSTZ_OPACR3_OPAC27(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
 
#define AIPSTZ_OPACR3_OPAC26_MASK   (0xF00000U)
 
#define AIPSTZ_OPACR3_OPAC26_SHIFT   (20U)
 
#define AIPSTZ_OPACR3_OPAC26(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
 
#define AIPSTZ_OPACR3_OPAC25_MASK   (0xF000000U)
 
#define AIPSTZ_OPACR3_OPAC25_SHIFT   (24U)
 
#define AIPSTZ_OPACR3_OPAC25(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
 
#define AIPSTZ_OPACR3_OPAC24_MASK   (0xF0000000U)
 
#define AIPSTZ_OPACR3_OPAC24_SHIFT   (28U)
 
#define AIPSTZ_OPACR3_OPAC24(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
 

OPACR4 - Off-Platform Peripheral Access Control Registers

#define AIPSTZ_OPACR4_OPAC33_MASK   (0xF000000U)
 
#define AIPSTZ_OPACR4_OPAC33_SHIFT   (24U)
 
#define AIPSTZ_OPACR4_OPAC33(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
 
#define AIPSTZ_OPACR4_OPAC32_MASK   (0xF0000000U)
 
#define AIPSTZ_OPACR4_OPAC32_SHIFT   (28U)
 
#define AIPSTZ_OPACR4_OPAC32(x)   (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
 

Detailed Description

Macro Definition Documentation

◆ AIPSTZ_MPR_MPROT0

#define AIPSTZ_MPR_MPROT0 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)

MPROT0 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

◆ AIPSTZ_MPR_MPROT1

#define AIPSTZ_MPR_MPROT1 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)

MPROT1 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

◆ AIPSTZ_MPR_MPROT2

#define AIPSTZ_MPR_MPROT2 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)

MPROT2 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

◆ AIPSTZ_MPR_MPROT3

#define AIPSTZ_MPR_MPROT3 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)

MPROT3 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses. 0bxx1x..This master is trusted for write accesses. 0bx0xx..This master is not trusted for read accesses. 0bx1xx..This master is trusted for read accesses. 0b1xxx..Write accesses from this master are allowed to be buffered

◆ AIPSTZ_OPACR1_OPAC10

#define AIPSTZ_OPACR1_OPAC10 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)

OPAC10 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC11

#define AIPSTZ_OPACR1_OPAC11 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)

OPAC11 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC12

#define AIPSTZ_OPACR1_OPAC12 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)

OPAC12 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC13

#define AIPSTZ_OPACR1_OPAC13 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)

OPAC13 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC14

#define AIPSTZ_OPACR1_OPAC14 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)

OPAC14 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC15

#define AIPSTZ_OPACR1_OPAC15 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)

OPAC15 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC8

#define AIPSTZ_OPACR1_OPAC8 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)

OPAC8 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR1_OPAC9

#define AIPSTZ_OPACR1_OPAC9 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)

OPAC9 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC16

#define AIPSTZ_OPACR2_OPAC16 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)

OPAC16 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC17

#define AIPSTZ_OPACR2_OPAC17 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)

OPAC17 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC18

#define AIPSTZ_OPACR2_OPAC18 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)

OPAC18 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC19

#define AIPSTZ_OPACR2_OPAC19 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)

OPAC19 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC20

#define AIPSTZ_OPACR2_OPAC20 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)

OPAC20 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC21

#define AIPSTZ_OPACR2_OPAC21 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)

OPAC21 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC22

#define AIPSTZ_OPACR2_OPAC22 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)

OPAC22 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR2_OPAC23

#define AIPSTZ_OPACR2_OPAC23 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)

OPAC23 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC24

#define AIPSTZ_OPACR3_OPAC24 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)

OPAC24 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC25

#define AIPSTZ_OPACR3_OPAC25 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)

OPAC25 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC26

#define AIPSTZ_OPACR3_OPAC26 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)

OPAC26 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC27

#define AIPSTZ_OPACR3_OPAC27 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)

OPAC27 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC28

#define AIPSTZ_OPACR3_OPAC28 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)

OPAC28 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC29

#define AIPSTZ_OPACR3_OPAC29 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)

OPAC29 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC30

#define AIPSTZ_OPACR3_OPAC30 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)

OPAC30 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR3_OPAC31

#define AIPSTZ_OPACR3_OPAC31 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)

OPAC31 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR4_OPAC32

#define AIPSTZ_OPACR4_OPAC32 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)

OPAC32 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR4_OPAC33

#define AIPSTZ_OPACR4_OPAC33 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)

OPAC33 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC0

#define AIPSTZ_OPACR_OPAC0 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)

OPAC0 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC1

#define AIPSTZ_OPACR_OPAC1 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)

OPAC1 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC2

#define AIPSTZ_OPACR_OPAC2 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)

OPAC2 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC3

#define AIPSTZ_OPACR_OPAC3 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)

OPAC3 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC4

#define AIPSTZ_OPACR_OPAC4 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)

OPAC4 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC5

#define AIPSTZ_OPACR_OPAC5 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)

OPAC5 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC6

#define AIPSTZ_OPACR_OPAC6 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)

OPAC6 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

◆ AIPSTZ_OPACR_OPAC7

#define AIPSTZ_OPACR_OPAC7 (   x)    (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)

OPAC7 0bxxx0..Accesses from an untrusted master are allowed. 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bxx0x..This peripheral allows write accesses. 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0bx0xx..This peripheral does not require supervisor privilege level for accesses. 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.

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