ADC Register Masks

Macros
#define	ADC_HC_COUNT   (8U)
#define	ADC_R_COUNT   (8U)
#define	ADC_TCTRL_COUNT   (8U)
#define	ADC_CMDL_COUNT   (15U)
#define	ADC_CMDH_COUNT   (15U)
#define	ADC_CV_COUNT   (4U)
#define	ADC_TCTRL_COUNT   (8U)
#define	ADC_CMDL_COUNT   (15U)
#define	ADC_CMDH_COUNT   (15U)
#define	ADC_CV_COUNT   (4U)

HC - Control register for hardware triggers
#define	ADC_HC_ADCH_MASK   (0x1FU)
#define	ADC_HC_ADCH_SHIFT   (0U)
#define	ADC_HC_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
#define	ADC_HC_AIEN_MASK   (0x80U)
#define	ADC_HC_AIEN_SHIFT   (7U)
#define	ADC_HC_AIEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)

HS - Status register for HW triggers
#define	ADC_HS_COCO0_MASK   (0x1U)
#define	ADC_HS_COCO0_SHIFT   (0U)
#define	ADC_HS_COCO0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
#define	ADC_HS_COCO1_MASK   (0x2U)
#define	ADC_HS_COCO1_SHIFT   (1U)
#define	ADC_HS_COCO1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)
#define	ADC_HS_COCO2_MASK   (0x4U)
#define	ADC_HS_COCO2_SHIFT   (2U)
#define	ADC_HS_COCO2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK)
#define	ADC_HS_COCO3_MASK   (0x8U)
#define	ADC_HS_COCO3_SHIFT   (3U)
#define	ADC_HS_COCO3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK)
#define	ADC_HS_COCO4_MASK   (0x10U)
#define	ADC_HS_COCO4_SHIFT   (4U)
#define	ADC_HS_COCO4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK)
#define	ADC_HS_COCO5_MASK   (0x20U)
#define	ADC_HS_COCO5_SHIFT   (5U)
#define	ADC_HS_COCO5(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK)
#define	ADC_HS_COCO6_MASK   (0x40U)
#define	ADC_HS_COCO6_SHIFT   (6U)
#define	ADC_HS_COCO6(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK)
#define	ADC_HS_COCO7_MASK   (0x80U)
#define	ADC_HS_COCO7_SHIFT   (7U)
#define	ADC_HS_COCO7(x)   (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK)

R - Data result register for HW triggers
#define	ADC_R_CDATA_MASK   (0xFFFU)
#define	ADC_R_CDATA_SHIFT   (0U)
#define	ADC_R_CDATA(x)   (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)

CFG - Configuration register
#define	ADC_CFG_ADICLK_MASK   (0x3U)
#define	ADC_CFG_ADICLK_SHIFT   (0U)
#define	ADC_CFG_ADICLK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
#define	ADC_CFG_MODE_MASK   (0xCU)
#define	ADC_CFG_MODE_SHIFT   (2U)
#define	ADC_CFG_MODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
#define	ADC_CFG_ADLSMP_MASK   (0x10U)
#define	ADC_CFG_ADLSMP_SHIFT   (4U)
#define	ADC_CFG_ADLSMP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
#define	ADC_CFG_ADIV_MASK   (0x60U)
#define	ADC_CFG_ADIV_SHIFT   (5U)
#define	ADC_CFG_ADIV(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
#define	ADC_CFG_ADLPC_MASK   (0x80U)
#define	ADC_CFG_ADLPC_SHIFT   (7U)
#define	ADC_CFG_ADLPC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
#define	ADC_CFG_ADSTS_MASK   (0x300U)
#define	ADC_CFG_ADSTS_SHIFT   (8U)
#define	ADC_CFG_ADSTS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
#define	ADC_CFG_ADHSC_MASK   (0x400U)
#define	ADC_CFG_ADHSC_SHIFT   (10U)
#define	ADC_CFG_ADHSC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
#define	ADC_CFG_REFSEL_MASK   (0x1800U)
#define	ADC_CFG_REFSEL_SHIFT   (11U)
#define	ADC_CFG_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define	ADC_CFG_ADTRG_MASK   (0x2000U)
#define	ADC_CFG_ADTRG_SHIFT   (13U)
#define	ADC_CFG_ADTRG(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
#define	ADC_CFG_AVGS_MASK   (0xC000U)
#define	ADC_CFG_AVGS_SHIFT   (14U)
#define	ADC_CFG_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
#define	ADC_CFG_OVWREN_MASK   (0x10000U)
#define	ADC_CFG_OVWREN_SHIFT   (16U)
#define	ADC_CFG_OVWREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)

GC - General control register
#define	ADC_GC_ADACKEN_MASK   (0x1U)
#define	ADC_GC_ADACKEN_SHIFT   (0U)
#define	ADC_GC_ADACKEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
#define	ADC_GC_DMAEN_MASK   (0x2U)
#define	ADC_GC_DMAEN_SHIFT   (1U)
#define	ADC_GC_DMAEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
#define	ADC_GC_ACREN_MASK   (0x4U)
#define	ADC_GC_ACREN_SHIFT   (2U)
#define	ADC_GC_ACREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
#define	ADC_GC_ACFGT_MASK   (0x8U)
#define	ADC_GC_ACFGT_SHIFT   (3U)
#define	ADC_GC_ACFGT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
#define	ADC_GC_ACFE_MASK   (0x10U)
#define	ADC_GC_ACFE_SHIFT   (4U)
#define	ADC_GC_ACFE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
#define	ADC_GC_AVGE_MASK   (0x20U)
#define	ADC_GC_AVGE_SHIFT   (5U)
#define	ADC_GC_AVGE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
#define	ADC_GC_ADCO_MASK   (0x40U)
#define	ADC_GC_ADCO_SHIFT   (6U)
#define	ADC_GC_ADCO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
#define	ADC_GC_CAL_MASK   (0x80U)
#define	ADC_GC_CAL_SHIFT   (7U)
#define	ADC_GC_CAL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)

GS - General status register
#define	ADC_GS_ADACT_MASK   (0x1U)
#define	ADC_GS_ADACT_SHIFT   (0U)
#define	ADC_GS_ADACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
#define	ADC_GS_CALF_MASK   (0x2U)
#define	ADC_GS_CALF_SHIFT   (1U)
#define	ADC_GS_CALF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
#define	ADC_GS_AWKST_MASK   (0x4U)
#define	ADC_GS_AWKST_SHIFT   (2U)
#define	ADC_GS_AWKST(x)   (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)

CV - Compare value register
#define	ADC_CV_CV1_MASK   (0xFFFU)
#define	ADC_CV_CV1_SHIFT   (0U)
#define	ADC_CV_CV1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
#define	ADC_CV_CV2_MASK   (0xFFF0000U)
#define	ADC_CV_CV2_SHIFT   (16U)
#define	ADC_CV_CV2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)

OFS - Offset correction value register
#define	ADC_OFS_OFS_MASK   (0xFFFU)
#define	ADC_OFS_OFS_SHIFT   (0U)
#define	ADC_OFS_OFS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
#define	ADC_OFS_SIGN_MASK   (0x1000U)
#define	ADC_OFS_SIGN_SHIFT   (12U)
#define	ADC_OFS_SIGN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)

CAL - Calibration value register
#define	ADC_CAL_CAL_CODE_MASK   (0xFU)
#define	ADC_CAL_CAL_CODE_SHIFT   (0U)
#define	ADC_CAL_CAL_CODE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)

VERID - Version ID Register
#define	ADC_VERID_RES_MASK   (0x1U)
#define	ADC_VERID_RES_SHIFT   (0U)
#define	ADC_VERID_RES(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
#define	ADC_VERID_DIFFEN_MASK   (0x2U)
#define	ADC_VERID_DIFFEN_SHIFT   (1U)
#define	ADC_VERID_DIFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
#define	ADC_VERID_MVI_MASK   (0x8U)
#define	ADC_VERID_MVI_SHIFT   (3U)
#define	ADC_VERID_MVI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
#define	ADC_VERID_CSW_MASK   (0x70U)
#define	ADC_VERID_CSW_SHIFT   (4U)
#define	ADC_VERID_CSW(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
#define	ADC_VERID_VR1RNGI_MASK   (0x100U)
#define	ADC_VERID_VR1RNGI_SHIFT   (8U)
#define	ADC_VERID_VR1RNGI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
#define	ADC_VERID_IADCKI_MASK   (0x200U)
#define	ADC_VERID_IADCKI_SHIFT   (9U)
#define	ADC_VERID_IADCKI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
#define	ADC_VERID_CALOFSI_MASK   (0x400U)
#define	ADC_VERID_CALOFSI_SHIFT   (10U)
#define	ADC_VERID_CALOFSI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
#define	ADC_VERID_MINOR_MASK   (0xFF0000U)
#define	ADC_VERID_MINOR_SHIFT   (16U)
#define	ADC_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
#define	ADC_VERID_MAJOR_MASK   (0xFF000000U)
#define	ADC_VERID_MAJOR_SHIFT   (24U)
#define	ADC_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
#define	CMP_VERID_FEATURE_MASK   (0xFFFFU)
#define	CMP_VERID_FEATURE_SHIFT   (0U)
#define	CMP_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
#define	CMP_VERID_MINOR_MASK   (0xFF0000U)
#define	CMP_VERID_MINOR_SHIFT   (16U)
#define	CMP_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
#define	CMP_VERID_MAJOR_MASK   (0xFF000000U)
#define	CMP_VERID_MAJOR_SHIFT   (24U)
#define	CMP_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
#define	LPUART_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPUART_VERID_FEATURE_SHIFT   (0U)
#define	LPUART_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define	LPUART_VERID_MINOR_MASK   (0xFF0000U)
#define	LPUART_VERID_MINOR_SHIFT   (16U)
#define	LPUART_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define	LPUART_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPUART_VERID_MAJOR_SHIFT   (24U)
#define	LPUART_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	ADC_PARAM_TRIG_NUM_MASK   (0xFFU)
#define	ADC_PARAM_TRIG_NUM_SHIFT   (0U)
#define	ADC_PARAM_TRIG_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
#define	ADC_PARAM_FIFOSIZE_MASK   (0xFF00U)
#define	ADC_PARAM_FIFOSIZE_SHIFT   (8U)
#define	ADC_PARAM_FIFOSIZE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
#define	ADC_PARAM_CV_NUM_MASK   (0xFF0000U)
#define	ADC_PARAM_CV_NUM_SHIFT   (16U)
#define	ADC_PARAM_CV_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
#define	ADC_PARAM_CMD_NUM_MASK   (0xFF000000U)
#define	ADC_PARAM_CMD_NUM_SHIFT   (24U)
#define	ADC_PARAM_CMD_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
#define	CMP_PARAM_PARAM_MASK   (0xFFFFFFFFU)
#define	CMP_PARAM_PARAM_SHIFT   (0U)
#define	CMP_PARAM_PARAM(x)   (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
#define	DAC_PARAM_FIFOSZ_MASK   (0x7U)
#define	DAC_PARAM_FIFOSZ_SHIFT   (0U)
#define	DAC_PARAM_FIFOSZ(x)   (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_MASK   (0xFFU)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT   (0U)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_MASK   (0xFF00U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT   (8U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
#define	LPUART_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPUART_PARAM_TXFIFO_SHIFT   (0U)
#define	LPUART_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define	LPUART_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPUART_PARAM_RXFIFO_SHIFT   (8U)
#define	LPUART_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

CTRL - LPADC Control Register
#define	ADC_CTRL_ADCEN_MASK   (0x1U)
#define	ADC_CTRL_ADCEN_SHIFT   (0U)
#define	ADC_CTRL_ADCEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
#define	ADC_CTRL_RST_MASK   (0x2U)
#define	ADC_CTRL_RST_SHIFT   (1U)
#define	ADC_CTRL_RST(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
#define	ADC_CTRL_DOZEN_MASK   (0x4U)
#define	ADC_CTRL_DOZEN_SHIFT   (2U)
#define	ADC_CTRL_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
#define	ADC_CTRL_TRIG_SRC_MASK   (0x18U)
#define	ADC_CTRL_TRIG_SRC_SHIFT   (3U)
#define	ADC_CTRL_TRIG_SRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
#define	ADC_CTRL_RSTFIFO_MASK   (0x100U)
#define	ADC_CTRL_RSTFIFO_SHIFT   (8U)
#define	ADC_CTRL_RSTFIFO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)

STAT - LPADC Status Register
#define	ADC_STAT_RDY_MASK   (0x1U)
#define	ADC_STAT_RDY_SHIFT   (0U)
#define	ADC_STAT_RDY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
#define	ADC_STAT_FOF_MASK   (0x2U)
#define	ADC_STAT_FOF_SHIFT   (1U)
#define	ADC_STAT_FOF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
#define	ADC_STAT_ADC_ACTIVE_MASK   (0x100U)
#define	ADC_STAT_ADC_ACTIVE_SHIFT   (8U)
#define	ADC_STAT_ADC_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
#define	ADC_STAT_TRGACT_MASK   (0x70000U)
#define	ADC_STAT_TRGACT_SHIFT   (16U)
#define	ADC_STAT_TRGACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
#define	ADC_STAT_CMDACT_MASK   (0xF000000U)
#define	ADC_STAT_CMDACT_SHIFT   (24U)
#define	ADC_STAT_CMDACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)

IE - Interrupt Enable Register
#define	ADC_IE_FWMIE_MASK   (0x1U)
#define	ADC_IE_FWMIE_SHIFT   (0U)
#define	ADC_IE_FWMIE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
#define	ADC_IE_FOFIE_MASK   (0x2U)
#define	ADC_IE_FOFIE_SHIFT   (1U)
#define	ADC_IE_FOFIE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)

DE - DMA Enable Register
#define	ADC_DE_FWMDE_MASK   (0x1U)
#define	ADC_DE_FWMDE_SHIFT   (0U)
#define	ADC_DE_FWMDE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)

CFG - LPADC Configuration Register
#define	ADC_CFG_TPRICTRL_MASK   (0x1U)
#define	ADC_CFG_TPRICTRL_SHIFT   (0U)
#define	ADC_CFG_TPRICTRL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
#define	ADC_CFG_PWRSEL_MASK   (0x30U)
#define	ADC_CFG_PWRSEL_SHIFT   (4U)
#define	ADC_CFG_PWRSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
#define	ADC_CFG_REFSEL_MASK   (0xC0U)
#define	ADC_CFG_REFSEL_SHIFT   (6U)
#define	ADC_CFG_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define	ADC_CFG_PUDLY_MASK   (0xFF0000U)
#define	ADC_CFG_PUDLY_SHIFT   (16U)
#define	ADC_CFG_PUDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
#define	ADC_CFG_PWREN_MASK   (0x10000000U)
#define	ADC_CFG_PWREN_SHIFT   (28U)
#define	ADC_CFG_PWREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)

PAUSE - LPADC Pause Register
#define	ADC_PAUSE_PAUSEDLY_MASK   (0x1FFU)
#define	ADC_PAUSE_PAUSEDLY_SHIFT   (0U)
#define	ADC_PAUSE_PAUSEDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
#define	ADC_PAUSE_PAUSEEN_MASK   (0x80000000U)
#define	ADC_PAUSE_PAUSEEN_SHIFT   (31U)
#define	ADC_PAUSE_PAUSEEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)

FCTRL - LPADC FIFO Control Register
#define	ADC_FCTRL_FCOUNT_MASK   (0x1FU)
#define	ADC_FCTRL_FCOUNT_SHIFT   (0U)
#define	ADC_FCTRL_FCOUNT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
#define	ADC_FCTRL_FWMARK_MASK   (0xF0000U)
#define	ADC_FCTRL_FWMARK_SHIFT   (16U)
#define	ADC_FCTRL_FWMARK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)

SWTRIG - Software Trigger Register
#define	ADC_SWTRIG_SWT0_MASK   (0x1U)
#define	ADC_SWTRIG_SWT0_SHIFT   (0U)
#define	ADC_SWTRIG_SWT0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
#define	ADC_SWTRIG_SWT1_MASK   (0x2U)
#define	ADC_SWTRIG_SWT1_SHIFT   (1U)
#define	ADC_SWTRIG_SWT1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
#define	ADC_SWTRIG_SWT2_MASK   (0x4U)
#define	ADC_SWTRIG_SWT2_SHIFT   (2U)
#define	ADC_SWTRIG_SWT2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
#define	ADC_SWTRIG_SWT3_MASK   (0x8U)
#define	ADC_SWTRIG_SWT3_SHIFT   (3U)
#define	ADC_SWTRIG_SWT3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
#define	ADC_SWTRIG_SWT4_MASK   (0x10U)
#define	ADC_SWTRIG_SWT4_SHIFT   (4U)
#define	ADC_SWTRIG_SWT4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
#define	ADC_SWTRIG_SWT5_MASK   (0x20U)
#define	ADC_SWTRIG_SWT5_SHIFT   (5U)
#define	ADC_SWTRIG_SWT5(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
#define	ADC_SWTRIG_SWT6_MASK   (0x40U)
#define	ADC_SWTRIG_SWT6_SHIFT   (6U)
#define	ADC_SWTRIG_SWT6(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
#define	ADC_SWTRIG_SWT7_MASK   (0x80U)
#define	ADC_SWTRIG_SWT7_SHIFT   (7U)
#define	ADC_SWTRIG_SWT7(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)

TCTRL - Trigger Control Register
#define	ADC_TCTRL_HTEN_MASK   (0x1U)
#define	ADC_TCTRL_HTEN_SHIFT   (0U)
#define	ADC_TCTRL_HTEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
#define	ADC_TCTRL_CMD_SEL_MASK   (0x2U)
#define	ADC_TCTRL_CMD_SEL_SHIFT   (1U)
#define	ADC_TCTRL_CMD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
#define	ADC_TCTRL_TPRI_MASK   (0x700U)
#define	ADC_TCTRL_TPRI_SHIFT   (8U)
#define	ADC_TCTRL_TPRI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
#define	ADC_TCTRL_TDLY_MASK   (0xF0000U)
#define	ADC_TCTRL_TDLY_SHIFT   (16U)
#define	ADC_TCTRL_TDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
#define	ADC_TCTRL_TCMD_MASK   (0xF000000U)
#define	ADC_TCTRL_TCMD_SHIFT   (24U)
#define	ADC_TCTRL_TCMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)

CMDL - LPADC Command Low Buffer Register
#define	ADC_CMDL_ADCH_MASK   (0x1FU)
#define	ADC_CMDL_ADCH_SHIFT   (0U)
#define	ADC_CMDL_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
#define	ADC_CMDL_ABSEL_MASK   (0x20U)
#define	ADC_CMDL_ABSEL_SHIFT   (5U)
#define	ADC_CMDL_ABSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
#define	ADC_CMDL_DIFF_MASK   (0x40U)
#define	ADC_CMDL_DIFF_SHIFT   (6U)
#define	ADC_CMDL_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
#define	ADC_CMDL_CSCALE_MASK   (0x2000U)
#define	ADC_CMDL_CSCALE_SHIFT   (13U)
#define	ADC_CMDL_CSCALE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)

CMDH - LPADC Command High Buffer Register
#define	ADC_CMDH_CMPEN_MASK   (0x3U)
#define	ADC_CMDH_CMPEN_SHIFT   (0U)
#define	ADC_CMDH_CMPEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
#define	ADC_CMDH_LWI_MASK   (0x80U)
#define	ADC_CMDH_LWI_SHIFT   (7U)
#define	ADC_CMDH_LWI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
#define	ADC_CMDH_STS_MASK   (0x700U)
#define	ADC_CMDH_STS_SHIFT   (8U)
#define	ADC_CMDH_STS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
#define	ADC_CMDH_AVGS_MASK   (0x7000U)
#define	ADC_CMDH_AVGS_SHIFT   (12U)
#define	ADC_CMDH_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
#define	ADC_CMDH_LOOP_MASK   (0xF0000U)
#define	ADC_CMDH_LOOP_SHIFT   (16U)
#define	ADC_CMDH_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
#define	ADC_CMDH_NEXT_MASK   (0xF000000U)
#define	ADC_CMDH_NEXT_SHIFT   (24U)
#define	ADC_CMDH_NEXT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)

CV - Compare Value Register
#define	ADC_CV_CVL_MASK   (0xFFFFU)
#define	ADC_CV_CVL_SHIFT   (0U)
#define	ADC_CV_CVL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
#define	ADC_CV_CVH_MASK   (0xFFFF0000U)
#define	ADC_CV_CVH_SHIFT   (16U)
#define	ADC_CV_CVH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)

RESFIFO - LPADC Data Result FIFO Register
#define	ADC_RESFIFO_D_MASK   (0xFFFFU)
#define	ADC_RESFIFO_D_SHIFT   (0U)
#define	ADC_RESFIFO_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
#define	ADC_RESFIFO_TSRC_MASK   (0x70000U)
#define	ADC_RESFIFO_TSRC_SHIFT   (16U)
#define	ADC_RESFIFO_TSRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
#define	ADC_RESFIFO_LOOPCNT_MASK   (0xF00000U)
#define	ADC_RESFIFO_LOOPCNT_SHIFT   (20U)
#define	ADC_RESFIFO_LOOPCNT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
#define	ADC_RESFIFO_CMDSRC_MASK   (0xF000000U)
#define	ADC_RESFIFO_CMDSRC_SHIFT   (24U)
#define	ADC_RESFIFO_CMDSRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
#define	ADC_RESFIFO_VALID_MASK   (0x80000000U)
#define	ADC_RESFIFO_VALID_SHIFT   (31U)
#define	ADC_RESFIFO_VALID(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)

VERID - Version ID Register
#define	ADC_VERID_RES_MASK   (0x1U)
#define	ADC_VERID_RES_SHIFT   (0U)
#define	ADC_VERID_RES(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
#define	ADC_VERID_DIFFEN_MASK   (0x2U)
#define	ADC_VERID_DIFFEN_SHIFT   (1U)
#define	ADC_VERID_DIFFEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
#define	ADC_VERID_MVI_MASK   (0x8U)
#define	ADC_VERID_MVI_SHIFT   (3U)
#define	ADC_VERID_MVI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
#define	ADC_VERID_CSW_MASK   (0x70U)
#define	ADC_VERID_CSW_SHIFT   (4U)
#define	ADC_VERID_CSW(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
#define	ADC_VERID_VR1RNGI_MASK   (0x100U)
#define	ADC_VERID_VR1RNGI_SHIFT   (8U)
#define	ADC_VERID_VR1RNGI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
#define	ADC_VERID_IADCKI_MASK   (0x200U)
#define	ADC_VERID_IADCKI_SHIFT   (9U)
#define	ADC_VERID_IADCKI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
#define	ADC_VERID_CALOFSI_MASK   (0x400U)
#define	ADC_VERID_CALOFSI_SHIFT   (10U)
#define	ADC_VERID_CALOFSI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
#define	ADC_VERID_MINOR_MASK   (0xFF0000U)
#define	ADC_VERID_MINOR_SHIFT   (16U)
#define	ADC_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
#define	ADC_VERID_MAJOR_MASK   (0xFF000000U)
#define	ADC_VERID_MAJOR_SHIFT   (24U)
#define	ADC_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
#define	CMP_VERID_FEATURE_MASK   (0xFFFFU)
#define	CMP_VERID_FEATURE_SHIFT   (0U)
#define	CMP_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
#define	CMP_VERID_MINOR_MASK   (0xFF0000U)
#define	CMP_VERID_MINOR_SHIFT   (16U)
#define	CMP_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
#define	CMP_VERID_MAJOR_MASK   (0xFF000000U)
#define	CMP_VERID_MAJOR_SHIFT   (24U)
#define	CMP_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
#define	FLEXIO_VERID_FEATURE_MASK   (0xFFFFU)
#define	FLEXIO_VERID_FEATURE_SHIFT   (0U)
#define	FLEXIO_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define	FLEXIO_VERID_MINOR_MASK   (0xFF0000U)
#define	FLEXIO_VERID_MINOR_SHIFT   (16U)
#define	FLEXIO_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define	FLEXIO_VERID_MAJOR_MASK   (0xFF000000U)
#define	FLEXIO_VERID_MAJOR_SHIFT   (24U)
#define	FLEXIO_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
#define	LPUART_VERID_FEATURE_MASK   (0xFFFFU)
#define	LPUART_VERID_FEATURE_SHIFT   (0U)
#define	LPUART_VERID_FEATURE(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define	LPUART_VERID_MINOR_MASK   (0xFF0000U)
#define	LPUART_VERID_MINOR_SHIFT   (16U)
#define	LPUART_VERID_MINOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define	LPUART_VERID_MAJOR_MASK   (0xFF000000U)
#define	LPUART_VERID_MAJOR_SHIFT   (24U)
#define	LPUART_VERID_MAJOR(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	ADC_PARAM_TRIG_NUM_MASK   (0xFFU)
#define	ADC_PARAM_TRIG_NUM_SHIFT   (0U)
#define	ADC_PARAM_TRIG_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
#define	ADC_PARAM_FIFOSIZE_MASK   (0xFF00U)
#define	ADC_PARAM_FIFOSIZE_SHIFT   (8U)
#define	ADC_PARAM_FIFOSIZE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
#define	ADC_PARAM_CV_NUM_MASK   (0xFF0000U)
#define	ADC_PARAM_CV_NUM_SHIFT   (16U)
#define	ADC_PARAM_CV_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
#define	ADC_PARAM_CMD_NUM_MASK   (0xFF000000U)
#define	ADC_PARAM_CMD_NUM_SHIFT   (24U)
#define	ADC_PARAM_CMD_NUM(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
#define	CMP_PARAM_PARAM_MASK   (0xFFFFFFFFU)
#define	CMP_PARAM_PARAM_SHIFT   (0U)
#define	CMP_PARAM_PARAM(x)   (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
#define	DAC_PARAM_FIFOSZ_MASK   (0x7U)
#define	DAC_PARAM_FIFOSZ_SHIFT   (0U)
#define	DAC_PARAM_FIFOSZ(x)   (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_MASK   (0xFFU)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT   (0U)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_MASK   (0xFF00U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT   (8U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
#define	FLEXIO_PARAM_SHIFTER_MASK   (0xFFU)
#define	FLEXIO_PARAM_SHIFTER_SHIFT   (0U)
#define	FLEXIO_PARAM_SHIFTER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define	FLEXIO_PARAM_TIMER_MASK   (0xFF00U)
#define	FLEXIO_PARAM_TIMER_SHIFT   (8U)
#define	FLEXIO_PARAM_TIMER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define	FLEXIO_PARAM_PIN_MASK   (0xFF0000U)
#define	FLEXIO_PARAM_PIN_SHIFT   (16U)
#define	FLEXIO_PARAM_PIN(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define	FLEXIO_PARAM_TRIGGER_MASK   (0xFF000000U)
#define	FLEXIO_PARAM_TRIGGER_SHIFT   (24U)
#define	FLEXIO_PARAM_TRIGGER(x)   (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
#define	LPUART_PARAM_TXFIFO_MASK   (0xFFU)
#define	LPUART_PARAM_TXFIFO_SHIFT   (0U)
#define	LPUART_PARAM_TXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define	LPUART_PARAM_RXFIFO_MASK   (0xFF00U)
#define	LPUART_PARAM_RXFIFO_SHIFT   (8U)
#define	LPUART_PARAM_RXFIFO(x)   (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

CTRL - LPADC Control Register
#define	ADC_CTRL_ADCEN_MASK   (0x1U)
#define	ADC_CTRL_ADCEN_SHIFT   (0U)
#define	ADC_CTRL_ADCEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
#define	ADC_CTRL_RST_MASK   (0x2U)
#define	ADC_CTRL_RST_SHIFT   (1U)
#define	ADC_CTRL_RST(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
#define	ADC_CTRL_DOZEN_MASK   (0x4U)
#define	ADC_CTRL_DOZEN_SHIFT   (2U)
#define	ADC_CTRL_DOZEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
#define	ADC_CTRL_TRIG_SRC_MASK   (0x18U)
#define	ADC_CTRL_TRIG_SRC_SHIFT   (3U)
#define	ADC_CTRL_TRIG_SRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
#define	ADC_CTRL_RSTFIFO_MASK   (0x100U)
#define	ADC_CTRL_RSTFIFO_SHIFT   (8U)
#define	ADC_CTRL_RSTFIFO(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)

STAT - LPADC Status Register
#define	ADC_STAT_RDY_MASK   (0x1U)
#define	ADC_STAT_RDY_SHIFT   (0U)
#define	ADC_STAT_RDY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
#define	ADC_STAT_FOF_MASK   (0x2U)
#define	ADC_STAT_FOF_SHIFT   (1U)
#define	ADC_STAT_FOF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
#define	ADC_STAT_ADC_ACTIVE_MASK   (0x100U)
#define	ADC_STAT_ADC_ACTIVE_SHIFT   (8U)
#define	ADC_STAT_ADC_ACTIVE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
#define	ADC_STAT_TRGACT_MASK   (0x70000U)
#define	ADC_STAT_TRGACT_SHIFT   (16U)
#define	ADC_STAT_TRGACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
#define	ADC_STAT_CMDACT_MASK   (0xF000000U)
#define	ADC_STAT_CMDACT_SHIFT   (24U)
#define	ADC_STAT_CMDACT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)

IE - Interrupt Enable Register
#define	ADC_IE_FWMIE_MASK   (0x1U)
#define	ADC_IE_FWMIE_SHIFT   (0U)
#define	ADC_IE_FWMIE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
#define	ADC_IE_FOFIE_MASK   (0x2U)
#define	ADC_IE_FOFIE_SHIFT   (1U)
#define	ADC_IE_FOFIE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)

DE - DMA Enable Register
#define	ADC_DE_FWMDE_MASK   (0x1U)
#define	ADC_DE_FWMDE_SHIFT   (0U)
#define	ADC_DE_FWMDE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)

CFG - LPADC Configuration Register
#define	ADC_CFG_TPRICTRL_MASK   (0x1U)
#define	ADC_CFG_TPRICTRL_SHIFT   (0U)
#define	ADC_CFG_TPRICTRL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
#define	ADC_CFG_PWRSEL_MASK   (0x30U)
#define	ADC_CFG_PWRSEL_SHIFT   (4U)
#define	ADC_CFG_PWRSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
#define	ADC_CFG_REFSEL_MASK   (0xC0U)
#define	ADC_CFG_REFSEL_SHIFT   (6U)
#define	ADC_CFG_REFSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define	ADC_CFG_PUDLY_MASK   (0xFF0000U)
#define	ADC_CFG_PUDLY_SHIFT   (16U)
#define	ADC_CFG_PUDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
#define	ADC_CFG_PWREN_MASK   (0x10000000U)
#define	ADC_CFG_PWREN_SHIFT   (28U)
#define	ADC_CFG_PWREN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)

PAUSE - LPADC Pause Register
#define	ADC_PAUSE_PAUSEDLY_MASK   (0x1FFU)
#define	ADC_PAUSE_PAUSEDLY_SHIFT   (0U)
#define	ADC_PAUSE_PAUSEDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
#define	ADC_PAUSE_PAUSEEN_MASK   (0x80000000U)
#define	ADC_PAUSE_PAUSEEN_SHIFT   (31U)
#define	ADC_PAUSE_PAUSEEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)

FCTRL - LPADC FIFO Control Register
#define	ADC_FCTRL_FCOUNT_MASK   (0x1FU)
#define	ADC_FCTRL_FCOUNT_SHIFT   (0U)
#define	ADC_FCTRL_FCOUNT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
#define	ADC_FCTRL_FWMARK_MASK   (0xF0000U)
#define	ADC_FCTRL_FWMARK_SHIFT   (16U)
#define	ADC_FCTRL_FWMARK(x)   (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)

SWTRIG - Software Trigger Register
#define	ADC_SWTRIG_SWT0_MASK   (0x1U)
#define	ADC_SWTRIG_SWT0_SHIFT   (0U)
#define	ADC_SWTRIG_SWT0(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
#define	ADC_SWTRIG_SWT1_MASK   (0x2U)
#define	ADC_SWTRIG_SWT1_SHIFT   (1U)
#define	ADC_SWTRIG_SWT1(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
#define	ADC_SWTRIG_SWT2_MASK   (0x4U)
#define	ADC_SWTRIG_SWT2_SHIFT   (2U)
#define	ADC_SWTRIG_SWT2(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
#define	ADC_SWTRIG_SWT3_MASK   (0x8U)
#define	ADC_SWTRIG_SWT3_SHIFT   (3U)
#define	ADC_SWTRIG_SWT3(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
#define	ADC_SWTRIG_SWT4_MASK   (0x10U)
#define	ADC_SWTRIG_SWT4_SHIFT   (4U)
#define	ADC_SWTRIG_SWT4(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
#define	ADC_SWTRIG_SWT5_MASK   (0x20U)
#define	ADC_SWTRIG_SWT5_SHIFT   (5U)
#define	ADC_SWTRIG_SWT5(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
#define	ADC_SWTRIG_SWT6_MASK   (0x40U)
#define	ADC_SWTRIG_SWT6_SHIFT   (6U)
#define	ADC_SWTRIG_SWT6(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
#define	ADC_SWTRIG_SWT7_MASK   (0x80U)
#define	ADC_SWTRIG_SWT7_SHIFT   (7U)
#define	ADC_SWTRIG_SWT7(x)   (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)

TCTRL - Trigger Control Register
#define	ADC_TCTRL_HTEN_MASK   (0x1U)
#define	ADC_TCTRL_HTEN_SHIFT   (0U)
#define	ADC_TCTRL_HTEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
#define	ADC_TCTRL_CMD_SEL_MASK   (0x2U)
#define	ADC_TCTRL_CMD_SEL_SHIFT   (1U)
#define	ADC_TCTRL_CMD_SEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
#define	ADC_TCTRL_TPRI_MASK   (0x700U)
#define	ADC_TCTRL_TPRI_SHIFT   (8U)
#define	ADC_TCTRL_TPRI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
#define	ADC_TCTRL_TDLY_MASK   (0xF0000U)
#define	ADC_TCTRL_TDLY_SHIFT   (16U)
#define	ADC_TCTRL_TDLY(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
#define	ADC_TCTRL_TCMD_MASK   (0xF000000U)
#define	ADC_TCTRL_TCMD_SHIFT   (24U)
#define	ADC_TCTRL_TCMD(x)   (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)

CMDL - LPADC Command Low Buffer Register
#define	ADC_CMDL_ADCH_MASK   (0x1FU)
#define	ADC_CMDL_ADCH_SHIFT   (0U)
#define	ADC_CMDL_ADCH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
#define	ADC_CMDL_ABSEL_MASK   (0x20U)
#define	ADC_CMDL_ABSEL_SHIFT   (5U)
#define	ADC_CMDL_ABSEL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
#define	ADC_CMDL_DIFF_MASK   (0x40U)
#define	ADC_CMDL_DIFF_SHIFT   (6U)
#define	ADC_CMDL_DIFF(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
#define	ADC_CMDL_CSCALE_MASK   (0x2000U)
#define	ADC_CMDL_CSCALE_SHIFT   (13U)
#define	ADC_CMDL_CSCALE(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)

CMDH - LPADC Command High Buffer Register
#define	ADC_CMDH_CMPEN_MASK   (0x3U)
#define	ADC_CMDH_CMPEN_SHIFT   (0U)
#define	ADC_CMDH_CMPEN(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
#define	ADC_CMDH_LWI_MASK   (0x80U)
#define	ADC_CMDH_LWI_SHIFT   (7U)
#define	ADC_CMDH_LWI(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
#define	ADC_CMDH_STS_MASK   (0x700U)
#define	ADC_CMDH_STS_SHIFT   (8U)
#define	ADC_CMDH_STS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
#define	ADC_CMDH_AVGS_MASK   (0x7000U)
#define	ADC_CMDH_AVGS_SHIFT   (12U)
#define	ADC_CMDH_AVGS(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
#define	ADC_CMDH_LOOP_MASK   (0xF0000U)
#define	ADC_CMDH_LOOP_SHIFT   (16U)
#define	ADC_CMDH_LOOP(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
#define	ADC_CMDH_NEXT_MASK   (0xF000000U)
#define	ADC_CMDH_NEXT_SHIFT   (24U)
#define	ADC_CMDH_NEXT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)

CV - Compare Value Register
#define	ADC_CV_CVL_MASK   (0xFFFFU)
#define	ADC_CV_CVL_SHIFT   (0U)
#define	ADC_CV_CVL(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
#define	ADC_CV_CVH_MASK   (0xFFFF0000U)
#define	ADC_CV_CVH_SHIFT   (16U)
#define	ADC_CV_CVH(x)   (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)

RESFIFO - LPADC Data Result FIFO Register
#define	ADC_RESFIFO_D_MASK   (0xFFFFU)
#define	ADC_RESFIFO_D_SHIFT   (0U)
#define	ADC_RESFIFO_D(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
#define	ADC_RESFIFO_TSRC_MASK   (0x70000U)
#define	ADC_RESFIFO_TSRC_SHIFT   (16U)
#define	ADC_RESFIFO_TSRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
#define	ADC_RESFIFO_LOOPCNT_MASK   (0xF00000U)
#define	ADC_RESFIFO_LOOPCNT_SHIFT   (20U)
#define	ADC_RESFIFO_LOOPCNT(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
#define	ADC_RESFIFO_CMDSRC_MASK   (0xF000000U)
#define	ADC_RESFIFO_CMDSRC_SHIFT   (24U)
#define	ADC_RESFIFO_CMDSRC(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
#define	ADC_RESFIFO_VALID_MASK   (0x80000000U)
#define	ADC_RESFIFO_VALID_SHIFT   (31U)
#define	ADC_RESFIFO_VALID(x)   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)

Detailed Description

Macro Definition Documentation

ADC_CAL_CAL_CODE

#define ADC_CAL_CAL_CODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)

CAL_CODE - Calibration Result Value

ADC_CFG_ADHSC

#define ADC_CFG_ADHSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)

ADHSC - High Speed Configuration 0b0..Normal conversion selected. 0b1..High speed conversion selected.

ADC_CFG_ADICLK

#define ADC_CFG_ADICLK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)

ADICLK - Input Clock Select 0b00..IPG clock 0b01..IPG clock divided by 2 0b10..Reserved 0b11..Asynchronous clock (ADACK)

ADC_CFG_ADIV

#define ADC_CFG_ADIV

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)

ADIV - Clock Divide Select 0b00..Input clock 0b01..Input clock / 2 0b10..Input clock / 4 0b11..Input clock / 8

ADC_CFG_ADLPC

#define ADC_CFG_ADLPC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)

ADLPC - Low-Power Configuration 0b0..ADC hard block not in low power mode. 0b1..ADC hard block in low power mode.

ADC_CFG_ADLSMP

#define ADC_CFG_ADLSMP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)

ADLSMP - Long Sample Time Configuration 0b0..Short sample mode. 0b1..Long sample mode.

ADC_CFG_ADSTS

#define ADC_CFG_ADSTS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)

ADSTS 0b00..Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b 0b01..Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b 0b10..Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b 0b11..Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b

ADC_CFG_ADTRG

#define ADC_CFG_ADTRG

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)

ADTRG - Conversion Trigger Select 0b0..Software trigger selected 0b1..Hardware trigger selected

ADC_CFG_AVGS

#define ADC_CFG_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)

AVGS - Hardware Average select 0b00..4 samples averaged 0b01..8 samples averaged 0b10..16 samples averaged 0b11..32 samples averaged

ADC_CFG_MODE

#define ADC_CFG_MODE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)

MODE - Conversion Mode Selection 0b00..8-bit conversion 0b01..10-bit conversion 0b10..12-bit conversion 0b11..Reserved

ADC_CFG_OVWREN

#define ADC_CFG_OVWREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)

OVWREN - Data Overwrite Enable 0b1..Enable the overwriting. 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.

ADC_CFG_PUDLY [1/2]

#define ADC_CFG_PUDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

PUDLY - Power Up Delay

ADC_CFG_PUDLY [2/2]

#define ADC_CFG_PUDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)

PUDLY - Power Up Delay

ADC_CFG_PWREN [1/2]

#define ADC_CFG_PWREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)

PWREN - LPADC Analog Pre-Enable 0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. 0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed.

ADC_CFG_PWREN [2/2]

#define ADC_CFG_PWREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)

PWREN - LPADC Analog Pre-Enable 0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. 0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed.

ADC_CFG_PWRSEL [1/2]

#define ADC_CFG_PWRSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)

PWRSEL - Power Configuration Select 0b00..Level 1 (Lowest power setting) 0b01..Level 2 0b10..Level 3 0b11..Level 4 (Highest power setting)

ADC_CFG_PWRSEL [2/2]

#define ADC_CFG_PWRSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)

PWRSEL - Power Configuration Select 0b00..Level 1 (Lowest power setting) 0b01..Level 2 0b10..Level 3 0b11..Level 4 (Highest power setting)

ADC_CFG_REFSEL [1/3]

#define ADC_CFG_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..Selects VREFH/VREFL as reference voltage. 0b01..Reserved 0b10..Reserved 0b11..Reserved

ADC_CFG_REFSEL [2/3]

#define ADC_CFG_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..(Default) Option 1 setting. 0b01..Option 2 setting. 0b10..Option 3 setting. 0b11..Reserved

ADC_CFG_REFSEL [3/3]

#define ADC_CFG_REFSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)

REFSEL - Voltage Reference Selection 0b00..(Default) Option 1 setting. 0b01..Option 2 setting. 0b10..Option 3 setting. 0b11..Reserved

ADC_CFG_TPRICTRL [1/2]

#define ADC_CFG_TPRICTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

TPRICTRL - LPADC trigger priority control 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion.

ADC_CFG_TPRICTRL [2/2]

#define ADC_CFG_TPRICTRL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)

TPRICTRL - LPADC trigger priority control 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 0b1..If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion.

ADC_CMDH_AVGS [1/2]

#define ADC_CMDH_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

AVGS - Hardware Average Select 0b000..Single conversion. 0b001..2 conversions averaged. 0b010..4 conversions averaged. 0b011..8 conversions averaged. 0b100..16 conversions averaged. 0b101..32 conversions averaged. 0b110..64 conversions averaged. 0b111..128 conversions averaged.

ADC_CMDH_AVGS [2/2]

#define ADC_CMDH_AVGS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)

AVGS - Hardware Average Select 0b000..Single conversion. 0b001..2 conversions averaged. 0b010..4 conversions averaged. 0b011..8 conversions averaged. 0b100..16 conversions averaged. 0b101..32 conversions averaged. 0b110..64 conversions averaged. 0b111..128 conversions averaged.

ADC_CMDH_CMPEN [1/2]

#define ADC_CMDH_CMPEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

CMPEN - Compare Function Enable 0b00..Compare disabled. 0b01..Reserved 0b10..Compare enabled. Store on true. 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.

ADC_CMDH_CMPEN [2/2]

#define ADC_CMDH_CMPEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)

CMPEN - Compare Function Enable 0b00..Compare disabled. 0b01..Reserved 0b10..Compare enabled. Store on true. 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.

ADC_CMDH_LOOP [1/2]

#define ADC_CMDH_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

LOOP - Loop Count Select 0b0000..Looping not enabled. Command executes 1 time. 0b0001..Loop 1 time. Command executes 2 times. 0b0010..Loop 2 times. Command executes 3 times. 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. 0b1111..Loop 15 times. Command executes 16 times.

ADC_CMDH_LOOP [2/2]

#define ADC_CMDH_LOOP

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)

LOOP - Loop Count Select 0b0000..Looping not enabled. Command executes 1 time. 0b0001..Loop 1 time. Command executes 2 times. 0b0010..Loop 2 times. Command executes 3 times. 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. 0b1111..Loop 15 times. Command executes 16 times.

ADC_CMDH_LWI [1/2]

#define ADC_CMDH_LWI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

LWI - Loop with Increment 0b0..Auto channel increment disabled 0b1..Auto channel increment enabled

ADC_CMDH_LWI [2/2]

#define ADC_CMDH_LWI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)

LWI - Loop with Increment 0b0..Auto channel increment disabled 0b1..Auto channel increment enabled

ADC_CMDH_NEXT [1/2]

#define ADC_CMDH_NEXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)

NEXT - Next Command Select 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0b0001..Select CMD1 command buffer register as next command. 0b0010-0b1110..Select corresponding CMD command buffer register as next command 0b1111..Select CMD15 command buffer register as next command.

ADC_CMDH_NEXT [2/2]

#define ADC_CMDH_NEXT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)

NEXT - Next Command Select 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0b0001..Select CMD1 command buffer register as next command. 0b0010-0b1110..Select corresponding CMD command buffer register as next command 0b1111..Select CMD15 command buffer register as next command.

ADC_CMDH_STS [1/2]

#define ADC_CMDH_STS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

STS - Sample Time Select 0b000..Minimum sample time of 3 ADCK cycles. 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.

ADC_CMDH_STS [2/2]

#define ADC_CMDH_STS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)

STS - Sample Time Select 0b000..Minimum sample time of 3 ADCK cycles. 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time. 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time. 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time. 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time. 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time. 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time. 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.

ADC_CMDL_ABSEL [1/2]

#define ADC_CMDL_ABSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)

ABSEL - A-side vs. B-side Select 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).

ADC_CMDL_ABSEL [2/2]

#define ADC_CMDL_ABSEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)

ABSEL - A-side vs. B-side Select 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB). 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).

ADC_CMDL_ADCH [1/2]

#define ADC_CMDL_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

ADCH - Input channel select 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.

ADC_CMDL_ADCH [2/2]

#define ADC_CMDL_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)

ADCH - Input channel select 0b00000..Select CH0A or CH0B or CH0A/CH0B pair. 0b00001..Select CH1A or CH1B or CH1A/CH1B pair. 0b00010..Select CH2A or CH2B or CH2A/CH2B pair. 0b00011..Select CH3A or CH3B or CH3A/CH3B pair. 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair. 0b11110..Select CH30A or CH30B or CH30A/CH30B pair. 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.

ADC_CMDL_CSCALE [1/2]

#define ADC_CMDL_CSCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)

CSCALE - Channel Scale 0b0..Scale selected analog channel (Factor of 30/64) 0b1..(Default) Full scale (Factor of 1)

ADC_CMDL_CSCALE [2/2]

#define ADC_CMDL_CSCALE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)

CSCALE - Channel Scale 0b0..Scale selected analog channel (Factor of 30/64) 0b1..(Default) Full scale (Factor of 1)

ADC_CMDL_DIFF [1/2]

#define ADC_CMDL_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended mode. 0b1..Differential mode.

ADC_CMDL_DIFF [2/2]

#define ADC_CMDL_DIFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)

DIFF - Differential Mode Enable 0b0..Single-ended mode. 0b1..Differential mode.

ADC_CTRL_ADCEN [1/2]

#define ADC_CTRL_ADCEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

ADCEN - LPADC Enable 0b0..LPADC is disabled. 0b1..LPADC is enabled.

ADC_CTRL_ADCEN [2/2]

#define ADC_CTRL_ADCEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)

ADCEN - LPADC Enable 0b0..LPADC is disabled. 0b1..LPADC is enabled.

ADC_CTRL_DOZEN [1/2]

#define ADC_CTRL_DOZEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

DOZEN - Doze Enable 0b0..LPADC is enabled in Doze mode. 0b1..LPADC is disabled in Doze mode.

ADC_CTRL_DOZEN [2/2]

#define ADC_CTRL_DOZEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)

DOZEN - Doze Enable 0b0..LPADC is enabled in Doze mode. 0b1..LPADC is disabled in Doze mode.

ADC_CTRL_RST [1/2]

#define ADC_CTRL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

RST - Software Reset 0b0..LPADC logic is not reset. 0b1..LPADC logic is reset.

ADC_CTRL_RST [2/2]

#define ADC_CTRL_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)

RST - Software Reset 0b0..LPADC logic is not reset. 0b1..LPADC logic is reset.

ADC_CTRL_RSTFIFO [1/2]

#define ADC_CTRL_RSTFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)

RSTFIFO - Reset FIFO 0b0..No effect. 0b1..FIFO is reset.

ADC_CTRL_RSTFIFO [2/2]

#define ADC_CTRL_RSTFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)

RSTFIFO - Reset FIFO 0b0..No effect. 0b1..FIFO is reset.

ADC_CTRL_TRIG_SRC [1/2]

#define ADC_CTRL_TRIG_SRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)

TRIG_SRC - Hardware trigger source selection 0b00..ADC_ETC hw trigger , and HW trigger are enabled 0b01..ADC_ETC hw trigger is enabled 0b10..HW trigger is enabled 0b11..Reserved

ADC_CTRL_TRIG_SRC [2/2]

#define ADC_CTRL_TRIG_SRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)

TRIG_SRC - Hardware trigger source selection 0b00..ADC_ETC hw trigger , and HW trigger are enabled 0b01..ADC_ETC hw trigger is enabled 0b10..HW trigger is enabled 0b11..Reserved

ADC_CV_CV1

#define ADC_CV_CV1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)

CV1 - Compare Value 1

ADC_CV_CV2

#define ADC_CV_CV2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)

CV2 - Compare Value 2

ADC_CV_CVH [1/2]

#define ADC_CV_CVH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)

CVH - Compare Value High.

ADC_CV_CVH [2/2]

#define ADC_CV_CVH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)

CVH - Compare Value High.

ADC_CV_CVL [1/2]

#define ADC_CV_CVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

CVL - Compare Value Low

ADC_CV_CVL [2/2]

#define ADC_CV_CVL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)

CVL - Compare Value Low

ADC_DE_FWMDE [1/2]

#define ADC_DE_FWMDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)

FWMDE - FIFO Watermark DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

ADC_DE_FWMDE [2/2]

#define ADC_DE_FWMDE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)

FWMDE - FIFO Watermark DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

ADC_FCTRL_FCOUNT [1/2]

#define ADC_FCTRL_FCOUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

FCOUNT - Result FIFO counter 0b00000..No data stored in FIFO 0b00001..1 dataword stored in FIFO 0b00010..2 datawords stored in FIFO 0b00100..4 datawords stored in FIFO 0b01000..8 datawords stored in FIFO 0b10000..16 datawords stored in FIFO

ADC_FCTRL_FCOUNT [2/2]

#define ADC_FCTRL_FCOUNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)

FCOUNT - Result FIFO counter 0b00000..No data stored in FIFO 0b00001..1 dataword stored in FIFO 0b00010..2 datawords stored in FIFO 0b00100..4 datawords stored in FIFO 0b01000..8 datawords stored in FIFO 0b10000..16 datawords stored in FIFO

ADC_FCTRL_FWMARK [1/2]

#define ADC_FCTRL_FWMARK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)

FWMARK - Watermark level selection 0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion 0b0001..Generates STAT[RDY] flag after 2nd successful conversion 0b0010..Generates STAT[RDY] flag after 3rd successful conversion 0b0011..Generates STAT[RDY] flag after 4th successful conversion 0b0100..Generates STAT[RDY] flag after 5th successful conversion 0b0101..Generates STAT[RDY] flag after 6th successful conversion 0b0110..Generates STAT[RDY] flag after 7th successful conversion 0b0111..Generates STAT[RDY] flag after 8th successful conversion 0b1000..Generates STAT[RDY] flag after 9th successful conversion 0b1001..Generates STAT[RDY] flag after 10th successful conversion 0b1010..Generates STAT[RDY] flag after 11th successful conversion 0b1011..Generates STAT[RDY] flag after 12th successful conversion 0b1100..Generates STAT[RDY] flag after 13th successful conversion 0b1101..Generates STAT[RDY] flag after 14th successful conversion 0b1110..Generates STAT[RDY] flag after 15th successful conversion 0b1111..Generates STAT[RDY] flag after 16th successful conversion

ADC_FCTRL_FWMARK [2/2]

#define ADC_FCTRL_FWMARK

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)

FWMARK - Watermark level selection 0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion 0b0001..Generates STAT[RDY] flag after 2nd successful conversion 0b0010..Generates STAT[RDY] flag after 3rd successful conversion 0b0011..Generates STAT[RDY] flag after 4th successful conversion 0b0100..Generates STAT[RDY] flag after 5th successful conversion 0b0101..Generates STAT[RDY] flag after 6th successful conversion 0b0110..Generates STAT[RDY] flag after 7th successful conversion 0b0111..Generates STAT[RDY] flag after 8th successful conversion 0b1000..Generates STAT[RDY] flag after 9th successful conversion 0b1001..Generates STAT[RDY] flag after 10th successful conversion 0b1010..Generates STAT[RDY] flag after 11th successful conversion 0b1011..Generates STAT[RDY] flag after 12th successful conversion 0b1100..Generates STAT[RDY] flag after 13th successful conversion 0b1101..Generates STAT[RDY] flag after 14th successful conversion 0b1110..Generates STAT[RDY] flag after 15th successful conversion 0b1111..Generates STAT[RDY] flag after 16th successful conversion

ADC_GC_ACFE

#define ADC_GC_ACFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)

ACFE - Compare Function Enable 0b0..Compare function disabled 0b1..Compare function enabled

ADC_GC_ACFGT

#define ADC_GC_ACFGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)

ACFGT - Compare Function Greater Than Enable 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers.

ADC_GC_ACREN

#define ADC_GC_ACREN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)

ACREN - Compare Function Range Enable 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.

ADC_GC_ADACKEN

#define ADC_GC_ADACKEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)

ADACKEN - Asynchronous clock output enable 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC

ADC_GC_ADCO

#define ADC_GC_ADCO

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)

ADCO - Continuous Conversion Enable 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.

ADC_GC_AVGE

#define ADC_GC_AVGE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)

AVGE - Hardware average enable 0b0..Hardware average function disabled 0b1..Hardware average function enabled

ADC_GC_CAL

#define ADC_GC_CAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)

CAL - Calibration

ADC_GC_DMAEN

#define ADC_GC_DMAEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)

DMAEN - DMA Enable 0b0..DMA disabled (default) 0b1..DMA enabled

ADC_GS_ADACT

#define ADC_GS_ADACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)

ADACT - Conversion Active 0b0..Conversion not in progress. 0b1..Conversion in progress.

ADC_GS_AWKST

#define ADC_GS_AWKST

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)

AWKST - Asynchronous wakeup interrupt status 0b1..Asynchronous wake up interrupt occurred in stop mode. 0b0..No asynchronous interrupt.

ADC_GS_CALF

#define ADC_GS_CALF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)

CALF - Calibration Failed Flag 0b0..Calibration completed normally. 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.

ADC_HC_ADCH

#define ADC_HC_ADCH

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)

ADCH - Input Channel Select 0b00000-0b01111..External channels 0 to 15 See External Signals for more information 0b10000..External channel selection from ADC_ETC 0b10001-0b10111..Reserved 0b11000..Reserved. 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally 0b11010..Reserved. 0b11011..Reserved. 0b11100-0b11110..Reserved. 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.

ADC_HC_AIEN

#define ADC_HC_AIEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)

AIEN - Conversion Complete Interrupt Enable/Disable Control 0b1..Conversion complete interrupt enabled 0b0..Conversion complete interrupt disabled

ADC_HS_COCO0

#define ADC_HS_COCO0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)

COCO0 - Conversion Complete Flag

ADC_HS_COCO1

#define ADC_HS_COCO1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)

COCO1 - Conversion Complete Flag

ADC_IE_FOFIE [1/2]

#define ADC_IE_FOFIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)

FOFIE - Result FIFO Overflow Interrupt Enable 0b0..FIFO overflow interrupts are not enabled. 0b1..FIFO overflow interrupts are enabled.

ADC_IE_FOFIE [2/2]

#define ADC_IE_FOFIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)

FOFIE - Result FIFO Overflow Interrupt Enable 0b0..FIFO overflow interrupts are not enabled. 0b1..FIFO overflow interrupts are enabled.

ADC_IE_FWMIE [1/2]

#define ADC_IE_FWMIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)

FWMIE - FIFO Watermark Interrupt Enable 0b0..FIFO watermark interrupts are not enabled. 0b1..FIFO watermark interrupts are enabled.

ADC_IE_FWMIE [2/2]

#define ADC_IE_FWMIE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)

FWMIE - FIFO Watermark Interrupt Enable 0b0..FIFO watermark interrupts are not enabled. 0b1..FIFO watermark interrupts are enabled.

ADC_OFS_OFS

#define ADC_OFS_OFS

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)

OFS - Offset value

ADC_OFS_SIGN

#define ADC_OFS_SIGN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)

SIGN - Sign bit 0b0..The offset value is added with the raw result 0b1..The offset value is subtracted from the raw converted value

ADC_PARAM_CMD_NUM [1/2]

#define ADC_PARAM_CMD_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)

CMD_NUM - Command Buffer Number 0b00001111..15 command buffers implemented

ADC_PARAM_CMD_NUM [2/2]

#define ADC_PARAM_CMD_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)

CMD_NUM - Command Buffer Number 0b00001111..15 command buffers implemented

ADC_PARAM_CV_NUM [1/2]

#define ADC_PARAM_CV_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

CV_NUM - Compare Value Number 0b00000100..4 compare value registers implemented

ADC_PARAM_CV_NUM [2/2]

#define ADC_PARAM_CV_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)

CV_NUM - Compare Value Number 0b00000100..4 compare value registers implemented

ADC_PARAM_FIFOSIZE [1/2]

#define ADC_PARAM_FIFOSIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

FIFOSIZE - Result FIFO Depth 0b00010000..Result FIFO depth = 16 datawords.

ADC_PARAM_FIFOSIZE [2/2]

#define ADC_PARAM_FIFOSIZE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)

FIFOSIZE - Result FIFO Depth 0b00010000..Result FIFO depth = 16 datawords.

ADC_PARAM_TRIG_NUM [1/2]

#define ADC_PARAM_TRIG_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

TRIG_NUM - Trigger Number 0b00001000..8 hardware triggers implemented

ADC_PARAM_TRIG_NUM [2/2]

#define ADC_PARAM_TRIG_NUM

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)

TRIG_NUM - Trigger Number 0b00001000..8 hardware triggers implemented

ADC_PAUSE_PAUSEDLY [1/2]

#define ADC_PAUSE_PAUSEDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

PAUSEDLY - Pause Delay

ADC_PAUSE_PAUSEDLY [2/2]

#define ADC_PAUSE_PAUSEDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)

PAUSEDLY - Pause Delay

ADC_PAUSE_PAUSEEN [1/2]

#define ADC_PAUSE_PAUSEEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)

PAUSEEN - PAUSE Option Enable 0b0..Pause operation disabled 0b1..Pause operation enabled

ADC_PAUSE_PAUSEEN [2/2]

#define ADC_PAUSE_PAUSEEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)

PAUSEEN - PAUSE Option Enable 0b0..Pause operation disabled 0b1..Pause operation enabled

ADC_R_CDATA

#define ADC_R_CDATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)

CDATA - Data (result of an ADC conversion)

ADC_RESFIFO_CMDSRC [1/2]

#define ADC_RESFIFO_CMDSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

CMDSRC - Command Buffer Source 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. 0b0001..CMD1 buffer used as control settings for this conversion. 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. 0b1111..CMD15 buffer used as control settings for this conversion.

ADC_RESFIFO_CMDSRC [2/2]

#define ADC_RESFIFO_CMDSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)

CMDSRC - Command Buffer Source 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. 0b0001..CMD1 buffer used as control settings for this conversion. 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion. 0b1111..CMD15 buffer used as control settings for this conversion.

ADC_RESFIFO_D [1/2]

#define ADC_RESFIFO_D

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

D - Data result

ADC_RESFIFO_D [2/2]

#define ADC_RESFIFO_D

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)

D - Data result

ADC_RESFIFO_LOOPCNT [1/2]

#define ADC_RESFIFO_LOOPCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

LOOPCNT - Loop count value 0b0000..Result is from initial conversion in command. 0b0001..Result is from second conversion in command. 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. 0b1111..Result is from 16th conversion in command.

ADC_RESFIFO_LOOPCNT [2/2]

#define ADC_RESFIFO_LOOPCNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)

LOOPCNT - Loop count value 0b0000..Result is from initial conversion in command. 0b0001..Result is from second conversion in command. 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. 0b1111..Result is from 16th conversion in command.

ADC_RESFIFO_TSRC [1/2]

#define ADC_RESFIFO_TSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

TSRC - Trigger Source 0b000..Trigger source 0 initiated this conversion. 0b001..Trigger source 1 initiated this conversion. 0b010-0b110..Corresponding trigger source initiated this conversion. 0b111..Trigger source 7 initiated this conversion.

ADC_RESFIFO_TSRC [2/2]

#define ADC_RESFIFO_TSRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)

TSRC - Trigger Source 0b000..Trigger source 0 initiated this conversion. 0b001..Trigger source 1 initiated this conversion. 0b010-0b110..Corresponding trigger source initiated this conversion. 0b111..Trigger source 7 initiated this conversion.

ADC_RESFIFO_VALID [1/2]

#define ADC_RESFIFO_VALID

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)

VALID - FIFO entry is valid 0b0..FIFO is empty. Discard any read from RESFIFO. 0b1..FIFO record read from RESFIFO is valid.

ADC_RESFIFO_VALID [2/2]

#define ADC_RESFIFO_VALID

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)

VALID - FIFO entry is valid 0b0..FIFO is empty. Discard any read from RESFIFO. 0b1..FIFO record read from RESFIFO is valid.

ADC_STAT_ADC_ACTIVE [1/2]

#define ADC_STAT_ADC_ACTIVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

ADC_ACTIVE - ADC Active 0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed. 0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.

ADC_STAT_ADC_ACTIVE [2/2]

#define ADC_STAT_ADC_ACTIVE

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)

ADC_ACTIVE - ADC Active 0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed. 0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.

ADC_STAT_CMDACT [1/2]

#define ADC_STAT_CMDACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)

CMDACT - Command Active 0b0000..No command is currently in progress. 0b0001..Command 1 currently being executed. 0b0010..Command 2 currently being executed. 0b0011-0b1111..Associated command number is currently being executed.

ADC_STAT_CMDACT [2/2]

#define ADC_STAT_CMDACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)

CMDACT - Command Active 0b0000..No command is currently in progress. 0b0001..Command 1 currently being executed. 0b0010..Command 2 currently being executed. 0b0011-0b1111..Associated command number is currently being executed.

ADC_STAT_FOF [1/2]

#define ADC_STAT_FOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)

FOF - Result FIFO Overflow Flag 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.

ADC_STAT_FOF [2/2]

#define ADC_STAT_FOF

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)

FOF - Result FIFO Overflow Flag 0b0..No result FIFO overflow has occurred since the last time the flag was cleared. 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.

ADC_STAT_RDY [1/2]

#define ADC_STAT_RDY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)

RDY - Result FIFO Ready Flag 0b0..Result FIFO data level not above watermark level. 0b1..Result FIFO holding data above watermark level.

ADC_STAT_RDY [2/2]

#define ADC_STAT_RDY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)

RDY - Result FIFO Ready Flag 0b0..Result FIFO data level not above watermark level. 0b1..Result FIFO holding data above watermark level.

ADC_STAT_TRGACT [1/2]

#define ADC_STAT_TRGACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

TRGACT - Trigger Active 0b000..Command (sequence) associated with Trigger 0 currently being executed. 0b001..Command (sequence) associated with Trigger 1 currently being executed. 0b010..Command (sequence) associated with Trigger 2 currently being executed. 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.

ADC_STAT_TRGACT [2/2]

#define ADC_STAT_TRGACT

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)

TRGACT - Trigger Active 0b000..Command (sequence) associated with Trigger 0 currently being executed. 0b001..Command (sequence) associated with Trigger 1 currently being executed. 0b010..Command (sequence) associated with Trigger 2 currently being executed. 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.

ADC_SWTRIG_SWT0 [1/2]

#define ADC_SWTRIG_SWT0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

SWT0 - Software trigger 0 event 0b0..No trigger 0 event generated. 0b1..Trigger 0 event generated.

ADC_SWTRIG_SWT0 [2/2]

#define ADC_SWTRIG_SWT0

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)

SWT0 - Software trigger 0 event 0b0..No trigger 0 event generated. 0b1..Trigger 0 event generated.

ADC_SWTRIG_SWT1 [1/2]

#define ADC_SWTRIG_SWT1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)

SWT1 - Software trigger 1 event 0b0..No trigger 1 event generated. 0b1..Trigger 1 event generated.

ADC_SWTRIG_SWT1 [2/2]

#define ADC_SWTRIG_SWT1

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)

SWT1 - Software trigger 1 event 0b0..No trigger 1 event generated. 0b1..Trigger 1 event generated.

ADC_SWTRIG_SWT2 [1/2]

#define ADC_SWTRIG_SWT2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)

SWT2 - Software trigger 2 event 0b0..No trigger 2 event generated. 0b1..Trigger 2 event generated.

ADC_SWTRIG_SWT2 [2/2]

#define ADC_SWTRIG_SWT2

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)

SWT2 - Software trigger 2 event 0b0..No trigger 2 event generated. 0b1..Trigger 2 event generated.

ADC_SWTRIG_SWT3 [1/2]

#define ADC_SWTRIG_SWT3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)

SWT3 - Software trigger 3 event 0b0..No trigger 3 event generated. 0b1..Trigger 3 event generated.

ADC_SWTRIG_SWT3 [2/2]

#define ADC_SWTRIG_SWT3

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)

SWT3 - Software trigger 3 event 0b0..No trigger 3 event generated. 0b1..Trigger 3 event generated.

ADC_SWTRIG_SWT4 [1/2]

#define ADC_SWTRIG_SWT4

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)

SWT4 - Software trigger 4 event 0b0..No trigger 4 event generated. 0b1..Trigger 4 event generated.

ADC_SWTRIG_SWT4 [2/2]

#define ADC_SWTRIG_SWT4

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)

SWT4 - Software trigger 4 event 0b0..No trigger 4 event generated. 0b1..Trigger 4 event generated.

ADC_SWTRIG_SWT5 [1/2]

#define ADC_SWTRIG_SWT5

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)

SWT5 - Software trigger 5 event 0b0..No trigger 5 event generated. 0b1..Trigger 5 event generated.

ADC_SWTRIG_SWT5 [2/2]

#define ADC_SWTRIG_SWT5

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)

SWT5 - Software trigger 5 event 0b0..No trigger 5 event generated. 0b1..Trigger 5 event generated.

ADC_SWTRIG_SWT6 [1/2]

#define ADC_SWTRIG_SWT6

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)

SWT6 - Software trigger 6 event 0b0..No trigger 6 event generated. 0b1..Trigger 6 event generated.

ADC_SWTRIG_SWT6 [2/2]

#define ADC_SWTRIG_SWT6

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)

SWT6 - Software trigger 6 event 0b0..No trigger 6 event generated. 0b1..Trigger 6 event generated.

ADC_SWTRIG_SWT7 [1/2]

#define ADC_SWTRIG_SWT7

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)

SWT7 - Software trigger 7 event 0b0..No trigger 7 event generated. 0b1..Trigger 7 event generated.

ADC_SWTRIG_SWT7 [2/2]

#define ADC_SWTRIG_SWT7

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)

SWT7 - Software trigger 7 event 0b0..No trigger 7 event generated. 0b1..Trigger 7 event generated.

ADC_TCTRL_CMD_SEL [1/2]

#define ADC_TCTRL_CMD_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)

CMD_SEL 0b0..TCTRLa[TCMD] will determine the command 0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].

ADC_TCTRL_CMD_SEL [2/2]

#define ADC_TCTRL_CMD_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)

CMD_SEL 0b0..TCTRLa[TCMD] will determine the command 0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].

ADC_TCTRL_HTEN [1/2]

#define ADC_TCTRL_HTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

HTEN - Trigger enable 0b0..Hardware trigger source disabled 0b1..Hardware trigger source enabled

ADC_TCTRL_HTEN [2/2]

#define ADC_TCTRL_HTEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)

HTEN - Trigger enable 0b0..Hardware trigger source disabled 0b1..Hardware trigger source enabled

ADC_TCTRL_TCMD [1/2]

#define ADC_TCTRL_TCMD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)

TCMD - Trigger command select 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. 0b0001..CMD1 is executed 0b0010-0b1110..Corresponding CMD is executed 0b1111..CMD15 is executed

ADC_TCTRL_TCMD [2/2]

#define ADC_TCTRL_TCMD

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)

TCMD - Trigger command select 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. 0b0001..CMD1 is executed 0b0010-0b1110..Corresponding CMD is executed 0b1111..CMD15 is executed

ADC_TCTRL_TDLY [1/2]

#define ADC_TCTRL_TDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

TDLY - Trigger delay select

ADC_TCTRL_TDLY [2/2]

#define ADC_TCTRL_TDLY

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)

TDLY - Trigger delay select

ADC_TCTRL_TPRI [1/2]

#define ADC_TCTRL_TPRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

TPRI - Trigger priority setting 0b000..Set to highest priority, Level 1 0b001-0b110..Set to corresponding priority level 0b111..Set to lowest priority, Level 8

ADC_TCTRL_TPRI [2/2]

#define ADC_TCTRL_TPRI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)

TPRI - Trigger priority setting 0b000..Set to highest priority, Level 1 0b001-0b110..Set to corresponding priority level 0b111..Set to lowest priority, Level 8

ADC_VERID_CALOFSI [1/2]

#define ADC_VERID_CALOFSI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

CALOFSI - Calibration Offset Function Implemented 0b0..Offset calibration and offset trimming not implemented. 0b1..Offset calibration and offset trimming implemented.

ADC_VERID_CALOFSI [2/2]

#define ADC_VERID_CALOFSI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)

CALOFSI - Calibration Offset Function Implemented 0b0..Offset calibration and offset trimming not implemented. 0b1..Offset calibration and offset trimming implemented.

ADC_VERID_CSW [1/2]

#define ADC_VERID_CSW

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

CSW - Channel Scale Width 0b000..Channel scaling not supported. 0b001..Channel scaling supported. 1-bit CSCALE control field. 0b110..Channel scaling supported. 6-bit CSCALE control field.

ADC_VERID_CSW [2/2]

#define ADC_VERID_CSW

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)

CSW - Channel Scale Width 0b000..Channel scaling not supported. 0b001..Channel scaling supported. 1-bit CSCALE control field. 0b110..Channel scaling supported. 6-bit CSCALE control field.

ADC_VERID_DIFFEN [1/2]

#define ADC_VERID_DIFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

DIFFEN - Differential Supported 0b0..Differential operation not supported. 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.

ADC_VERID_DIFFEN [2/2]

#define ADC_VERID_DIFFEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)

DIFFEN - Differential Supported 0b0..Differential operation not supported. 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.

ADC_VERID_IADCKI [1/2]

#define ADC_VERID_IADCKI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

IADCKI - Internal LPADC Clock implemented 0b0..Internal clock source not implemented. 0b1..Internal clock source (and CFG[ADCKEN]) implemented.

ADC_VERID_IADCKI [2/2]

#define ADC_VERID_IADCKI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)

IADCKI - Internal LPADC Clock implemented 0b0..Internal clock source not implemented. 0b1..Internal clock source (and CFG[ADCKEN]) implemented.

ADC_VERID_MAJOR [1/2]

#define ADC_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)

MAJOR - Major Version Number

ADC_VERID_MAJOR [2/2]

#define ADC_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)

MAJOR - Major Version Number

ADC_VERID_MINOR [1/2]

#define ADC_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

MINOR - Minor Version Number

ADC_VERID_MINOR [2/2]

#define ADC_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)

MINOR - Minor Version Number

ADC_VERID_MVI [1/2]

#define ADC_VERID_MVI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

MVI - Multi Vref Implemented 0b0..Single voltage reference input supported. 0b1..Multiple voltage reference inputs supported.

ADC_VERID_MVI [2/2]

#define ADC_VERID_MVI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)

MVI - Multi Vref Implemented 0b0..Single voltage reference input supported. 0b1..Multiple voltage reference inputs supported.

ADC_VERID_RES [1/2]

#define ADC_VERID_RES

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

RES - Resolution 0b0..Up to 13-bit differential/12-bit single ended resolution supported. 0b1..Up to 16-bit differential/15-bit single ended resolution supported.

ADC_VERID_RES [2/2]

#define ADC_VERID_RES

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)

RES - Resolution 0b0..Up to 13-bit differential/12-bit single ended resolution supported. 0b1..Up to 16-bit differential/15-bit single ended resolution supported.

ADC_VERID_VR1RNGI [1/2]

#define ADC_VERID_VR1RNGI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

VR1RNGI - Voltage Reference 1 Range Control Bit Implemented 0b0..Range control not required. CFG[VREF1RNG] is not implemented. 0b1..Range control required. CFG[VREF1RNG] is implemented.

ADC_VERID_VR1RNGI [2/2]

#define ADC_VERID_VR1RNGI

(

x

)

(((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)

VR1RNGI - Voltage Reference 1 Range Control Bit Implemented 0b0..Range control not required. CFG[VREF1RNG] is not implemented. 0b1..Range control required. CFG[VREF1RNG] is implemented.

CMP_PARAM_PARAM [1/2]

#define CMP_PARAM_PARAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.

CMP_PARAM_PARAM [2/2]

#define CMP_PARAM_PARAM

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)

PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.

CMP_VERID_FEATURE [1/2]

#define CMP_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number. This read only filed returns the feature set number.

CMP_VERID_FEATURE [2/2]

#define CMP_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number. This read only filed returns the feature set number.

CMP_VERID_MAJOR [1/2]

#define CMP_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

MAJOR - Major Version Number. This read only field returns the major version number for the module specification.

CMP_VERID_MAJOR [2/2]

#define CMP_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)

MAJOR - Major Version Number. This read only field returns the major version number for the module specification.

CMP_VERID_MINOR [1/2]

#define CMP_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.

CMP_VERID_MINOR [2/2]

#define CMP_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)

MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.

DAC_PARAM_FIFOSZ [1/2]

#define DAC_PARAM_FIFOSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

FIFOSZ - FIFO size 0b000..FIFO depth is 2 0b001..FIFO depth is 4 0b010..FIFO depth is 8 0b011..FIFO depth is 16 0b100..FIFO depth is 32 0b101..FIFO depth is 64 0b110..FIFO depth is 128 0b111..FIFO depth is 256

DAC_PARAM_FIFOSZ [2/2]

#define DAC_PARAM_FIFOSZ

(

x

)

(((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)

FIFOSZ - FIFO size 0b000..FIFO depth is 2 0b001..FIFO depth is 4 0b010..FIFO depth is 8 0b011..FIFO depth is 16 0b100..FIFO depth is 32 0b101..FIFO depth is 64 0b110..FIFO depth is 128 0b111..FIFO depth is 256

EMVSIM_PARAM_RX_FIFO_DEPTH [1/2]

#define EMVSIM_PARAM_RX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)

RX_FIFO_DEPTH - Receive FIFO Depth

EMVSIM_PARAM_RX_FIFO_DEPTH [2/2]

#define EMVSIM_PARAM_RX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)

RX_FIFO_DEPTH - Receive FIFO Depth

EMVSIM_PARAM_TX_FIFO_DEPTH [1/2]

#define EMVSIM_PARAM_TX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

TX_FIFO_DEPTH - Transmit FIFO Depth

EMVSIM_PARAM_TX_FIFO_DEPTH [2/2]

#define EMVSIM_PARAM_TX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

TX_FIFO_DEPTH - Transmit FIFO Depth

FLEXIO_PARAM_PIN [1/2]

#define FLEXIO_PARAM_PIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

PIN - Pin Number

FLEXIO_PARAM_PIN [2/2]

#define FLEXIO_PARAM_PIN

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)

PIN - Pin Number

FLEXIO_PARAM_SHIFTER [1/2]

#define FLEXIO_PARAM_SHIFTER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

SHIFTER - Shifter Number

FLEXIO_PARAM_SHIFTER [2/2]

#define FLEXIO_PARAM_SHIFTER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)

SHIFTER - Shifter Number

FLEXIO_PARAM_TIMER [1/2]

#define FLEXIO_PARAM_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

TIMER - Timer Number

FLEXIO_PARAM_TIMER [2/2]

#define FLEXIO_PARAM_TIMER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)

TIMER - Timer Number

FLEXIO_PARAM_TRIGGER [1/2]

#define FLEXIO_PARAM_TRIGGER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

TRIGGER - Trigger Number

FLEXIO_PARAM_TRIGGER [2/2]

#define FLEXIO_PARAM_TRIGGER

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)

TRIGGER - Trigger Number

FLEXIO_VERID_FEATURE [1/2]

#define FLEXIO_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.

FLEXIO_VERID_FEATURE [2/2]

#define FLEXIO_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)

FEATURE - Feature Specification Number 0b0000000000000000..Standard features implemented. 0b0000000000000001..Supports state, logic and parallel modes. 0b0000000000000010..Supports pin control registers. 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.

FLEXIO_VERID_MAJOR [1/2]

#define FLEXIO_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

MAJOR - Major Version Number

FLEXIO_VERID_MAJOR [2/2]

#define FLEXIO_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)

MAJOR - Major Version Number

FLEXIO_VERID_MINOR [1/2]

#define FLEXIO_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

MINOR - Minor Version Number

FLEXIO_VERID_MINOR [2/2]

#define FLEXIO_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPUART_PARAM_RXFIFO [1/2]

#define LPUART_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPUART_PARAM_RXFIFO [2/2]

#define LPUART_PARAM_RXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

LPUART_PARAM_TXFIFO [1/2]

#define LPUART_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPUART_PARAM_TXFIFO [2/2]

#define LPUART_PARAM_TXFIFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

LPUART_VERID_FEATURE [1/2]

#define LPUART_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

LPUART_VERID_FEATURE [2/2]

#define LPUART_VERID_FEATURE

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

LPUART_VERID_MAJOR [1/2]

#define LPUART_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPUART_VERID_MAJOR [2/2]

#define LPUART_VERID_MAJOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

LPUART_VERID_MINOR [1/2]

#define LPUART_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number

LPUART_VERID_MINOR [2/2]

#define LPUART_VERID_MINOR

(

x

)

(((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number