RTEMS 6.1-rc5
Loading...
Searching...
No Matches
grlib_impl.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * Copyright (C) 2017 Cobham Gaisler AB
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#ifndef GRLIB_IMPL_H
29#define GRLIB_IMPL_H
30
32#include <rtems/malloc.h>
33
34/*
35 * Use interrupt lock primitives compatible with SMP defined in RTEMS 4.11.99
36 * and higher.
37 */
38#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x040b63)
39
40#include <rtems/score/isrlock.h>
41
42/* map via rtems_interrupt_lock_* API: */
43#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock)
44#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name)
45#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level)
46#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level)
47#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level)
48#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level)
49#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k
50#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k)
51#define SPIN_FREE(lock) rtems_interrupt_lock_destroy(lock)
52
53/* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */
54#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level
55#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_local_disable(_level)
56#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_local_enable(_level)
57
58#else
59
60#ifdef RTEMS_SMP
61#error SMP mode not compatible with these interrupt lock primitives
62#endif
63
64/* maintain single-core compatibility with older versions of RTEMS: */
65#define SPIN_DECLARE(name)
66#define SPIN_INIT(lock, name)
67#define SPIN_LOCK(lock, level)
68#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level)
69#define SPIN_UNLOCK(lock, level)
70#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level)
71#define SPIN_IRQFLAGS(k) rtems_interrupt_level k
72#define SPIN_ISR_IRQFLAGS(k)
73#define SPIN_FREE(lock)
74
75/* turn on/off local CPU's interrupt to ensure HW timing - not SMP safe. */
76#define IRQ_LOCAL_DECLARE(_level) rtems_interrupt_level _level
77#define IRQ_LOCAL_DISABLE(_level) rtems_interrupt_disable(_level)
78#define IRQ_LOCAL_ENABLE(_level) rtems_interrupt_enable(_level)
79
80#endif
81
82#ifdef __cplusplus
83extern "C" {
84#endif
85
86#if (((__RTEMS_MAJOR__ << 16) | (__RTEMS_MINOR__ << 8) | __RTEMS_REVISION__) >= 0x050000)
87
88static inline void *grlib_malloc(size_t size)
89{
90 return rtems_malloc(size);
91}
92
93static inline void *grlib_calloc(size_t nelem, size_t elsize)
94{
95 return rtems_calloc(nelem, elsize);
96}
97
98#else
99
100static inline void *grlib_malloc(size_t size)
101{
102 return malloc(size);
103}
104
105static inline void *grlib_calloc(size_t nelem, size_t elsize)
106{
107 return calloc(nelem, elsize);
108}
109
110#endif
111
112#ifdef __sparc__
113
114static inline unsigned char grlib_read_uncached8(unsigned int address)
115{
116 unsigned char tmp;
117 __asm__ (" lduba [%1]1, %0 "
118 : "=r"(tmp)
119 : "r"(address)
120 );
121 return tmp;
122}
123
124static inline unsigned short grlib_read_uncached16(unsigned int addr) {
125 unsigned short tmp;
126 __asm__ (" lduha [%1]1, %0 "
127 : "=r"(tmp)
128 : "r"(addr)
129 );
130 return tmp;
131}
132
133
134static inline unsigned int grlib_read_uncached32(unsigned int address)
135{
136 unsigned int tmp;
137 __asm__ (" lda [%1]1, %0 "
138 : "=r"(tmp)
139 : "r"(address)
140 );
141 return tmp;
142}
143
144static inline uint64_t grlib_read_uncached64(uint64_t *address)
145{
146 uint64_t tmp;
147 __asm__ (" ldda [%1]1, %0 "
148 : "=r"(tmp)
149 : "r"(address)
150 );
151 return tmp;
152}
153
154#define GRLIB_DMA_IS_CACHE_COHERENT CPU_SPARC_HAS_SNOOPING
155
156#else
157
158static unsigned char __inline__ grlib_read_uncached8(unsigned int address)
159{
160 unsigned char tmp = (*(volatile unsigned char *)(address));
161 return tmp;
162}
163
164static __inline__ unsigned short grlib_read_uncached16(unsigned int address) {
165 unsigned short tmp = (*(volatile unsigned short *)(address));
166 return tmp;
167}
168
169static inline unsigned int grlib_read_uncached32(unsigned int address)
170{
171 unsigned int tmp = (*(volatile unsigned int *)(address));
172 return tmp;
173}
174
175#define GRLIB_DMA_IS_CACHE_COHERENT 1
176
177#endif
178
179#ifdef __cplusplus
180}
181#endif
182
183#endif /* GRLIB_IMPL_H */
This header file provides basic definitions used by the API and the implementation.
void * rtems_malloc(size_t size) RTEMS_MALLOCLIKE RTEMS_ALLOC_SIZE(1) RTEMS_WARN_UNUSED_RESULT
Allocates a memory area of the specified size from the heap.
void * rtems_calloc(size_t nelem, size_t elsize) RTEMS_MALLOCLIKE RTEMS_ALLOC_SIZE_2(1
Allocates a memory area for the specified count of elements from the heap.
This header file provides the interfaces of the ISR Locks.
This header file defines interfaces to support and use dynamic memory allocation.