RTEMS 6.1-rc5
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Macros | Functions
ddr.c File Reference
Board Support Packages » AArch64 » AMD Zynq UltraScale+ MPSoC and RFSoC - Application Processing Unit

This source file contains the implementation of DDR ECC support. More...

#include <bsp.h>
#include <bsp/ecc_priv.h>
#include <bsp/irq.h>
#include <bsp/utility.h>
#include <rtems/rtems/intr.h>

Macros

#define DDRC_ADDRMAP_4BIT_SPECIAL   15
 
#define DDRC_ADDRMAP_5BIT_SPECIAL   31
 
#define DDRC_MSTR_OFFSET   0x0
 
#define DDRC_MSTR_BURST_RDWR(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_MSTR_BURST_RDWR_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_MSTR_BURST_RDWR_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_MSTR_BURST_RDWR_4   0x2
 
#define DDRC_MSTR_BURST_RDWR_8   0x4
 
#define DDRC_MSTR_BURST_RDWR_16   0x8
 
#define DDRC_MSTR_DATA_BUS_WIDTH(val)   BSP_FLD32(val, 12, 13)
 
#define DDRC_MSTR_DATA_BUS_WIDTH_GET(reg)   BSP_FLD32GET(reg, 12, 13)
 
#define DDRC_MSTR_DATA_BUS_WIDTH_SET(reg, val)   BSP_FLD32SET(reg, val, 12, 13)
 
#define DDRC_MSTR_DATA_BUS_WIDTH_FULL   0x0
 
#define DDRC_MSTR_DATA_BUS_WIDTH_HALF   0x1
 
#define DDRC_MSTR_DATA_BUS_WIDTH_QUARTER   0x2
 
#define DDRC_MSTR_LPDDR4   BSP_BIT32(5)
 
#define DDRC_MSTR_DDR4   BSP_BIT32(4)
 
#define DDRC_MSTR_LPDDR3   BSP_BIT32(3)
 
#define DDRC_MSTR_DDR3   BSP_BIT32(0)
 
#define DDRC_ADDRMAP0_OFFSET   0x200
 
#define DDRC_ADDRMAP0_RANK_B0_BASE   6
 
#define DDRC_ADDRMAP0_RANK_B0_TARGET_BIT(bw, lp3)   0
 
#define DDRC_ADDRMAP0_RANK_B0_TARGET   rank
 
#define DDRC_ADDRMAP0_RANK_B0_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP0_RANK_B0(val)   BSP_FLD32(val, 0, 4)
 
#define DDRC_ADDRMAP0_RANK_B0_GET(reg)   BSP_FLD32GET(reg, 0, 4)
 
#define DDRC_ADDRMAP0_RANK_B0_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 4)
 
#define DDRC_ADDRMAP1_OFFSET   0x204
 
#define DDRC_ADDRMAP1_BANK_B2_BASE   4
 
#define DDRC_ADDRMAP1_BANK_B2_TARGET_BIT(bw, lp3)   2
 
#define DDRC_ADDRMAP1_BANK_B2_TARGET   bank
 
#define DDRC_ADDRMAP1_BANK_B2_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP1_BANK_B2(val)   BSP_FLD32(val, 16, 20)
 
#define DDRC_ADDRMAP1_BANK_B2_GET(reg)   BSP_FLD32GET(reg, 16, 20)
 
#define DDRC_ADDRMAP1_BANK_B2_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 20)
 
#define DDRC_ADDRMAP1_BANK_B1_BASE   3
 
#define DDRC_ADDRMAP1_BANK_B1_TARGET_BIT(bw, lp3)   1
 
#define DDRC_ADDRMAP1_BANK_B1_TARGET   bank
 
#define DDRC_ADDRMAP1_BANK_B1_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP1_BANK_B1(val)   BSP_FLD32(val, 8, 12)
 
#define DDRC_ADDRMAP1_BANK_B1_GET(reg)   BSP_FLD32GET(reg, 8, 12)
 
#define DDRC_ADDRMAP1_BANK_B1_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 12)
 
#define DDRC_ADDRMAP1_BANK_B0_BASE   2
 
#define DDRC_ADDRMAP1_BANK_B0_TARGET_BIT(bw, lp3)   0
 
#define DDRC_ADDRMAP1_BANK_B0_TARGET   bank
 
#define DDRC_ADDRMAP1_BANK_B0_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP1_BANK_B0(val)   BSP_FLD32(val, 0, 4)
 
#define DDRC_ADDRMAP1_BANK_B0_GET(reg)   BSP_FLD32GET(reg, 0, 4)
 
#define DDRC_ADDRMAP1_BANK_B0_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 4)
 
#define DDRC_ADDRMAP2_OFFSET   0x208
 
#define DDRC_ADDRMAP2_COL_B5_BASE   5
 
#define DDRC_ADDRMAP2_COL_B5_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP2_COL_B5_TARGET   column
 
#define DDRC_ADDRMAP2_COL_B5_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP2_COL_B5(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP2_COL_B5_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP2_COL_B5_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP2_COL_B4_BASE   4
 
#define DDRC_ADDRMAP2_COL_B4_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP2_COL_B4_TARGET   column
 
#define DDRC_ADDRMAP2_COL_B4_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP2_COL_B4(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP2_COL_B4_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP2_COL_B4_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP2_COL_B3_BASE   3
 
#define DDRC_ADDRMAP2_COL_B3_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP2_COL_B3_TARGET   column
 
#define DDRC_ADDRMAP2_COL_B3_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP2_COL_B3(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP2_COL_B3_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP2_COL_B3_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP2_COL_B2_BASE   2
 
#define DDRC_ADDRMAP2_COL_B2_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP2_COL_B2_TARGET   column
 
#define DDRC_ADDRMAP2_COL_B2_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP2_COL_B2(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP2_COL_B2_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP2_COL_B2_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP3_OFFSET   0x20c
 
#define DDRC_ADDRMAP3_COL_B9_BASE   9
 
#define DDRC_ADDRMAP3_COL_B9_TARGET_BIT(bw, lp3)    map3_col_b9_target_bit(bw, lp3)
 
#define DDRC_ADDRMAP3_COL_B9_TARGET   column
 
#define DDRC_ADDRMAP3_COL_B9_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP3_COL_B9(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP3_COL_B9_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP3_COL_B9_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP3_COL_B8_BASE   8
 
#define DDRC_ADDRMAP3_COL_B8_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP3_COL_B8_TARGET   column
 
#define DDRC_ADDRMAP3_COL_B8_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP3_COL_B8(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP3_COL_B8_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP3_COL_B8_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP3_COL_B7_BASE   7
 
#define DDRC_ADDRMAP3_COL_B7_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP3_COL_B7_TARGET   column
 
#define DDRC_ADDRMAP3_COL_B7_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP3_COL_B7(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP3_COL_B7_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP3_COL_B7_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP3_COL_B6_BASE   6
 
#define DDRC_ADDRMAP3_COL_B6_TARGET_BIT(bw, lp3)
 
#define DDRC_ADDRMAP3_COL_B6_TARGET   column
 
#define DDRC_ADDRMAP3_COL_B6_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP3_COL_B6(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP3_COL_B6_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP3_COL_B6_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP4_OFFSET   0x210
 
#define DDRC_ADDRMAP4_COL_B11_BASE   11
 
#define DDRC_ADDRMAP4_COL_B11_TARGET_BIT(bw, lp3)    (lp3?11:13)
 
#define DDRC_ADDRMAP4_COL_B11_TARGET   column
 
#define DDRC_ADDRMAP4_COL_B11_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP4_COL_B11(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP4_COL_B11_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP4_COL_B11_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP4_COL_B10_BASE   10
 
#define DDRC_ADDRMAP4_COL_B10_TARGET_BIT(bw, lp3)    map4_col_b10_target_bit(bw, lp3)
 
#define DDRC_ADDRMAP4_COL_B10_TARGET   column
 
#define DDRC_ADDRMAP4_COL_B10_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP4_COL_B10(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP4_COL_B10_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP4_COL_B10_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP5_OFFSET   0x214
 
#define DDRC_ADDRMAP5_ROW_B11_BASE   17
 
#define DDRC_ADDRMAP5_ROW_B11_TARGET_BIT(bw, lp3)   11
 
#define DDRC_ADDRMAP5_ROW_B11_TARGET   row
 
#define DDRC_ADDRMAP5_ROW_B11_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP5_ROW_B11(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP5_ROW_B11_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP5_ROW_B11_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP5_ROW_B2_10(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP5_ROW_B2_10_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP5_ROW_B2_10_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP5_ROW_B1_BASE   7
 
#define DDRC_ADDRMAP5_ROW_B1_TARGET_BIT(bw, lp3)   1
 
#define DDRC_ADDRMAP5_ROW_B1_TARGET   row
 
#define DDRC_ADDRMAP5_ROW_B1_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP5_ROW_B1(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP5_ROW_B1_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP5_ROW_B1_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP5_ROW_B0_BASE   6
 
#define DDRC_ADDRMAP5_ROW_B0_TARGET_BIT(bw, lp3)   0
 
#define DDRC_ADDRMAP5_ROW_B0_TARGET   row
 
#define DDRC_ADDRMAP5_ROW_B0_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP5_ROW_B0(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP5_ROW_B0_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP5_ROW_B0_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP6_OFFSET   0x218
 
#define DDRC_ADDRMAP6_LPDDR3_6_12   BSP_BIT(bw, lp3)32(31)
 
#define DDRC_ADDRMAP6_ROW_B15_BASE   21
 
#define DDRC_ADDRMAP6_ROW_B15_TARGET_BIT(bw, lp3)   15
 
#define DDRC_ADDRMAP6_ROW_B15_TARGET   row
 
#define DDRC_ADDRMAP6_ROW_B15_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP6_ROW_B15(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP6_ROW_B15_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP6_ROW_B15_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP6_ROW_B14_BASE   20
 
#define DDRC_ADDRMAP6_ROW_B14_TARGET_BIT(bw, lp3)   14
 
#define DDRC_ADDRMAP6_ROW_B14_TARGET   row
 
#define DDRC_ADDRMAP6_ROW_B14_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP6_ROW_B14(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP6_ROW_B14_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP6_ROW_B14_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP6_ROW_B13_BASE   19
 
#define DDRC_ADDRMAP6_ROW_B13_TARGET_BIT(bw, lp3)   13
 
#define DDRC_ADDRMAP6_ROW_B13_TARGET   row
 
#define DDRC_ADDRMAP6_ROW_B13_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP6_ROW_B13(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP6_ROW_B13_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP6_ROW_B13_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP6_ROW_B12_BASE   18
 
#define DDRC_ADDRMAP6_ROW_B12_TARGET_BIT(bw, lp3)   12
 
#define DDRC_ADDRMAP6_ROW_B12_TARGET   row
 
#define DDRC_ADDRMAP6_ROW_B12_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP6_ROW_B12(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP6_ROW_B12_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP6_ROW_B12_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP7_OFFSET   0x21c
 
#define DDRC_ADDRMAP7_ROW_B17_BASE   23
 
#define DDRC_ADDRMAP7_ROW_B17_TARGET_BIT(bw, lp3)   17
 
#define DDRC_ADDRMAP7_ROW_B17_TARGET   row
 
#define DDRC_ADDRMAP7_ROW_B17_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP7_ROW_B17(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP7_ROW_B17_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP7_ROW_B17_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP7_ROW_B16_BASE   22
 
#define DDRC_ADDRMAP7_ROW_B16_TARGET_BIT(bw, lp3)   16
 
#define DDRC_ADDRMAP7_ROW_B16_TARGET   row
 
#define DDRC_ADDRMAP7_ROW_B16_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP7_ROW_B16(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP7_ROW_B16_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP7_ROW_B16_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP8_OFFSET   0x220
 
#define DDRC_ADDRMAP8_BG_B1_BASE   3
 
#define DDRC_ADDRMAP8_BG_B1_TARGET_BIT(bw, lp3)   1
 
#define DDRC_ADDRMAP8_BG_B1_TARGET   bank_group
 
#define DDRC_ADDRMAP8_BG_B1_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP8_BG_B1(val)   BSP_FLD32(val, 8, 12)
 
#define DDRC_ADDRMAP8_BG_B1_GET(reg)   BSP_FLD32GET(reg, 8, 12)
 
#define DDRC_ADDRMAP8_BG_B1_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 12)
 
#define DDRC_ADDRMAP8_BG_B0_BASE   2
 
#define DDRC_ADDRMAP8_BG_B0_TARGET_BIT(bw, lp3)   0
 
#define DDRC_ADDRMAP8_BG_B0_TARGET   bank_group
 
#define DDRC_ADDRMAP8_BG_B0_SPECIAL   DDRC_ADDRMAP_5BIT_SPECIAL
 
#define DDRC_ADDRMAP8_BG_B0(val)   BSP_FLD32(val, 0, 4)
 
#define DDRC_ADDRMAP8_BG_B0_GET(reg)   BSP_FLD32GET(reg, 0, 4)
 
#define DDRC_ADDRMAP8_BG_B0_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 4)
 
#define DDRC_ADDRMAP9_OFFSET   0x224
 
#define DDRC_ADDRMAP9_ROW_B5_BASE   11
 
#define DDRC_ADDRMAP9_ROW_B5_TARGET_BIT(bw, lp3)   5
 
#define DDRC_ADDRMAP9_ROW_B5_TARGET   row
 
#define DDRC_ADDRMAP9_ROW_B5_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP9_ROW_B5(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP9_ROW_B5_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP9_ROW_B5_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP9_ROW_B4_BASE   10
 
#define DDRC_ADDRMAP9_ROW_B4_TARGET_BIT(bw, lp3)   4
 
#define DDRC_ADDRMAP9_ROW_B4_TARGET   row
 
#define DDRC_ADDRMAP9_ROW_B4_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP9_ROW_B4(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP9_ROW_B4_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP9_ROW_B4_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP9_ROW_B3_BASE   9
 
#define DDRC_ADDRMAP9_ROW_B3_TARGET_BIT(bw, lp3)   3
 
#define DDRC_ADDRMAP9_ROW_B3_TARGET   row
 
#define DDRC_ADDRMAP9_ROW_B3_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP9_ROW_B3(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP9_ROW_B3_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP9_ROW_B3_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP9_ROW_B2_BASE   8
 
#define DDRC_ADDRMAP9_ROW_B2_TARGET_BIT(bw, lp3)   2
 
#define DDRC_ADDRMAP9_ROW_B2_TARGET   row
 
#define DDRC_ADDRMAP9_ROW_B2_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP9_ROW_B2(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP9_ROW_B2_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP9_ROW_B2_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP10_OFFSET   0x228
 
#define DDRC_ADDRMAP10_ROW_B9_BASE   15
 
#define DDRC_ADDRMAP10_ROW_B9_TARGET_BIT(bw, lp3)   9
 
#define DDRC_ADDRMAP10_ROW_B9_TARGET   row
 
#define DDRC_ADDRMAP10_ROW_B9_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP10_ROW_B9(val)   BSP_FLD32(val, 24, 27)
 
#define DDRC_ADDRMAP10_ROW_B9_GET(reg)   BSP_FLD32GET(reg, 24, 27)
 
#define DDRC_ADDRMAP10_ROW_B9_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 27)
 
#define DDRC_ADDRMAP10_ROW_B8_BASE   14
 
#define DDRC_ADDRMAP10_ROW_B8_TARGET_BIT(bw, lp3)   8
 
#define DDRC_ADDRMAP10_ROW_B8_TARGET   row
 
#define DDRC_ADDRMAP10_ROW_B8_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP10_ROW_B8(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ADDRMAP10_ROW_B8_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ADDRMAP10_ROW_B8_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ADDRMAP10_ROW_B7_BASE   13
 
#define DDRC_ADDRMAP10_ROW_B7_TARGET_BIT(bw, lp3)   7
 
#define DDRC_ADDRMAP10_ROW_B7_TARGET   row
 
#define DDRC_ADDRMAP10_ROW_B7_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP10_ROW_B7(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ADDRMAP10_ROW_B7_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ADDRMAP10_ROW_B7_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ADDRMAP10_ROW_B6_BASE   12
 
#define DDRC_ADDRMAP10_ROW_B6_TARGET_BIT(bw, lp3)   6
 
#define DDRC_ADDRMAP10_ROW_B6_TARGET   row
 
#define DDRC_ADDRMAP10_ROW_B6_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP10_ROW_B6(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP10_ROW_B6_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP10_ROW_B6_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ADDRMAP11_OFFSET   0x22c
 
#define DDRC_ADDRMAP11_ROW_B10_BASE   16
 
#define DDRC_ADDRMAP11_ROW_B10_TARGET_BIT(bw, lp3)   10
 
#define DDRC_ADDRMAP11_ROW_B10_TARGET   row
 
#define DDRC_ADDRMAP11_ROW_B10_SPECIAL   DDRC_ADDRMAP_4BIT_SPECIAL
 
#define DDRC_ADDRMAP11_ROW_B10(val)   BSP_FLD32(val, 0, 3)
 
#define DDRC_ADDRMAP11_ROW_B10_GET(reg)   BSP_FLD32GET(reg, 0, 3)
 
#define DDRC_ADDRMAP11_ROW_B10_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 3)
 
#define DDRC_ECCPOISONADDR0_OFFSET   0xB8
 
#define DDRC_ECCPOISONADDR0_RANK   BSP_BIT32(24)
 
#define DDRC_ECCPOISONADDR0_COL(val)   BSP_FLD32(val, 0, 11)
 
#define DDRC_ECCPOISONADDR0_COL_GET(reg)   BSP_FLD32GET(reg, 0, 11)
 
#define DDRC_ECCPOISONADDR0_COL_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 11)
 
#define DDRC_ECCPOISONADDR1_OFFSET   0xBC
 
#define DDRC_ECCPOISONADDR1_BG(val)   BSP_FLD32(val, 28, 29)
 
#define DDRC_ECCPOISONADDR1_BG_GET(reg)   BSP_FLD32GET(reg, 28, 29)
 
#define DDRC_ECCPOISONADDR1_BG_SET(reg, val)   BSP_FLD32SET(reg, val, 28, 29)
 
#define DDRC_ECCPOISONADDR1_BANK(val)   BSP_FLD32(val, 24, 26)
 
#define DDRC_ECCPOISONADDR1_BANK_GET(reg)   BSP_FLD32GET(reg, 24, 26)
 
#define DDRC_ECCPOISONADDR1_BANK_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 26)
 
#define DDRC_ECCPOISONADDR1_ROW(val)   BSP_FLD32(val, 0, 17)
 
#define DDRC_ECCPOISONADDR1_ROW_GET(reg)   BSP_FLD32GET(reg, 0, 17)
 
#define DDRC_ECCPOISONADDR1_ROW_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 17)
 
#define DDRC_READ(offset)   (*(uint32_t *)(ddrc_base + offset))
 
#define DDRC_MAP_BIT(value, source, target)   ((value >> source) & 0x1) << target
 
#define DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, BIT_ID, info, addrmap)
 
#define DDR_QIS_OFFSET   0x200
 
#define DDR_QIE_OFFSET   0x208
 
#define DDR_QID_OFFSET   0x20c
 
#define DDR_QI_UNCRERR   BSP_BIT32(2)
 
#define DDR_QI_CORERR   BSP_BIT32(1)
 
#define DDRC_ECCSTAT_OFFSET   0x78
 
#define DDRC_ECCSTAT_UNCR_ERR(val)   BSP_FLD32(val, 16, 19)
 
#define DDRC_ECCSTAT_UNCR_ERR_GET(reg)   BSP_FLD32GET(reg, 16, 19)
 
#define DDRC_ECCSTAT_UNCR_ERR_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 19)
 
#define DDRC_ECCSTAT_CORR_ERR(val)   BSP_FLD32(val, 8, 11)
 
#define DDRC_ECCSTAT_CORR_ERR_GET(reg)   BSP_FLD32GET(reg, 8, 11)
 
#define DDRC_ECCSTAT_CORR_ERR_SET(reg, val)   BSP_FLD32SET(reg, val, 8, 11)
 
#define DDRC_ECCSTAT_CORR_BIT(val)   BSP_FLD32(val, 0, 6)
 
#define DDRC_ECCSTAT_CORR_BIT_GET(reg)   BSP_FLD32GET(reg, 0, 6)
 
#define DDRC_ECCSTAT_CORR_BIT_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 6)
 
#define DDRC_ECCCADDR0_OFFSET   0x84
 
#define DDRC_ECCUADDR0_OFFSET   0xA4
 
#define DDRC_ECCXADDR0_RANK   BSP_BIT32(24)
 
#define DDRC_ECCXADDR0_ROW(val)   BSP_FLD32(val, 0, 17)
 
#define DDRC_ECCXADDR0_ROW_GET(reg)   BSP_FLD32GET(reg, 0, 17)
 
#define DDRC_ECCXADDR0_ROW_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 17)
 
#define DDRC_ECCCADDR1_OFFSET   0x88
 
#define DDRC_ECCUADDR1_OFFSET   0xA8
 
#define DDRC_ECCXADDR1_BG(val)   BSP_FLD32(val, 24, 25)
 
#define DDRC_ECCXADDR1_BG_GET(reg)   BSP_FLD32GET(reg, 24, 25)
 
#define DDRC_ECCXADDR1_BG_SET(reg, val)   BSP_FLD32SET(reg, val, 24, 25)
 
#define DDRC_ECCXADDR1_BANK(val)   BSP_FLD32(val, 16, 18)
 
#define DDRC_ECCXADDR1_BANK_GET(reg)   BSP_FLD32GET(reg, 16, 18)
 
#define DDRC_ECCXADDR1_BANK_SET(reg, val)   BSP_FLD32SET(reg, val, 16, 18)
 
#define DDRC_ECCXADDR1_COL(val)   BSP_FLD32(val, 0, 11)
 
#define DDRC_ECCXADDR1_COL_GET(reg)   BSP_FLD32GET(reg, 0, 11)
 
#define DDRC_ECCXADDR1_COL_SET(reg, val)   BSP_FLD32SET(reg, val, 0, 11)
 

Functions

rtems_status_code zynqmp_configure_ddr_ecc (void)
 Configure DDR Memory ECC reporting.
 

Detailed Description

This source file contains the implementation of DDR ECC support.

Macro Definition Documentation

◆ DDRC_ADDRMAP2_COL_B2_TARGET_BIT

#define DDRC_ADDRMAP2_COL_B2_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
2 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 3 : 4))

◆ DDRC_ADDRMAP2_COL_B3_TARGET_BIT

#define DDRC_ADDRMAP2_COL_B3_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
3 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 4 : 5 ))

◆ DDRC_ADDRMAP2_COL_B4_TARGET_BIT

#define DDRC_ADDRMAP2_COL_B4_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
4 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 5 : 6))

◆ DDRC_ADDRMAP2_COL_B5_TARGET_BIT

#define DDRC_ADDRMAP2_COL_B5_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
5 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 6 : 7))

◆ DDRC_ADDRMAP3_COL_B6_TARGET_BIT

#define DDRC_ADDRMAP3_COL_B6_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
6 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 7 : 8))

◆ DDRC_ADDRMAP3_COL_B7_TARGET_BIT

#define DDRC_ADDRMAP3_COL_B7_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
7 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 8 : 9))

◆ DDRC_ADDRMAP3_COL_B8_TARGET_BIT

#define DDRC_ADDRMAP3_COL_B8_TARGET_BIT (   bw,
  lp3 
)
Value:
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
8 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 9 : 11))

◆ DDRC_CHECK_AND_UNMAP

#define DDRC_CHECK_AND_UNMAP (   bus_width,
  lpddr3,
  BIT_ID,
  info,
  addrmap 
)
Value:
({ \
uint32_t mapbit = DDRC_ ## BIT_ID ## _GET(addrmap); \
uint32_t target_bit = DDRC_ ## BIT_ID ## _TARGET_BIT(bus_width, lpddr3); \
if (mapbit != DDRC_ ## BIT_ID ## _SPECIAL) { \
mapbit += DDRC_ ## BIT_ID ## _BASE; \
/* account for AXI -> HIF shift */ \
mapbit += 3; \
info->address |= \
DDRC_MAP_BIT(info-> DDRC_ ## BIT_ID ## _TARGET, target_bit, mapbit); \
} \
})
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