RTEMS 6.1-rc5
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Data Structures | Macros
fsl_clock.h File Reference
Clock
#include "fsl_common.h"

Go to the source code of this file.

Data Structures

struct  _clock_group_config
 The structure used to configure clock group. More...
 
struct  _clock_arm_pll_config
 PLL configuration for ARM. More...
 
struct  _clock_usb_pll_config
 PLL configuration for USB. More...
 
struct  _clock_pll_ss_config
 Spread specturm configure Pll. More...
 
struct  _clock_sys_pll2_config
 PLL configure for Sys Pll2. More...
 
struct  _clock_sys_pll1_config
 PLL configure for Sys Pll1. More...
 
struct  _clock_audio_pll_config
 PLL configuration for AUDIO and VIDEO. More...
 
struct  _clock_audio_pll_gpc_config
 PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. More...
 
struct  _clock_enet_pll_config
 PLL configuration for ENET. More...
 
struct  _clock_root_config_t
 Clock root configuration. More...
 
struct  _clock_root_setpoint_config_t
 Clock root configuration in SetPoint Mode. More...
 

Macros

#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL   0
 Configure whether driver controls clock.
 

Functions

Driver version
uint32_t CLOCK_GetFreq (clock_name_t name)
 Gets the clock frequency for a specific clock name.
 
OSC operations
void CLOCK_OSC_EnableOsc24M (void)
 Enable OSC 24Mhz.
 
void CLOCK_OSC_SetOsc24MWorkMode (clock_24MOsc_mode_t workMode)
 Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and bypass mode.
 
void CLOCK_OSC_EnableOscRc400M (void)
 Enable OSC RC 400Mhz.
 
void CLOCK_OSC_TrimOscRc400M (bool enable, bool bypass, uint16_t trim)
 Trims OSC RC 400MHz.
 
void CLOCK_OSC_SetOscRc400MRefClkDiv (uint8_t divValue)
 Set the divide value for ref_clk to generate slow clock.
 
void CLOCK_OSC_SetOscRc400MFastClkCount (uint16_t targetCount)
 Set the target count for the fast clock.
 
void CLOCK_OSC_SetOscRc400MHysteresisValue (uint8_t negHysteresis, uint8_t posHysteresis)
 Set the negative and positive hysteresis value for the tuned clock.
 
void CLOCK_OSC_BypassOscRc400MTuneLogic (bool enableBypass)
 Bypass/un-bypass the tune logic.
 
void CLOCK_OSC_EnableOscRc400MTuneLogic (bool enable)
 Start/Stop the tune logic.
 
void CLOCK_OSC_FreezeOscRc400MTuneValue (bool enableFreeze)
 Freeze/Unfreeze the tuning value.
 
void CLOCK_OSC_SetOscRc400MTuneValue (uint8_t tuneValue)
 Set the 400MHz RC oscillator tune value when the tune logic is disabled.
 
void CLOCK_OSC_Set1MHzOutputBehavior (clock_1MHzOut_behavior_t behavior)
 Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, enable the free-running 1MHz clock output, enable the locked 1MHz clock output.
 
void CLOCK_OSC_SetLocked1MHzCount (uint16_t count)
 Set the count for the locked 1MHz clock out.
 
bool CLOCK_OSC_CheckLocked1MHzErrorFlag (void)
 Check the error flag for locked 1MHz clock out.
 
void CLOCK_OSC_ClearLocked1MHzErrorFlag (void)
 Clear the error flag for locked 1MHz clock out.
 
uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount (void)
 Get current count for the fast clock during the tune process.
 
uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue (void)
 Get current tune value used by oscillator during tune process.
 
void CLOCK_OSC_SetOsc16MConfig (clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut)
 Configure the 16MHz oscillator.
 
status_t CLOCK_CalcArmPllFreq (clock_arm_pll_config_t *config, uint32_t freqInMhz)
 Calculate corresponding config values per given frequency.
 
status_t CLOCK_InitArmPllWithFreq (uint32_t freqInMhz)
 Initializes the Arm PLL with Specific Frequency (in Mhz).
 
void CLOCK_CalcPllSpreadSpectrum (uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss)
 Calculate spread spectrum step and stop.
 
void CLOCK_InitSysPll1 (const clock_sys_pll1_config_t *config)
 Initialize the System PLL1.
 
void CLOCK_DeinitSysPll1 (void)
 De-initialize the System PLL1.
 
void CLOCK_GPC_SetSysPll1OutputFreq (const clock_sys_pll1_gpc_config_t *config)
 Set System PLL1 output frequency in GPC mode.
 
void CLOCK_InitSysPll2 (const clock_sys_pll2_config_t *config)
 Initialize the System PLL2.
 
void CLOCK_DeinitSysPll2 (void)
 De-initialize the System PLL2.
 
bool CLOCK_IsSysPll2PfdEnabled (clock_pfd_t pfd)
 Check if Sys PLL2 PFD is enabled.
 
void CLOCK_InitSysPll3 (void)
 Initialize the System PLL3.
 
void CLOCK_DeinitSysPll3 (void)
 De-initialize the System PLL3.
 
bool CLOCK_IsSysPll3PfdEnabled (clock_pfd_t pfd)
 Check if Sys PLL3 PFD is enabled.
 
PLL/PFD operations
void CLOCK_InitArmPll (const clock_arm_pll_config_t *config)
 Initialize the ARM PLL.
 
void CLOCK_DeinitArmPll (void)
 De-initialize the ARM PLL.
 
void CLOCK_InitAudioPll (const clock_audio_pll_config_t *config)
 Initializes the Audio PLL.
 
void CLOCK_DeinitAudioPll (void)
 De-initialize the Audio PLL.
 
void CLOCK_InitVideoPll (const clock_video_pll_config_t *config)
 Initialize the video PLL.
 
void CLOCK_DeinitVideoPll (void)
 De-initialize the Video PLL.
 
uint32_t CLOCK_GetPllFreq (clock_pll_t pll)
 Get current PLL output frequency.
 
bool CLOCK_EnableUsbhs0PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock.
 
void CLOCK_DisableUsbhs0PhyPllClock (void)
 Disable USB HS PHY PLL clock.
 
bool CLOCK_EnableUsbhs1PhyPllClock (clock_usb_phy_src_t src, uint32_t freq)
 Enable USB HS PHY PLL clock.
 
void CLOCK_DisableUsbhs1PhyPllClock (void)
 Disable USB HS PHY PLL clock.
 
PLL/PFD operations
void CLOCK_SetPllBypass (clock_pll_t pll, bool bypass)
 PLL bypass setting.
 
status_t CLOCK_CalcAvPllFreq (clock_av_pll_config_t *config, uint32_t freqInMhz)
 Calculate corresponding config values per given frequency.
 
status_t CLOCK_InitAudioPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
 Initializes the Audio PLL with Specific Frequency (in Mhz).
 
void CLOCK_GPC_SetAudioPllOutputFreq (const clock_audio_pll_gpc_config_t *config)
 Set Audio PLL output frequency in GPC mode.
 
status_t CLOCK_InitVideoPllWithFreq (uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod)
 Initializes the Video PLL with Specific Frequency (in Mhz).
 
void CLOCK_GPC_SetVideoPllOutputFreq (const clock_video_pll_gpc_config_t *config)
 Set Video PLL output frequency in GPC mode.
 
void CLOCK_InitPfd (clock_pll_t pll, clock_pfd_t pfd, uint8_t frac)
 Initialize PLL PFD.
 
void CLOCK_DeinitPfd (clock_pll_t pll, clock_pfd_t pfd)
 De-initialize selected PLL PFD.
 
uint32_t CLOCK_GetPfdFreq (clock_pll_t pll, clock_pfd_t pfd)
 Get current PFD output frequency.
 
uint32_t CLOCK_GetFreqFromObs (uint32_t obsSigIndex, uint32_t obsIndex)
 
void CLOCK_OSCPLL_ControlBySetPointMode (clock_name_t name, uint16_t spValue, uint16_t stbyValue)
 Set this clock works in SetPoint control Mode.
 
void CLOCK_OSCPLL_ControlByCpuLowPowerMode (clock_name_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
 Set this clock works in CPU Low Power Mode.
 
void CLOCK_ROOT_ControlBySetPointMode (clock_root_t name, const clock_root_setpoint_config_t *spTable)
 Set this clock works in SetPoint controlled Mode.
 
void CLOCK_LPCG_ControlBySetPointMode (clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue)
 Set this clock works in SetPoint control Mode.
 
void CLOCK_LPCG_ControlByCpuLowPowerMode (clock_lpcg_t name, uint8_t domainId, clock_level_t level0, clock_level_t level1)
 Set this clock works in CPU Low Power Mode.
 
OSC operations
bool CLOCK_EnableUsbhs0Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock.
 
bool CLOCK_EnableUsbhs1Clock (clock_usb_src_t src, uint32_t freq)
 Enable USB HS clock.
 

Driver version

#define FSL_CLOCK_DRIVER_VERSION   (MAKE_VERSION(2, 1, 2))
 CLOCK driver version.
 
#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY   (240000000UL)
 
#define CCSR_OFFSET   0x0C
 CCM registers offset.
 
#define CBCDR_OFFSET   0x14
 
#define CBCMR_OFFSET   0x18
 
#define CSCMR1_OFFSET   0x1C
 
#define CSCMR2_OFFSET   0x20
 
#define CSCDR1_OFFSET   0x24
 
#define CDCDR_OFFSET   0x30
 
#define CSCDR2_OFFSET   0x38
 
#define CSCDR3_OFFSET   0x3C
 
#define CACRR_OFFSET   0x10
 
#define CS1CDR_OFFSET   0x28
 
#define CS2CDR_OFFSET   0x2C
 
#define ARM_PLL_OFFSET   0x00
 CCM Analog registers offset.
 
#define PLL_SYS_OFFSET   0x30
 
#define PLL_USB1_OFFSET   0x10
 
#define PLL_AUDIO_OFFSET   0x70
 
#define PLL_VIDEO_OFFSET   0xA0
 
#define PLL_ENET_OFFSET   0xE0
 
#define PLL_USB2_OFFSET   0x20
 
#define CCM_TUPLE(reg, shift, mask, busyShift)    (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
 
#define CCM_TUPLE_REG(base, tuple)   (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
 
#define CCM_TUPLE_SHIFT(tuple)   (((tuple) >> 8U) & 0x1FU)
 
#define CCM_TUPLE_MASK(tuple)   ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
 
#define CCM_TUPLE_BUSY_SHIFT(tuple)   (((tuple) >> 26U) & 0x3FU)
 
#define CCM_BUSY_WAIT   (0x20U)
 
#define CCM_ANALOG_TUPLE(reg, shift)   (((reg & 0xFFFU) << 16U) | (shift))
 CCM ANALOG tuple macros to map corresponding registers and bit fields.
 
#define CCM_ANALOG_TUPLE_SHIFT(tuple)   (((uint32_t)tuple) & 0x1FU)
 
#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off)    (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
 
#define CCM_ANALOG_TUPLE_REG(base, tuple)   CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
 
#define SYS_PLL1_FREQ   (1000000000UL)
 SYS_PLL_FREQ frequency in Hz.
 
#define SYS_PLL2_MFI   (22UL)
 
#define SYS_PLL2_FREQ   (XTAL_FREQ * SYS_PLL2_MFI)
 
#define SYS_PLL3_MFI   (20UL)
 
#define SYS_PLL3_FREQ   (XTAL_FREQ * SYS_PLL3_MFI)
 
#define XTAL_FREQ   (24000000UL)
 
#define LPADC_CLOCKS
 Clock gate name array for ADC.
 
#define ADC_ETC_CLOCKS
 Clock gate name array for ADC.
 
#define AOI_CLOCKS
 Clock gate name array for AOI.
 
#define DCDC_CLOCKS
 Clock gate name array for DCDC.
 
#define SRC_CLOCKS
 Clock gate name array for SRC.
 
#define GPC_CLOCKS
 Clock gate name array for GPC.
 
#define SSARC_CLOCKS
 Clock gate name array for SSARC.
 
#define WDOG_CLOCKS
 Clock gate name array for WDOG.
 
#define EWM_CLOCKS
 Clock gate name array for EWM.
 
#define SEMA_CLOCKS
 Clock gate name array for Sema.
 
#define MU_CLOCKS
 Clock gate name array for MU.
 
#define EDMA_CLOCKS
 Clock gate name array for EDMA.
 
#define FLEXRAM_CLOCKS
 Clock gate name array for FLEXRAM.
 
#define LMEM_CLOCKS
 Clock gate name array for LMEM.
 
#define FLEXSPI_CLOCKS
 Clock gate name array for FLEXSPI.
 
#define RDC_CLOCKS
 Clock gate name array for RDC.
 
#define DCDC_CLOCKS
 Clock gate name array for DCDC.
 
#define SEMC_CLOCKS
 Clock ip name array for SEMC.
 
#define XECC_CLOCKS
 Clock ip name array for XECC.
 
#define IEE_CLOCKS
 Clock ip name array for IEE.
 
#define KEYMANAGER_CLOCKS
 Clock ip name array for KEY_MANAGER.
 
#define PUF_CLOCKS
 Clock ip name array for PUF.
 
#define OCOTP_CLOCKS
 Clock ip name array for OCOTP.
 
#define CAAM_CLOCKS
 Clock ip name array for CAAM.
 
#define XBAR_CLOCKS
 Clock ip name array for XBAR.
 
#define IOMUXC_CLOCKS
 Clock ip name array for IOMUXC.
 
#define GPIO_CLOCKS
 Clock ip name array for GPIO.
 
#define KPP_CLOCKS
 Clock ip name array for KPP.
 
#define FLEXIO_CLOCKS
 Clock ip name array for FLEXIO.
 
#define DAC_CLOCKS
 Clock ip name array for DAC.
 
#define CMP_CLOCKS
 Clock ip name array for CMP.
 
#define PIT_CLOCKS
 Clock ip name array for PIT.
 
#define GPT_CLOCKS
 Clock ip name array for GPT.
 
#define TMR_CLOCKS
 Clock ip name array for QTIMER.
 
#define ENC_CLOCKS
 Clock ip name array for ENC.
 
#define PWM_CLOCKS
 Clock ip name array for PWM.
 
#define FLEXCAN_CLOCKS
 Clock ip name array for FLEXCAN.
 
#define LPUART_CLOCKS
 Clock ip name array for LPUART.
 
#define LPI2C_CLOCKS
 Clock ip name array for LPI2C.
 
#define LPSPI_CLOCKS
 Clock ip name array for LPSPI.
 
#define EMVSIM_CLOCKS
 Clock ip name array for EMVSIM.
 
#define ENET_CLOCKS
 Clock ip name array for ENET.
 
#define USB_CLOCKS
 Clock ip name array for USB.
 
#define CDOG_CLOCKS
 Clock ip name array for CDOG.
 
#define USDHC_CLOCKS
 Clock ip name array for USDHC.
 
#define ASRC_CLOCKS
 Clock ip name array for ASRC.
 
#define MQS_CLOCKS
 Clock ip name array for MQS.
 
#define PDM_CLOCKS
 Clock ip name array for PDM.
 
#define SPDIF_CLOCKS
 Clock ip name array for SPDIF.
 
#define SAI_CLOCKS
 Clock ip name array for SAI.
 
#define PXP_CLOCKS
 Clock ip name array for PXP.
 
#define GPU2D_CLOCKS
 Clock ip name array for GPU2d.
 
#define LCDIF_CLOCKS
 Clock ip name array for LCDIF.
 
#define LCDIFV2_CLOCKS
 Clock ip name array for LCDIFV2.
 
#define MIPI_DSI_HOST_CLOCKS
 Clock ip name array for MIPI_DSI.
 
#define MIPI_CSI2RX_CLOCKS
 Clock ip name array for MIPI_CSI.
 
#define CSI_CLOCKS
 Clock ip name array for CSI.
 
#define DCIC_CLOCKS
 Clock ip name array for DCIC.
 
#define DMAMUX_CLOCKS
 Clock ip name array for DMAMUX_CLOCKS.
 
#define XBARA_CLOCKS
 Clock ip name array for XBARA.
 
#define XBARB_CLOCKS
 Clock ip name array for XBARB.
 
#define CCM_OBS_M7_CLK_ROOT   128, 4
 
#define CCM_OBS_M4_CLK_ROOT   129, 0
 
#define CCM_OBS_BUS_CLK_ROOT   130, 2
 
#define CCM_OBS_BUS_LPSR_CLK_ROOT   131, 0
 
#define CCM_OBS_SEMC_CLK_ROOT   132, 2
 
#define CCM_OBS_CSSYS_CLK_ROOT   133, 2
 
#define CCM_OBS_CSTRACE_CLK_ROOT   134, 2
 
#define CCM_OBS_M4_SYSTICK_CLK_ROOT   135, 0
 
#define CCM_OBS_M7_SYSTICK_CLK_ROOT   136, 2
 
#define CCM_OBS_ADC1_CLK_ROOT   137, 2
 
#define CCM_OBS_ADC2_CLK_ROOT   138, 2
 
#define CCM_OBS_ACMP_CLK_ROOT   139, 2
 
#define CCM_OBS_FLEXIO1_CLK_ROOT   140, 2
 
#define CCM_OBS_FLEXIO2_CLK_ROOT   141, 2
 
#define CCM_OBS_GPT1_CLK_ROOT   142, 2
 
#define CCM_OBS_GPT2_CLK_ROOT   143, 2
 
#define CCM_OBS_GPT3_CLK_ROOT   144, 2
 
#define CCM_OBS_GPT4_CLK_ROOT   145, 2
 
#define CCM_OBS_GPT5_CLK_ROOT   146, 2
 
#define CCM_OBS_GPT6_CLK_ROOT   147, 2
 
#define CCM_OBS_FLEXSPI1_CLK_ROOT   148, 2
 
#define CCM_OBS_FLEXSPI2_CLK_ROOT   149, 2
 
#define CCM_OBS_CAN1_CLK_ROOT   150, 2
 
#define CCM_OBS_CAN2_CLK_ROOT   151, 2
 
#define CCM_OBS_CAN3_CLK_ROOT   152, 0
 
#define CCM_OBS_LPUART1_CLK_ROOT   153, 2
 
#define CCM_OBS_LPUART2_CLK_ROOT   154, 2
 
#define CCM_OBS_LPUART3_CLK_ROOT   155, 2
 
#define CCM_OBS_LPUART4_CLK_ROOT   156, 2
 
#define CCM_OBS_LPUART5_CLK_ROOT   157, 2
 
#define CCM_OBS_LPUART6_CLK_ROOT   158, 2
 
#define CCM_OBS_LPUART7_CLK_ROOT   159, 2
 
#define CCM_OBS_LPUART8_CLK_ROOT   160, 2
 
#define CCM_OBS_LPUART9_CLK_ROOT   161, 2
 
#define CCM_OBS_LPUART10_CLK_ROOT   162, 2
 
#define CCM_OBS_LPUART11_CLK_ROOT   163, 0
 
#define CCM_OBS_LPUART12_CLK_ROOT   164, 0
 
#define CCM_OBS_LPI2C1_CLK_ROOT   165, 2
 
#define CCM_OBS_LPI2C2_CLK_ROOT   166, 2
 
#define CCM_OBS_LPI2C3_CLK_ROOT   167, 2
 
#define CCM_OBS_LPI2C4_CLK_ROOT   168, 2
 
#define CCM_OBS_LPI2C5_CLK_ROOT   169, 0
 
#define CCM_OBS_LPI2C6_CLK_ROOT   170, 0
 
#define CCM_OBS_LPSPI1_CLK_ROOT   171, 2
 
#define CCM_OBS_LPSPI2_CLK_ROOT   172, 2
 
#define CCM_OBS_LPSPI3_CLK_ROOT   173, 2
 
#define CCM_OBS_LPSPI4_CLK_ROOT   174, 2
 
#define CCM_OBS_LPSPI5_CLK_ROOT   175, 0
 
#define CCM_OBS_LPSPI6_CLK_ROOT   176, 0
 
#define CCM_OBS_EMV1_CLK_ROOT   177, 2
 
#define CCM_OBS_EMV2_CLK_ROOT   178, 2
 
#define CCM_OBS_ENET1_CLK_ROOT   179, 2
 
#define CCM_OBS_ENET2_CLK_ROOT   180, 2
 
#define CCM_OBS_ENET_25M_CLK_ROOT   182, 2
 
#define CCM_OBS_ENET_TIMER1_CLK_ROOT   183, 2
 
#define CCM_OBS_ENET_TIMER2_CLK_ROOT   184, 2
 
#define CCM_OBS_USDHC1_CLK_ROOT   186, 2
 
#define CCM_OBS_USDHC2_CLK_ROOT   187, 2
 
#define CCM_OBS_ASRC_CLK_ROOT   188, 2
 
#define CCM_OBS_MQS_CLK_ROOT   189, 2
 
#define CCM_OBS_MIC_CLK_ROOT   190, 0
 
#define CCM_OBS_SPDIF_CLK_ROOT   191, 2
 
#define CCM_OBS_SAI1_CLK_ROOT   192, 2
 
#define CCM_OBS_SAI2_CLK_ROOT   193, 2
 
#define CCM_OBS_SAI3_CLK_ROOT   194, 2
 
#define CCM_OBS_SAI4_CLK_ROOT   195, 0
 
#define CCM_OBS_GC355_CLK_ROOT   196, 2
 
#define CCM_OBS_LCDIF_CLK_ROOT   197, 2
 
#define CCM_OBS_LCDIFV2_CLK_ROOT   198, 2
 
#define CCM_OBS_MIPI_REF_CLK_ROOT   199, 2
 
#define CCM_OBS_MIPI_ESC_CLK_ROOT   200, 2
 
#define CCM_OBS_CSI2_CLK_ROOT   201, 2
 
#define CCM_OBS_CSI2_ESC_CLK_ROOT   202, 2
 
#define CCM_OBS_CSI2_UI_CLK_ROOT   203, 2
 
#define CCM_OBS_CSI_CLK_ROOT   204, 2
 
#define CCM_OBS_CCM_CKO1_CLK_ROOT   205, 0
 
#define CCM_OBS_CCM_CKO2_CLK_ROOT   206, 2
 
#define CCM_OBS_CM7_CORE_STCLKEN   207, 4
 
#define CCM_OBS_CCM_FLEXRAM_CLK_ROOT   208, 4
 
#define CCM_OBS_MIPI_DSI_TXESC   209, 2
 
#define CCM_OBS_MIPI_DSI_RXESC   210, 2
 
#define CCM_OBS_OSC_RC_16M   224, 0
 
#define CCM_OBS_OSC_RC_48M   225, 0
 
#define CCM_OBS_OSC_RC_48M_DIV2   226, 0
 
#define CCM_OBS_OSC_RC_400M   227, 0
 
#define CCM_OBS_OSC_24M_OUT   229, 0
 
#define CCM_OBS_ARM_PLL_OUT   231, 2
 
#define CCM_OBS_SYS_PLL2_OUT   233, 2
 
#define CCM_OBS_SYS_PLL2_PFD0   234, 2
 
#define CCM_OBS_SYS_PLL2_PFD1   235, 2
 
#define CCM_OBS_SYS_PLL2_PFD2   236, 2
 
#define CCM_OBS_SYS_PLL2_PFD3   237, 2
 
#define CCM_OBS_SYS_PLL3_OUT   239, 2
 
#define CCM_OBS_SYS_PLL3_DIV2   240, 2
 
#define CCM_OBS_SYS_PLL3_PFD0   241, 2
 
#define CCM_OBS_SYS_PLL3_PFD1   242, 2
 
#define CCM_OBS_SYS_PLL3_PFD2   243, 2
 
#define CCM_OBS_SYS_PLL3_PFD3   244, 2
 
#define CCM_OBS_SYS_PLL1_OUT   246, 2
 
#define CCM_OBS_SYS_PLL1_DIV2   247, 2
 
#define CCM_OBS_SYS_PLL1_DIV5   248, 2
 
#define CCM_OBS_PLL_AUDIO_OUT   250, 2
 
#define CCM_OBS_PLL_VIDEO_OUT   252, 2
 
#define CCM_OBS_DIV   3
 
#define clock_ip_name_t   clock_lpcg_t
 
#define CLOCK_GetCpuClkFreq   CLOCK_GetM4Freq
 
#define CLOCK_GetCoreSysClkFreq   CLOCK_GetCpuClkFreq
 
#define PLL_PFD_COUNT   4
 
enum  _clock_lpcg {
  kCLOCK_M7 = 0 , kCLOCK_M4 = 1 , kCLOCK_Sim_M7 = 2 , kCLOCK_Sim_M = 3 ,
  kCLOCK_Sim_Disp = 4 , kCLOCK_Sim_Per = 5 , kCLOCK_Sim_Lpsr = 6 , kCLOCK_Anadig = 7 ,
  kCLOCK_Dcdc = 8 , kCLOCK_Src = 9 , kCLOCK_Ccm = 10 , kCLOCK_Gpc = 11 ,
  kCLOCK_Ssarc = 12 , kCLOCK_Sim_R = 13 , kCLOCK_Wdog1 = 14 , kCLOCK_Wdog2 = 15 ,
  kCLOCK_Wdog3 = 16 , kCLOCK_Wdog4 = 17 , kCLOCK_Ewm0 = 18 , kCLOCK_Sema = 19 ,
  kCLOCK_Mu_A = 20 , kCLOCK_Mu_B = 21 , kCLOCK_Edma = 22 , kCLOCK_Edma_Lpsr = 23 ,
  kCLOCK_Romcp = 24 , kCLOCK_Ocram = 25 , kCLOCK_Flexram = 26 , kCLOCK_Lmem = 27 ,
  kCLOCK_Flexspi1 = 28 , kCLOCK_Flexspi2 = 29 , kCLOCK_Rdc = 30 , kCLOCK_M7_Xrdc = 31 ,
  kCLOCK_M4_Xrdc = 32 , kCLOCK_Semc = 33 , kCLOCK_Xecc = 34 , kCLOCK_Iee = 35 ,
  kCLOCK_Key_Manager = 36 , kCLOCK_Puf = 36 , kCLOCK_Ocotp = 37 , kCLOCK_Snvs_Hp = 38 ,
  kCLOCK_Snvs = 39 , kCLOCK_Caam = 40 , kCLOCK_Jtag_Mux = 41 , kCLOCK_Cstrace = 42 ,
  kCLOCK_Xbar1 = 43 , kCLOCK_Xbar2 = 44 , kCLOCK_Xbar3 = 45 , kCLOCK_Aoi1 = 46 ,
  kCLOCK_Aoi2 = 47 , kCLOCK_Adc_Etc = 48 , kCLOCK_Iomuxc = 49 , kCLOCK_Iomuxc_Lpsr = 50 ,
  kCLOCK_Gpio = 51 , kCLOCK_Kpp = 52 , kCLOCK_Flexio1 = 53 , kCLOCK_Flexio2 = 54 ,
  kCLOCK_Lpadc1 = 55 , kCLOCK_Lpadc2 = 56 , kCLOCK_Dac = 57 , kCLOCK_Acmp1 = 58 ,
  kCLOCK_Acmp2 = 59 , kCLOCK_Acmp3 = 60 , kCLOCK_Acmp4 = 61 , kCLOCK_Pit1 = 62 ,
  kCLOCK_Pit2 = 63 , kCLOCK_Gpt1 = 64 , kCLOCK_Gpt2 = 65 , kCLOCK_Gpt3 = 66 ,
  kCLOCK_Gpt4 = 67 , kCLOCK_Gpt5 = 68 , kCLOCK_Gpt6 = 69 , kCLOCK_Qtimer1 = 70 ,
  kCLOCK_Qtimer2 = 71 , kCLOCK_Qtimer3 = 72 , kCLOCK_Qtimer4 = 73 , kCLOCK_Enc1 = 74 ,
  kCLOCK_Enc2 = 75 , kCLOCK_Enc3 = 76 , kCLOCK_Enc4 = 77 , kCLOCK_Hrtimer = 78 ,
  kCLOCK_Pwm1 = 79 , kCLOCK_Pwm2 = 80 , kCLOCK_Pwm3 = 81 , kCLOCK_Pwm4 = 82 ,
  kCLOCK_Can1 = 83 , kCLOCK_Can2 = 84 , kCLOCK_Can3 = 85 , kCLOCK_Lpuart1 = 86 ,
  kCLOCK_Lpuart2 = 87 , kCLOCK_Lpuart3 = 88 , kCLOCK_Lpuart4 = 89 , kCLOCK_Lpuart5 = 90 ,
  kCLOCK_Lpuart6 = 91 , kCLOCK_Lpuart7 = 92 , kCLOCK_Lpuart8 = 93 , kCLOCK_Lpuart9 = 94 ,
  kCLOCK_Lpuart10 = 95 , kCLOCK_Lpuart11 = 96 , kCLOCK_Lpuart12 = 97 , kCLOCK_Lpi2c1 = 98 ,
  kCLOCK_Lpi2c2 = 99 , kCLOCK_Lpi2c3 = 100 , kCLOCK_Lpi2c4 = 101 , kCLOCK_Lpi2c5 = 102 ,
  kCLOCK_Lpi2c6 = 103 , kCLOCK_Lpspi1 = 104 , kCLOCK_Lpspi2 = 105 , kCLOCK_Lpspi3 = 106 ,
  kCLOCK_Lpspi4 = 107 , kCLOCK_Lpspi5 = 108 , kCLOCK_Lpspi6 = 109 , kCLOCK_Sim1 = 110 ,
  kCLOCK_Sim2 = 111 , kCLOCK_Enet = 112 , kCLOCK_Enet_1g = 113 , kCLOCK_Usb = 115 ,
  kCLOCK_Cdog = 116 , kCLOCK_Usdhc1 = 117 , kCLOCK_Usdhc2 = 118 , kCLOCK_Asrc = 119 ,
  kCLOCK_Mqs = 120 , kCLOCK_Pdm = 121 , kCLOCK_Spdif = 122 , kCLOCK_Sai1 = 123 ,
  kCLOCK_Sai2 = 124 , kCLOCK_Sai3 = 125 , kCLOCK_Sai4 = 126 , kCLOCK_Pxp = 127 ,
  kCLOCK_Gpu2d = 128 , kCLOCK_Lcdif = 129 , kCLOCK_Lcdifv2 = 130 , kCLOCK_Mipi_Dsi = 131 ,
  kCLOCK_Mipi_Csi = 132 , kCLOCK_Csi = 133 , kCLOCK_Dcic_Mipi = 134 , kCLOCK_Dcic_Lcd = 135 ,
  kCLOCK_Video_Mux = 136 , kCLOCK_Uniq_Edt_I = 137 , kCLOCK_IpInvalid
}
 Clock LPCG index. More...
 
enum  _clock_name {
  kCLOCK_CpuClk = 0x0U , kCLOCK_AhbClk = 0x1U , kCLOCK_SemcClk = 0x2U , kCLOCK_IpgClk = 0x3U ,
  kCLOCK_PerClk = 0x4U , kCLOCK_OscClk = 0x5U , kCLOCK_RtcClk = 0x6U , kCLOCK_ArmPllClk = 0x7U ,
  kCLOCK_Usb1PllClk = 0x8U , kCLOCK_Usb1PllPfd0Clk = 0x9U , kCLOCK_Usb1PllPfd1Clk = 0xAU , kCLOCK_Usb1PllPfd2Clk = 0xBU ,
  kCLOCK_Usb1PllPfd3Clk = 0xCU , kCLOCK_Usb1SwClk = 0x17U , kCLOCK_Usb1Sw120MClk = 0x18U , kCLOCK_Usb1Sw60MClk = 0x19U ,
  kCLOCK_Usb1Sw80MClk = 0x1AU , kCLOCK_Usb2PllClk = 0xDU , kCLOCK_SysPllClk = 0xEU , kCLOCK_SysPllPfd0Clk = 0xFU ,
  kCLOCK_SysPllPfd1Clk = 0x10U , kCLOCK_SysPllPfd2Clk = 0x11U , kCLOCK_SysPllPfd3Clk = 0x12U , kCLOCK_EnetPll0Clk = 0x13U ,
  kCLOCK_EnetPll1Clk = 0x14U , kCLOCK_AudioPllClk = 0x15U , kCLOCK_VideoPllClk = 0x16U , kCLOCK_NoneName = CLOCK_SOURCE_NONE ,
  kCLOCK_OscRc16M = 0 , kCLOCK_OscRc48M = 1 , kCLOCK_OscRc48MDiv2 = 2 , kCLOCK_OscRc400M = 3 ,
  kCLOCK_Osc24M = 4 , kCLOCK_Osc24MOut = 5 , kCLOCK_ArmPll = 6 , kCLOCK_ArmPllOut = 7 ,
  kCLOCK_SysPll2 = 8 , kCLOCK_SysPll2Out = 9 , kCLOCK_SysPll2Pfd0 = 10 , kCLOCK_SysPll2Pfd1 = 11 ,
  kCLOCK_SysPll2Pfd2 = 12 , kCLOCK_SysPll2Pfd3 = 13 , kCLOCK_SysPll3 = 14 , kCLOCK_SysPll3Out = 15 ,
  kCLOCK_SysPll3Div2 = 16 , kCLOCK_SysPll3Pfd0 = 17 , kCLOCK_SysPll3Pfd1 = 18 , kCLOCK_SysPll3Pfd2 = 19 ,
  kCLOCK_SysPll3Pfd3 = 20 , kCLOCK_SysPll1 = 21 , kCLOCK_SysPll1Out = 22 , kCLOCK_SysPll1Div2 = 23 ,
  kCLOCK_SysPll1Div5 = 24 , kCLOCK_AudioPll = 25 , kCLOCK_AudioPllOut = 26 , kCLOCK_VideoPll = 27 ,
  kCLOCK_VideoPllOut = 28 , kCLOCK_CpuClk , kCLOCK_CoreSysClk , kCLOCK_Reserved = 0xFFU
}
 Clock name. More...
 
enum  _clock_root {
  kCLOCK_Usdhc1ClkRoot = 0U , kCLOCK_Usdhc2ClkRoot , kCLOCK_FlexspiClkRoot , kCLOCK_CsiClkRoot ,
  kCLOCK_LpspiClkRoot , kCLOCK_TraceClkRoot , kCLOCK_Sai1ClkRoot , kCLOCK_Sai2ClkRoot ,
  kCLOCK_Sai3ClkRoot , kCLOCK_Lpi2cClkRoot , kCLOCK_CanClkRoot , kCLOCK_UartClkRoot ,
  kCLOCK_LcdifClkRoot , kCLOCK_SpdifClkRoot , kCLOCK_Flexio1ClkRoot , kCLOCK_Flexio2ClkRoot ,
  kCLOCK_Root_M7 = 0 , kCLOCK_Root_M4 = 1 , kCLOCK_Root_Bus = 2 , kCLOCK_Root_Bus_Lpsr = 3 ,
  kCLOCK_Root_Semc = 4 , kCLOCK_Root_Cssys = 5 , kCLOCK_Root_Cstrace = 6 , kCLOCK_Root_M4_Systick = 7 ,
  kCLOCK_Root_M7_Systick = 8 , kCLOCK_Root_Adc1 = 9 , kCLOCK_Root_Adc2 = 10 , kCLOCK_Root_Acmp = 11 ,
  kCLOCK_Root_Flexio1 = 12 , kCLOCK_Root_Flexio2 = 13 , kCLOCK_Root_Gpt1 = 14 , kCLOCK_Root_Gpt2 = 15 ,
  kCLOCK_Root_Gpt3 = 16 , kCLOCK_Root_Gpt4 = 17 , kCLOCK_Root_Gpt5 = 18 , kCLOCK_Root_Gpt6 = 19 ,
  kCLOCK_Root_Flexspi1 = 20 , kCLOCK_Root_Flexspi2 = 21 , kCLOCK_Root_Can1 = 22 , kCLOCK_Root_Can2 = 23 ,
  kCLOCK_Root_Can3 = 24 , kCLOCK_Root_Lpuart1 = 25 , kCLOCK_Root_Lpuart2 = 26 , kCLOCK_Root_Lpuart3 = 27 ,
  kCLOCK_Root_Lpuart4 = 28 , kCLOCK_Root_Lpuart5 = 29 , kCLOCK_Root_Lpuart6 = 30 , kCLOCK_Root_Lpuart7 = 31 ,
  kCLOCK_Root_Lpuart8 = 32 , kCLOCK_Root_Lpuart9 = 33 , kCLOCK_Root_Lpuart10 = 34 , kCLOCK_Root_Lpuart11 = 35 ,
  kCLOCK_Root_Lpuart12 = 36 , kCLOCK_Root_Lpi2c1 = 37 , kCLOCK_Root_Lpi2c2 = 38 , kCLOCK_Root_Lpi2c3 = 39 ,
  kCLOCK_Root_Lpi2c4 = 40 , kCLOCK_Root_Lpi2c5 = 41 , kCLOCK_Root_Lpi2c6 = 42 , kCLOCK_Root_Lpspi1 = 43 ,
  kCLOCK_Root_Lpspi2 = 44 , kCLOCK_Root_Lpspi3 = 45 , kCLOCK_Root_Lpspi4 = 46 , kCLOCK_Root_Lpspi5 = 47 ,
  kCLOCK_Root_Lpspi6 = 48 , kCLOCK_Root_Emv1 = 49 , kCLOCK_Root_Emv2 = 50 , kCLOCK_Root_Enet1 = 51 ,
  kCLOCK_Root_Enet2 = 52 , kCLOCK_Root_Enet_25m = 54 , kCLOCK_Root_Enet_Timer1 = 55 , kCLOCK_Root_Enet_Timer2 = 56 ,
  kCLOCK_Root_Usdhc1 = 58 , kCLOCK_Root_Usdhc2 = 59 , kCLOCK_Root_Asrc = 60 , kCLOCK_Root_Mqs = 61 ,
  kCLOCK_Root_Mic = 62 , kCLOCK_Root_Spdif = 63 , kCLOCK_Root_Sai1 = 64 , kCLOCK_Root_Sai2 = 65 ,
  kCLOCK_Root_Sai3 = 66 , kCLOCK_Root_Sai4 = 67 , kCLOCK_Root_Gc355 = 68 , kCLOCK_Root_Lcdif = 69 ,
  kCLOCK_Root_Lcdifv2 = 70 , kCLOCK_Root_Mipi_Ref = 71 , kCLOCK_Root_Mipi_Esc = 72 , kCLOCK_Root_Csi2 = 73 ,
  kCLOCK_Root_Csi2_Esc = 74 , kCLOCK_Root_Csi2_Ui = 75 , kCLOCK_Root_Csi = 76 , kCLOCK_Root_Cko1 = 77 ,
  kCLOCK_Root_Cko2 = 78
}
 Root clock index. More...
 
enum  _clock_root_mux_source {
  kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U , kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U ,
  kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U , kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U , kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U , kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U , kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U ,
  kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U , kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U , kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U , kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U , kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U ,
  kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U , kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U , kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U , kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U ,
  kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U , kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U , kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U ,
  kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U , kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U , kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U , kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U , kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U ,
  kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U , kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U ,
  kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U ,
  kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U ,
  kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U ,
  kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U , kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U ,
  kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U , kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U ,
  kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U , kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U ,
  kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U , kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U ,
  kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U , kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U ,
  kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U , kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U ,
  kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U ,
  kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U , kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U ,
  kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U , kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U , kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U , kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U , kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U , kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U , kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U , kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U , kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U ,
  kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U , kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U ,
  kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U ,
  kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U ,
  kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U , kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U ,
  kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U , kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U , kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U ,
  kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U , kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U , kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U ,
  kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U , kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U , kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U ,
  kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U , kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U , kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U , kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U ,
  kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U , kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U
}
 The enumerator of clock roots' clock source mux value. More...
 
enum  _clock_group { kCLOCK_Group_FlexRAM = 0 , kCLOCK_Group_MipiDsi = 1 , kCLOCK_Group_Last }
 Clock group enumeration. More...
 
enum  _clock_osc { kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U , kCLOCK_RcOsc = 0U , kCLOCK_XtalOsc = 1U }
 OSC 24M sorce select. More...
 
enum  _clock_gate_value {
  kCLOCK_ClockNotNeeded = 0U , kCLOCK_ClockNeededRun = 1U , kCLOCK_ClockNeededRunWait = 3U , kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK ,
  kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK
}
 Clock gate value. More...
 
enum  _clock_mode_t {
  kCLOCK_ModeRun = 0U , kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U , kCLOCK_ModeRun = 0U ,
  kCLOCK_ModeWait = 1U , kCLOCK_ModeStop = 2U
}
 System clock mode. More...
 
enum  _clock_usb_src { kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU , kCLOCK_Usb480M = 0 , kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU }
 USB clock source definition. More...
 
enum  _clock_usb_phy_src { kCLOCK_Usbphy480M = 0 , kCLOCK_Usbphy480M = 0 }
 Source of the USB HS PHY. More...
 
enum  _clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U , kCLOCK_PllClkSrc24M = 0U , kCLOCK_PllSrcClkPN = 1U }
 PLL clock source, bypass cloco source also. More...
 
enum  _clock_pll_post_div { kCLOCK_PllPostDiv8 = 0U , kCLOCK_PllPostDiv4 = 1U }
 PLL post divider enumeration. More...
 
enum  _clock_pll {
  kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT) , kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT) , kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT) , kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT) ,
  kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT) , kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT) , kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT) , kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT) ,
  kCLOCK_PllArm , kCLOCK_PllSys1 , kCLOCK_PllSys2 , kCLOCK_PllSys3 ,
  kCLOCK_PllAudio , kCLOCK_PllVideo , kCLOCK_PllInvalid = -1
}
 PLL name. More...
 
enum  _clock_pfd {
  kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U ,
  kCLOCK_Pfd0 = 0U , kCLOCK_Pfd1 = 1U , kCLOCK_Pfd2 = 2U , kCLOCK_Pfd3 = 3U
}
 PLL PFD name. More...
 
enum  _clock_control_mode { kCLOCK_SoftwareMode = 0U , kCLOCK_GpcMode }
 The enumeration of control mode. More...
 
enum  _clock_24MOsc_mode { kCLOCK_24MOscHighGainMode = 0U , kCLOCK_24MOscBypassMode = 1U , kCLOCK_24MOscLowPowerMode = 2U }
 The enumeration of 24MHz crystal oscillator mode. More...
 
enum  _clock_16MOsc_source { kCLOCK_16MOscSourceFrom16MOsc = 0U , kCLOCK_16MOscSourceFrom24MOsc = 1U }
 The enumeration of 16MHz RC oscillator clock source. More...
 
enum  _clock_1MHzOut_behavior { kCLOCK_1MHzOutDisable = 0U , kCLOCK_1MHzOutEnableLocked1Mhz = 1U , kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U }
 The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. More...
 
enum  _clock_level {
  kCLOCK_Level0 = 0x0UL , kCLOCK_Level1 = 0x1UL , kCLOCK_Level2 = 0x2UL , kCLOCK_Level3 = 0x3UL ,
  kCLOCK_Level4 = 0x4UL
}
 The clock dependence level. More...
 
typedef enum _clock_lpcg clock_lpcg_t
 Clock LPCG index.
 
typedef enum _clock_name clock_name_t
 Clock name.
 
typedef enum _clock_root clock_root_t
 Root clock index.
 
typedef enum _clock_root_mux_source clock_root_mux_source_t
 The enumerator of clock roots' clock source mux value.
 
typedef enum _clock_group clock_group_t
 Clock group enumeration.
 
typedef struct _clock_group_config clock_group_config_t
 The structure used to configure clock group.
 
typedef enum _clock_osc clock_osc_t
 OSC 24M sorce select.
 
typedef enum _clock_gate_value clock_gate_value_t
 Clock gate value.
 
typedef enum _clock_mode_t clock_mode_t
 System clock mode.
 
typedef enum _clock_usb_src clock_usb_src_t
 USB clock source definition.
 
typedef enum _clock_usb_phy_src clock_usb_phy_src_t
 Source of the USB HS PHY.
 
typedef enum _clock_pll_post_div clock_pll_post_div_t
 PLL post divider enumeration.
 
typedef struct _clock_arm_pll_config clock_arm_pll_config_t
 PLL configuration for ARM.
 
typedef struct _clock_usb_pll_config clock_usb_pll_config_t
 PLL configuration for USB.
 
typedef struct _clock_pll_ss_config clock_pll_ss_config_t
 Spread specturm configure Pll.
 
typedef struct _clock_sys_pll2_config clock_sys_pll2_config_t
 PLL configure for Sys Pll2.
 
typedef struct _clock_sys_pll1_config clock_sys_pll1_config_t
 PLL configure for Sys Pll1.
 
typedef struct _clock_audio_pll_config clock_av_pll_config_t
 PLL configuration for AUDIO and VIDEO.
 
typedef struct _clock_audio_pll_config clock_audio_pll_config_t
 
typedef struct _clock_audio_pll_config clock_video_pll_config_t
 
typedef struct _clock_audio_pll_gpc_config clock_audio_pll_gpc_config_t
 PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL.
 
typedef struct _clock_audio_pll_gpc_config clock_video_pll_gpc_config_t
 
typedef struct _clock_audio_pll_gpc_config clock_sys_pll1_gpc_config_t
 
typedef struct _clock_enet_pll_config clock_enet_pll_config_t
 PLL configuration for ENET.
 
typedef struct _clock_root_config_t clock_root_config_t
 Clock root configuration.
 
typedef struct _clock_root_setpoint_config_t clock_root_setpoint_config_t
 Clock root configuration in SetPoint Mode.
 
typedef enum _clock_pll clock_pll_t
 PLL name.
 
typedef enum _clock_pfd clock_pfd_t
 PLL PFD name.
 
typedef enum _clock_control_mode clock_control_mode_t
 The enumeration of control mode.
 
typedef enum _clock_24MOsc_mode clock_24MOsc_mode_t
 The enumeration of 24MHz crystal oscillator mode.
 
typedef enum _clock_16MOsc_source clock_16MOsc_source_t
 The enumeration of 16MHz RC oscillator clock source.
 
typedef enum _clock_1MHzOut_behavior clock_1MHzOut_behavior_t
 The enumeration of 1MHz output clock behavior, including disabling 1MHz output, enabling locked 1MHz clock output, and enabling free-running 1MHz clock output.
 
typedef enum _clock_level clock_level_t
 The clock dependence level.
 
void CLOCK_SetGroupConfig (clock_group_t group, const clock_group_config_t *config)
 Set the clock group configuration.
 
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