RTEMS 6.1-rc4
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SLCR support. More...
#include <stdint.h>
Go to the source code of this file.
Functions | |
void | zynq_slcr_fpga_clk_rst_mask_set (uint32_t mask) |
Set the mask that allows the FPGA resets to be modified. | |
void | zynq_slcr_fpga_clk_rst (uint32_t val) |
Control the FPGA reset values. | |
void | zynq_slcr_level_shifter_enable (uint32_t val) |
Control the level shifters between the PS and PL. | |
SLCR support.
void zynq_slcr_fpga_clk_rst | ( | uint32_t | val | ) |
Control the FPGA reset values.
val | Bits 0 through 3 correspond to FPGA RST 0 through 3. A bit value of 1 asserts the reset. |
void zynq_slcr_fpga_clk_rst_mask_set | ( | uint32_t | mask | ) |
Set the mask that allows the FPGA resets to be modified.
Bit 0 corresponds to FPGA0_OUT_RST, and bit 3 to FPGA3_OUT_RST. Setting a bit in the mask to 1 allows calls to zynq_slcr_fpga_clk_rst to modify that reset. The default mask is 0xf.
void zynq_slcr_level_shifter_enable | ( | uint32_t | val | ) |
Control the level shifters between the PS and PL.
val | Acceptable values are ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE, ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL, and ZYNQ_SLCR_LVL_SHFTR_EN_ALL. |