#include "xil_io.h"

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Macros
#define	XNANDPSU_HW_H /* by using protection macros */

#define	XNANDPSU_PKT_OFFSET 0x00U

#define	XNANDPSU_MEM_ADDR1_OFFSET 0x04U

#define	XNANDPSU_MEM_ADDR2_OFFSET 0x08U

#define	XNANDPSU_CMD_OFFSET 0x0CU

#define	XNANDPSU_PROG_OFFSET 0x10U

#define	XNANDPSU_INTR_STS_EN_OFFSET 0x14U

#define	XNANDPSU_INTR_SIG_EN_OFFSET 0x18U

#define	XNANDPSU_INTR_STS_OFFSET 0x1CU

#define	XNANDPSU_READY_BUSY_OFFSET 0x20U

#define	XNANDPSU_FLASH_STS_OFFSET 0x28U

#define	XNANDPSU_TIMING_OFFSET 0x2CU

#define	XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U

#define	XNANDPSU_ECC_OFFSET 0x34U

#define	XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U

#define	XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU

#define	XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U

#define	XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U

#define	XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U

#define	XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU

#define	XNANDPSU_CPU_REL_OFFSET 0x58U

#define	XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU

#define	XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U

#define	XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U

#define	XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U

#define	XNANDPSU_DATA_INTF_OFFSET 0x6CU

#define	XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U

#define	XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U

#define	XNANDPSU_DMA_BUF_BND_OFFSET 0x54U

#define	XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U

Packet Register bit definitions and masks
#define	XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU

#define	XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U

#define	XNANDPSU_PKT_PKT_CNT_SHIFT 12U

Memory Address Register 1 bit definitions and masks
#define	XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U

Memory Address Register 2 bit definitions and masks
#define	XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U

#define	XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U

Command Register bit definitions and masks
#define	XNANDPSU_CMD_CMD1_MASK 0x000000FFU

#define	XNANDPSU_CMD_CMD2_MASK 0x0000FF00U

#define	XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U

#define	XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U

#define	XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U

#define	XNANDPSU_CMD_ECC_ON_MASK 0x80000000U

#define	XNANDPSU_CMD_CMD2_SHIFT 8U

#define	XNANDPSU_CMD_PG_SIZE_SHIFT 23U

#define	XNANDPSU_CMD_DMA_EN_SHIFT 26U

#define	XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U

#define	XNANDPSU_CMD_ECC_ON_SHIFT 31U

Program Register bit definitions and masks
#define	XNANDPSU_PROG_RD_MASK 0x00000001U

#define	XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U

#define	XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U

#define	XNANDPSU_PROG_RD_STS_MASK 0x00000008U

#define	XNANDPSU_PROG_PG_PROG_MASK 0x00000010U

#define	XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U

#define	XNANDPSU_PROG_RD_ID_MASK 0x00000040U

#define	XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U

#define	XNANDPSU_PROG_RST_MASK 0x00000100U

#define	XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U

#define	XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U

#define	XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U

#define	XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U

#define	XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U

#define	XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U

#define	XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U

#define	XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U

#define	XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U

#define	XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U

#define	XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U

#define	XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U

#define	XNANDPSU_PROG_RST_LUN_MASK 0x00800000U

#define	XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U

#define	XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U

#define	XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U

Interrupt Status Enable Register bit definitions and masks
#define	XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt Signal Enable Register bit definitions and masks
#define	XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt Status Register bit definitions and masks
#define	XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt bit definitions and masks
#define	XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U

ID2 Register bit definitions and masks
#define	XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU

Flash Status Register bit definitions and masks
#define	XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU

Timing Register bit definitions and masks
#define	XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U

#define	XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U

#define	XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U

#define	XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U

ECC Register bit definitions and masks
#define	XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU

#define	XNANDPSU_ECC_SIZE_MASK 0x01FF0000U

#define	XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U

ECC Error Count Register bit definitions and masks
#define	XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU

#define	XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U

ECC Spare Command Register bit definitions and masks
#define	XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU

#define	XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U

Data Interface Register bit definitions and masks
#define	XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U

#define	XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U

#define	XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U

#define	XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U

#define	XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U

#define	XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U

DMA Buffer Boundary Register bit definitions and masks
#define	XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U

#define	XNANDPSU_DMA_BUF_BND_4K 0x0U

#define	XNANDPSU_DMA_BUF_BND_8K 0x1U

#define	XNANDPSU_DMA_BUF_BND_16K 0x2U

#define	XNANDPSU_DMA_BUF_BND_32K 0x3U

#define	XNANDPSU_DMA_BUF_BND_64K 0x4U

#define	XNANDPSU_DMA_BUF_BND_128K 0x5U

#define	XNANDPSU_DMA_BUF_BND_256K 0x6U

#define	XNANDPSU_DMA_BUF_BND_512K 0x7U

Slave DMA Configuration Register bit definitions and masks
#define	XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U

#define	XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU

#define	XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U

#define	XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U

#define	XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U

#define	XNandPsu_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))

#define	XNandPsu_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(((BaseAddress) + (RegOffset)), (Data))

Macros