RTEMS 6.1-rc4
Loading...
Searching...
No Matches
Data Fields
_enet_buffer_config Struct Reference
Enet

Defines the receive buffer descriptor configuration structure. More...

#include <fsl_enet.h>

Data Fields

uint16_t rxBdNumber
 
uint16_t txBdNumber
 
uint16_t rxBuffSizeAlign
 
uint16_t txBuffSizeAlign
 
volatile enet_rx_bd_struct_t * rxBdStartAddrAlign
 
volatile enet_tx_bd_struct_t * txBdStartAddrAlign
 
uint8_t * rxBufferAlign
 
uint8_t * txBufferAlign
 
bool rxMaintainEnable
 
bool txMaintainEnable
 
enet_frame_info_t * txFrameInfo
 

Detailed Description

Defines the receive buffer descriptor configuration structure.

Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements.

  1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size.
  2. The aligned transmit and receive buffer descriptor start address must be at least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. buffer descriptors should be put in non-cacheable region when cache is enabled.
  3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". when the data buffers are in cacheable region when cache is enabled, all those size should be aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size.
The documentation for this struct was generated from the following file:
Generated by doxygen 1.9.6