RTEMS 6.1-rc4
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stm32h7xx_hal_dma.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_DMA_H
21#define STM32H7xx_HAL_DMA_H
22
23#ifdef __cplusplus
24 extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
39
49typedef struct
50{
51 uint32_t Request;
54 uint32_t Direction;
58 uint32_t PeriphInc;
61 uint32_t MemInc;
64 uint32_t PeriphDataAlignment;
67 uint32_t MemDataAlignment;
70 uint32_t Mode;
75 uint32_t Priority;
78 uint32_t FIFOMode;
83 uint32_t FIFOThreshold;
86 uint32_t MemBurst;
92 uint32_t PeriphBurst;
97}DMA_InitTypeDef;
98
102typedef enum
103{
104 HAL_DMA_STATE_RESET = 0x00U,
105 HAL_DMA_STATE_READY = 0x01U,
106 HAL_DMA_STATE_BUSY = 0x02U,
107 HAL_DMA_STATE_ERROR = 0x03U,
108 HAL_DMA_STATE_ABORT = 0x04U,
109}HAL_DMA_StateTypeDef;
110
114typedef enum
115{
116 HAL_DMA_FULL_TRANSFER = 0x00U,
117 HAL_DMA_HALF_TRANSFER = 0x01U,
118}HAL_DMA_LevelCompleteTypeDef;
119
123typedef enum
124{
125 HAL_DMA_XFER_CPLT_CB_ID = 0x00U,
126 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U,
127 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U,
128 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U,
129 HAL_DMA_XFER_ERROR_CB_ID = 0x04U,
130 HAL_DMA_XFER_ABORT_CB_ID = 0x05U,
131 HAL_DMA_XFER_ALL_CB_ID = 0x06U
132}HAL_DMA_CallbackIDTypeDef;
133
137typedef struct __DMA_HandleTypeDef
138{
139 void *Instance;
141 DMA_InitTypeDef Init;
143 HAL_LockTypeDef Lock;
145 __IO HAL_DMA_StateTypeDef State;
147 void *Parent;
149 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);
151 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
153 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);
155 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);
157 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);
159 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);
161 __IO uint32_t ErrorCode;
163 uint32_t StreamBaseAddress;
165 uint32_t StreamIndex;
167 DMAMUX_Channel_TypeDef *DMAmuxChannel;
169 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus;
171 uint32_t DMAmuxChannelStatusMask;
174 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen;
176 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus;
178 uint32_t DMAmuxRequestGenStatusMask;
180}DMA_HandleTypeDef;
181
187/* Exported constants --------------------------------------------------------*/
188
200#define HAL_DMA_ERROR_NONE (0x00000000U)
201#define HAL_DMA_ERROR_TE (0x00000001U)
202#define HAL_DMA_ERROR_FE (0x00000002U)
203#define HAL_DMA_ERROR_DME (0x00000004U)
204#define HAL_DMA_ERROR_TIMEOUT (0x00000020U)
205#define HAL_DMA_ERROR_PARAM (0x00000040U)
206#define HAL_DMA_ERROR_NO_XFER (0x00000080U)
207#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)
208#define HAL_DMA_ERROR_SYNC (0x00000200U)
209#define HAL_DMA_ERROR_REQGEN (0x00000400U)
210#define HAL_DMA_ERROR_BUSY (0x00000800U)
221/* DMAMUX1 requests */
222#define DMA_REQUEST_MEM2MEM 0U
224#define DMA_REQUEST_GENERATOR0 1U
225#define DMA_REQUEST_GENERATOR1 2U
226#define DMA_REQUEST_GENERATOR2 3U
227#define DMA_REQUEST_GENERATOR3 4U
228#define DMA_REQUEST_GENERATOR4 5U
229#define DMA_REQUEST_GENERATOR5 6U
230#define DMA_REQUEST_GENERATOR6 7U
231#define DMA_REQUEST_GENERATOR7 8U
233#define DMA_REQUEST_ADC1 9U
234#define DMA_REQUEST_ADC2 10U
236#define DMA_REQUEST_TIM1_CH1 11U
237#define DMA_REQUEST_TIM1_CH2 12U
238#define DMA_REQUEST_TIM1_CH3 13U
239#define DMA_REQUEST_TIM1_CH4 14U
240#define DMA_REQUEST_TIM1_UP 15U
241#define DMA_REQUEST_TIM1_TRIG 16U
242#define DMA_REQUEST_TIM1_COM 17U
244#define DMA_REQUEST_TIM2_CH1 18U
245#define DMA_REQUEST_TIM2_CH2 19U
246#define DMA_REQUEST_TIM2_CH3 20U
247#define DMA_REQUEST_TIM2_CH4 21U
248#define DMA_REQUEST_TIM2_UP 22U
250#define DMA_REQUEST_TIM3_CH1 23U
251#define DMA_REQUEST_TIM3_CH2 24U
252#define DMA_REQUEST_TIM3_CH3 25U
253#define DMA_REQUEST_TIM3_CH4 26U
254#define DMA_REQUEST_TIM3_UP 27U
255#define DMA_REQUEST_TIM3_TRIG 28U
257#define DMA_REQUEST_TIM4_CH1 29U
258#define DMA_REQUEST_TIM4_CH2 30U
259#define DMA_REQUEST_TIM4_CH3 31U
260#define DMA_REQUEST_TIM4_UP 32U
262#define DMA_REQUEST_I2C1_RX 33U
263#define DMA_REQUEST_I2C1_TX 34U
264#define DMA_REQUEST_I2C2_RX 35U
265#define DMA_REQUEST_I2C2_TX 36U
267#define DMA_REQUEST_SPI1_RX 37U
268#define DMA_REQUEST_SPI1_TX 38U
269#define DMA_REQUEST_SPI2_RX 39U
270#define DMA_REQUEST_SPI2_TX 40U
272#define DMA_REQUEST_USART1_RX 41U
273#define DMA_REQUEST_USART1_TX 42U
274#define DMA_REQUEST_USART2_RX 43U
275#define DMA_REQUEST_USART2_TX 44U
276#define DMA_REQUEST_USART3_RX 45U
277#define DMA_REQUEST_USART3_TX 46U
279#define DMA_REQUEST_TIM8_CH1 47U
280#define DMA_REQUEST_TIM8_CH2 48U
281#define DMA_REQUEST_TIM8_CH3 49U
282#define DMA_REQUEST_TIM8_CH4 50U
283#define DMA_REQUEST_TIM8_UP 51U
284#define DMA_REQUEST_TIM8_TRIG 52U
285#define DMA_REQUEST_TIM8_COM 53U
287#define DMA_REQUEST_TIM5_CH1 55U
288#define DMA_REQUEST_TIM5_CH2 56U
289#define DMA_REQUEST_TIM5_CH3 57U
290#define DMA_REQUEST_TIM5_CH4 58U
291#define DMA_REQUEST_TIM5_UP 59U
292#define DMA_REQUEST_TIM5_TRIG 60U
294#define DMA_REQUEST_SPI3_RX 61U
295#define DMA_REQUEST_SPI3_TX 62U
297#define DMA_REQUEST_UART4_RX 63U
298#define DMA_REQUEST_UART4_TX 64U
299#define DMA_REQUEST_UART5_RX 65U
300#define DMA_REQUEST_UART5_TX 66U
302#define DMA_REQUEST_DAC1_CH1 67U
303#define DMA_REQUEST_DAC1_CH2 68U
305#define DMA_REQUEST_TIM6_UP 69U
306#define DMA_REQUEST_TIM7_UP 70U
308#define DMA_REQUEST_USART6_RX 71U
309#define DMA_REQUEST_USART6_TX 72U
311#define DMA_REQUEST_I2C3_RX 73U
312#define DMA_REQUEST_I2C3_TX 74U
314#if defined (PSSI)
315#define DMA_REQUEST_DCMI_PSSI 75U
316#define DMA_REQUEST_DCMI DMA_REQUEST_DCMI_PSSI /* Legacy define */
317#else
318#define DMA_REQUEST_DCMI 75U
319#endif /* PSSI */
320
321#define DMA_REQUEST_CRYP_IN 76U
322#define DMA_REQUEST_CRYP_OUT 77U
324#define DMA_REQUEST_HASH_IN 78U
326#define DMA_REQUEST_UART7_RX 79U
327#define DMA_REQUEST_UART7_TX 80U
328#define DMA_REQUEST_UART8_RX 81U
329#define DMA_REQUEST_UART8_TX 82U
331#define DMA_REQUEST_SPI4_RX 83U
332#define DMA_REQUEST_SPI4_TX 84U
333#define DMA_REQUEST_SPI5_RX 85U
334#define DMA_REQUEST_SPI5_TX 86U
336#define DMA_REQUEST_SAI1_A 87U
337#define DMA_REQUEST_SAI1_B 88U
339#if defined(SAI2)
340#define DMA_REQUEST_SAI2_A 89U
341#define DMA_REQUEST_SAI2_B 90U
342#endif /* SAI2 */
343
344#define DMA_REQUEST_SWPMI_RX 91U
345#define DMA_REQUEST_SWPMI_TX 92U
347#define DMA_REQUEST_SPDIF_RX_DT 93U
348#define DMA_REQUEST_SPDIF_RX_CS 94U
350#if defined(HRTIM1)
351#define DMA_REQUEST_HRTIM_MASTER 95U
352#define DMA_REQUEST_HRTIM_TIMER_A 96U
353#define DMA_REQUEST_HRTIM_TIMER_B 97U
354#define DMA_REQUEST_HRTIM_TIMER_C 98U
355#define DMA_REQUEST_HRTIM_TIMER_D 99U
356#define DMA_REQUEST_HRTIM_TIMER_E 100U
357#endif /* HRTIM1 */
358
359#define DMA_REQUEST_DFSDM1_FLT0 101U
360#define DMA_REQUEST_DFSDM1_FLT1 102U
361#define DMA_REQUEST_DFSDM1_FLT2 103U
362#define DMA_REQUEST_DFSDM1_FLT3 104U
364#define DMA_REQUEST_TIM15_CH1 105U
365#define DMA_REQUEST_TIM15_UP 106U
366#define DMA_REQUEST_TIM15_TRIG 107U
367#define DMA_REQUEST_TIM15_COM 108U
369#define DMA_REQUEST_TIM16_CH1 109U
370#define DMA_REQUEST_TIM16_UP 110U
372#define DMA_REQUEST_TIM17_CH1 111U
373#define DMA_REQUEST_TIM17_UP 112U
375#if defined(SAI3)
376#define DMA_REQUEST_SAI3_A 113U
377#define DMA_REQUEST_SAI3_B 114U
378#endif /* SAI3 */
379
380#if defined(ADC3)
381#define DMA_REQUEST_ADC3 115U
382#endif /* ADC3 */
383
384#if defined(UART9)
385#define DMA_REQUEST_UART9_RX 116U
386#define DMA_REQUEST_UART9_TX 117U
387#endif /* UART9 */
388
389#if defined(USART10)
390#define DMA_REQUEST_USART10_RX 118U
391#define DMA_REQUEST_USART10_TX 119U
392#endif /* USART10 */
393
394#if defined(FMAC)
395#define DMA_REQUEST_FMAC_READ 120U
396#define DMA_REQUEST_FMAC_WRITE 121U
397#endif /* FMAC */
398
399#if defined(CORDIC)
400#define DMA_REQUEST_CORDIC_READ 122U
401#define DMA_REQUEST_CORDIC_WRITE 123U
402#endif /* CORDIC */
403
404#if defined(I2C5)
405#define DMA_REQUEST_I2C5_RX 124U
406#define DMA_REQUEST_I2C5_TX 125U
407#endif /* I2C5 */
408
409#if defined(TIM23)
410#define DMA_REQUEST_TIM23_CH1 126U
411#define DMA_REQUEST_TIM23_CH2 127U
412#define DMA_REQUEST_TIM23_CH3 128U
413#define DMA_REQUEST_TIM23_CH4 129U
414#define DMA_REQUEST_TIM23_UP 130U
415#define DMA_REQUEST_TIM23_TRIG 131U
416#endif /* TIM23 */
417
418#if defined(TIM24)
419#define DMA_REQUEST_TIM24_CH1 132U
420#define DMA_REQUEST_TIM24_CH2 133U
421#define DMA_REQUEST_TIM24_CH3 134U
422#define DMA_REQUEST_TIM24_CH4 135U
423#define DMA_REQUEST_TIM24_UP 136U
424#define DMA_REQUEST_TIM24_TRIG 137U
425#endif /* TIM24 */
426
427/* DMAMUX2 requests */
428#define BDMA_REQUEST_MEM2MEM 0U
429#define BDMA_REQUEST_GENERATOR0 1U
430#define BDMA_REQUEST_GENERATOR1 2U
431#define BDMA_REQUEST_GENERATOR2 3U
432#define BDMA_REQUEST_GENERATOR3 4U
433#define BDMA_REQUEST_GENERATOR4 5U
434#define BDMA_REQUEST_GENERATOR5 6U
435#define BDMA_REQUEST_GENERATOR6 7U
436#define BDMA_REQUEST_GENERATOR7 8U
437#define BDMA_REQUEST_LPUART1_RX 9U
438#define BDMA_REQUEST_LPUART1_TX 10U
439#define BDMA_REQUEST_SPI6_RX 11U
440#define BDMA_REQUEST_SPI6_TX 12U
441#define BDMA_REQUEST_I2C4_RX 13U
442#define BDMA_REQUEST_I2C4_TX 14U
443#if defined(SAI4)
444#define BDMA_REQUEST_SAI4_A 15U
445#define BDMA_REQUEST_SAI4_B 16U
446#endif /* SAI4 */
447#if defined(ADC3)
448#define BDMA_REQUEST_ADC3 17U
449#endif /* ADC3 */
450#if defined(DAC2)
451#define BDMA_REQUEST_DAC2_CH1 17U
452#endif /* DAC2 */
453#if defined(DFSDM2_Channel0)
454#define BDMA_REQUEST_DFSDM2_FLT0 18U
455#endif /* DFSDM1_Channel0 */
456
466#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U)
467#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0)
468#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1)
478#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC)
479#define DMA_PINC_DISABLE ((uint32_t)0x00000000U)
489#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC)
490#define DMA_MINC_DISABLE ((uint32_t)0x00000000U)
500#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U)
501#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0)
502#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1)
512#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U)
513#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0)
514#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1)
524#define DMA_NORMAL ((uint32_t)0x00000000U)
525#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC)
526#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL)
527#define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM)
528#define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT))
538#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U)
539#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0)
540#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1)
541#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL)
551#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U)
552#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS)
562#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U)
563#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0)
564#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1)
565#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH)
575#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
576#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
577#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
578#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
588#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
589#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
590#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
591#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
601#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
602#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
603#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
604#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
605#define DMA_IT_FE ((uint32_t)0x00000080U)
615#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
616#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
617#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
618#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
619#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
620#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
621#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
622#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
623#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
624#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
625#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
626#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
627#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
628#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
629#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
630#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
631#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
632#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
633#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
634#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
644#define BDMA_FLAG_GL0 ((uint32_t)0x00000001)
645#define BDMA_FLAG_TC0 ((uint32_t)0x00000002)
646#define BDMA_FLAG_HT0 ((uint32_t)0x00000004)
647#define BDMA_FLAG_TE0 ((uint32_t)0x00000008)
648#define BDMA_FLAG_GL1 ((uint32_t)0x00000010)
649#define BDMA_FLAG_TC1 ((uint32_t)0x00000020)
650#define BDMA_FLAG_HT1 ((uint32_t)0x00000040)
651#define BDMA_FLAG_TE1 ((uint32_t)0x00000080)
652#define BDMA_FLAG_GL2 ((uint32_t)0x00000100)
653#define BDMA_FLAG_TC2 ((uint32_t)0x00000200)
654#define BDMA_FLAG_HT2 ((uint32_t)0x00000400)
655#define BDMA_FLAG_TE2 ((uint32_t)0x00000800)
656#define BDMA_FLAG_GL3 ((uint32_t)0x00001000)
657#define BDMA_FLAG_TC3 ((uint32_t)0x00002000)
658#define BDMA_FLAG_HT3 ((uint32_t)0x00004000)
659#define BDMA_FLAG_TE3 ((uint32_t)0x00008000)
660#define BDMA_FLAG_GL4 ((uint32_t)0x00010000)
661#define BDMA_FLAG_TC4 ((uint32_t)0x00020000)
662#define BDMA_FLAG_HT4 ((uint32_t)0x00040000)
663#define BDMA_FLAG_TE4 ((uint32_t)0x00080000)
664#define BDMA_FLAG_GL5 ((uint32_t)0x00100000)
665#define BDMA_FLAG_TC5 ((uint32_t)0x00200000)
666#define BDMA_FLAG_HT5 ((uint32_t)0x00400000)
667#define BDMA_FLAG_TE5 ((uint32_t)0x00800000)
668#define BDMA_FLAG_GL6 ((uint32_t)0x01000000)
669#define BDMA_FLAG_TC6 ((uint32_t)0x02000000)
670#define BDMA_FLAG_HT6 ((uint32_t)0x04000000)
671#define BDMA_FLAG_TE6 ((uint32_t)0x08000000)
672#define BDMA_FLAG_GL7 ((uint32_t)0x10000000)
673#define BDMA_FLAG_TC7 ((uint32_t)0x20000000)
674#define BDMA_FLAG_HT7 ((uint32_t)0x40000000)
675#define BDMA_FLAG_TE7 ((uint32_t)0x80000000)
676
685/* Exported macro ------------------------------------------------------------*/
695#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
696
709#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
710
716#define __HAL_DMA_ENABLE(__HANDLE__) \
717((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
718(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
719
725#define __HAL_DMA_DISABLE(__HANDLE__) \
726((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
727(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
728
729/* Interrupt & Flag management */
730
736#if defined(BDMA1)
737#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
738(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
739 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
741 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
742 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
743 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
744 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
745 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
746 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
747 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
748 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
749 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
750 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
751 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
752 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
753 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
754 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0 :\
755 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0 :\
756 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1 :\
757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1 :\
758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2 :\
759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2 :\
760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3 :\
761 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3 :\
762 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4 :\
763 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4 :\
764 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5 :\
765 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5 :\
766 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6 :\
767 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6 :\
768 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7 :\
769 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7 :\
770 (uint32_t)0x00000000)
771#else
772#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
773(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
774 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
775 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
776 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
777 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
778 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
779 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
780 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
781 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
782 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
783 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
784 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
785 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
786 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
787 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
788 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
789 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\
790 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\
791 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\
792 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\
793 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\
794 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\
795 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
796 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
797 (uint32_t)0x00000000)
798#endif /* BDMA1 */
799
805#if defined(BDMA1)
806#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
807(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
808 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
809 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
810 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
811 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
812 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
813 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
814 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
815 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
816 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
817 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
818 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
819 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
820 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
821 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
822 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
823 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0 :\
824 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0 :\
825 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1 :\
826 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1 :\
827 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2 :\
828 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2 :\
829 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3 :\
830 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3 :\
831 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4 :\
832 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4 :\
833 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5 :\
834 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5 :\
835 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6 :\
836 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6 :\
837 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7 :\
838 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7 :\
839 (uint32_t)0x00000000)
840#else
841#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
842(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
843 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
844 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
845 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
846 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
847 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
848 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
849 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
850 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
851 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
852 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
853 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
854 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
855 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
856 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
857 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
858 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\
859 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\
860 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\
861 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\
862 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\
863 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\
864 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
865 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
866 (uint32_t)0x00000000)
867#endif /* BDMA1 */
868
874#if defined(BDMA1)
875#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
876(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
877 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
878 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
879 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
880 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
881 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
882 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
883 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
884 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
885 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
886 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
887 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
888 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
889 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
890 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
891 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
892 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0 :\
893 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0 :\
894 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1 :\
895 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1 :\
896 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2 :\
897 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2 :\
898 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3 :\
899 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3 :\
900 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4 :\
901 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4 :\
902 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5 :\
903 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5 :\
904 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6 :\
905 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6 :\
906 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7 :\
907 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7 :\
908 (uint32_t)0x00000000)
909#else
910#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
911(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
912 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
913 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
914 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
915 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
916 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
917 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
918 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
919 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
920 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
921 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
922 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
923 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
924 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
925 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
926 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
927 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\
928 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\
929 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\
930 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\
931 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\
932 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\
933 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
934 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
935 (uint32_t)0x00000000)
936#endif /* BDMA1 */
937
943#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
944(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
945 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
946 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
947 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
948 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
949 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
950 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
951 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
952 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
953 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
954 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
955 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
956 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
957 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
958 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
959 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
960 (uint32_t)0x00000000)
961
967#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
968(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
969 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
970 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
971 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
972 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
973 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
974 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
975 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
976 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
977 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
978 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
979 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
980 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
981 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
982 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
983 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
984 (uint32_t)0x00000000)
985
991#if defined(BDMA1)
992#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
993(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
994 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
995 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
996 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
997 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
998 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
999 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
1000 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
1001 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
1002 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
1003 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
1004 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
1005 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
1006 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
1007 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
1008 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
1009 (uint32_t)0x00000000)
1010#else
1011#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
1012(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
1013 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
1014 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
1015 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
1016 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
1017 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
1018 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
1019 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
1020 (uint32_t)0x00000000)
1021#endif /* BDMA1 */
1022
1036#if defined(BDMA1)
1037#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1038(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->ISR & (__FLAG__)) :\
1039 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7 )? (BDMA1->ISR & (__FLAG__)) :\
1040 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3 )? (DMA2->HISR & (__FLAG__)) :\
1041 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7 )? (DMA2->LISR & (__FLAG__)) :\
1042 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3 )? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1043#else
1044#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
1045(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
1046 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
1047 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
1048 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
1049#endif /* BDMA1 */
1050
1064#if defined(BDMA1)
1065#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1066(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
1067 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA1->IFCR = (__FLAG__)) :\
1068 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1069 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1070 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1071#else
1072#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1073(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
1074 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
1075 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
1076 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
1077#endif /* BDMA1 */
1078
1079#define DMA_TO_BDMA_IT(__DMA_IT__) \
1080((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1081 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
1082 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
1083 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\
1084 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
1085 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
1086 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
1087 (uint32_t)0x00000000)
1088
1089
1090#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1091(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
1092
1093#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1094(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
1095
1108#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1109 (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1110 (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
1111
1112
1113#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
1114
1115#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1116(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
1117
1130#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
1131 (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
1132 (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
1133
1134
1135#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
1136
1137#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
1138 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
1139 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
1140
1153#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1154 (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
1155 (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
1156
1174#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1175 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
1176 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
1177
1184#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
1185 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
1186 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
1187
1192/* Include DMA HAL Extension module */
1193#include "stm32h7xx_hal_dma_ex.h"
1194
1195/* Exported functions --------------------------------------------------------*/
1196
1208HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
1209HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
1219HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1220HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
1221HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
1222HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
1223HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
1224void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
1225HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
1226HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
1227
1237HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
1238uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
1245/* Private Constants -------------------------------------------------------------*/
1255/* Private types -------------------------------------------------------------*/
1264/* Private macros ------------------------------------------------------------*/
1271#if defined(TIM24)
1272#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_TIM24_TRIG))
1273#elif defined(ADC3)
1274#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
1275#else
1276#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
1277#endif /* TIM24 */
1278
1279#if defined(ADC3)
1280#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
1281#else
1282#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
1283#endif /* ADC3 */
1284
1285#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
1286 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
1287 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
1288
1289#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
1290
1291#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
1292 ((STATE) == DMA_PINC_DISABLE))
1293
1294#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
1295 ((STATE) == DMA_MINC_DISABLE))
1296
1297#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
1298 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
1299 ((SIZE) == DMA_PDATAALIGN_WORD))
1300
1301#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
1302 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
1303 ((SIZE) == DMA_MDATAALIGN_WORD ))
1304
1305#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
1306 ((MODE) == DMA_CIRCULAR) || \
1307 ((MODE) == DMA_PFCTRL) || \
1308 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \
1309 ((MODE) == DMA_DOUBLE_BUFFER_M1))
1310
1311#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
1312 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
1313 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
1314 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
1315
1316#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
1317 ((STATE) == DMA_FIFOMODE_ENABLE))
1318
1319#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
1320 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
1321 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
1322 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
1323
1324#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
1325 ((BURST) == DMA_MBURST_INC4) || \
1326 ((BURST) == DMA_MBURST_INC8) || \
1327 ((BURST) == DMA_MBURST_INC16))
1328
1329#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
1330 ((BURST) == DMA_PBURST_INC4) || \
1331 ((BURST) == DMA_PBURST_INC8) || \
1332 ((BURST) == DMA_PBURST_INC16))
1337/* Private functions ---------------------------------------------------------*/
1355#ifdef __cplusplus
1356}
1357#endif
1358
1359#endif /* STM32H7xx_HAL_DMA_H */
1360
__IO
#define __IO
Definition: core_cm4.h:239
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_DMA_StateTypeDef
HAL_DMA_StateTypeDef
HAL DMA State structures definition.
Definition: stm32h7xx_hal_dma.h:103
HAL_DMA_LevelCompleteTypeDef
HAL_DMA_LevelCompleteTypeDef
HAL DMA Transfer complete level structure definition.
Definition: stm32h7xx_hal_dma.h:115
HAL_DMA_CallbackIDTypeDef
HAL_DMA_CallbackIDTypeDef
HAL DMA Callbacks IDs structure definition.
Definition: stm32h7xx_hal_dma.h:124
HAL_DMA_STATE_RESET
@ HAL_DMA_STATE_RESET
Definition: stm32h7xx_hal_dma.h:104
HAL_DMA_STATE_ERROR
@ HAL_DMA_STATE_ERROR
Definition: stm32h7xx_hal_dma.h:107
HAL_DMA_STATE_READY
@ HAL_DMA_STATE_READY
Definition: stm32h7xx_hal_dma.h:105
HAL_DMA_STATE_ABORT
@ HAL_DMA_STATE_ABORT
Definition: stm32h7xx_hal_dma.h:108
HAL_DMA_STATE_BUSY
@ HAL_DMA_STATE_BUSY
Definition: stm32h7xx_hal_dma.h:106
HAL_DMA_FULL_TRANSFER
@ HAL_DMA_FULL_TRANSFER
Definition: stm32h7xx_hal_dma.h:116
HAL_DMA_HALF_TRANSFER
@ HAL_DMA_HALF_TRANSFER
Definition: stm32h7xx_hal_dma.h:117
HAL_DMA_XFER_M1CPLT_CB_ID
@ HAL_DMA_XFER_M1CPLT_CB_ID
Definition: stm32h7xx_hal_dma.h:127
HAL_DMA_XFER_ABORT_CB_ID
@ HAL_DMA_XFER_ABORT_CB_ID
Definition: stm32h7xx_hal_dma.h:130
HAL_DMA_XFER_ERROR_CB_ID
@ HAL_DMA_XFER_ERROR_CB_ID
Definition: stm32h7xx_hal_dma.h:129
HAL_DMA_XFER_HALFCPLT_CB_ID
@ HAL_DMA_XFER_HALFCPLT_CB_ID
Definition: stm32h7xx_hal_dma.h:126
HAL_DMA_XFER_CPLT_CB_ID
@ HAL_DMA_XFER_CPLT_CB_ID
Definition: stm32h7xx_hal_dma.h:125
HAL_DMA_XFER_M1HALFCPLT_CB_ID
@ HAL_DMA_XFER_M1HALFCPLT_CB_ID
Definition: stm32h7xx_hal_dma.h:128
HAL_DMA_XFER_ALL_CB_ID
@ HAL_DMA_XFER_ALL_CB_ID
Definition: stm32h7xx_hal_dma.h:131
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
stm32h7xx_hal_dma_ex.h
Header file of DMA HAL extension module.
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_InitTypeDef
DMA Configuration Structure definition.
Definition: stm32h7xx_hal_dma.h:50
DMA_InitTypeDef::Direction
uint32_t Direction
Definition: stm32h7xx_hal_dma.h:54
DMA_InitTypeDef::PeriphDataAlignment
uint32_t PeriphDataAlignment
Definition: stm32h7xx_hal_dma.h:64
DMA_InitTypeDef::FIFOThreshold
uint32_t FIFOThreshold
Definition: stm32h7xx_hal_dma.h:83
DMA_InitTypeDef::PeriphBurst
uint32_t PeriphBurst
Definition: stm32h7xx_hal_dma.h:92
DMA_InitTypeDef::PeriphInc
uint32_t PeriphInc
Definition: stm32h7xx_hal_dma.h:58
DMA_InitTypeDef::MemInc
uint32_t MemInc
Definition: stm32h7xx_hal_dma.h:61
DMA_InitTypeDef::Request
uint32_t Request
Definition: stm32h7xx_hal_dma.h:51
DMA_InitTypeDef::MemDataAlignment
uint32_t MemDataAlignment
Definition: stm32h7xx_hal_dma.h:67
DMA_InitTypeDef::FIFOMode
uint32_t FIFOMode
Definition: stm32h7xx_hal_dma.h:78
DMA_InitTypeDef::MemBurst
uint32_t MemBurst
Definition: stm32h7xx_hal_dma.h:86
DMA_InitTypeDef::Mode
uint32_t Mode
Definition: stm32h7xx_hal_dma.h:70
DMA_InitTypeDef::Priority
uint32_t Priority
Definition: stm32h7xx_hal_dma.h:75
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32h7xx_hal_dma.h:138
__DMA_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_dma.h:143
__DMA_HandleTypeDef::DMAmuxRequestGenStatus
DMAMUX_RequestGenStatus_TypeDef * DMAmuxRequestGenStatus
Definition: stm32h7xx_hal_dma.h:176
__DMA_HandleTypeDef::DMAmuxChannel
DMAMUX_Channel_TypeDef * DMAmuxChannel
Definition: stm32h7xx_hal_dma.h:167
__DMA_HandleTypeDef::XferAbortCallback
void(* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:159
__DMA_HandleTypeDef::DMAmuxChannelStatusMask
uint32_t DMAmuxChannelStatusMask
Definition: stm32h7xx_hal_dma.h:171
__DMA_HandleTypeDef::Init
DMA_InitTypeDef Init
Definition: stm32h7xx_hal_dma.h:141
__DMA_HandleTypeDef::StreamIndex
uint32_t StreamIndex
Definition: stm32h7xx_hal_dma.h:165
__DMA_HandleTypeDef::XferCpltCallback
void(* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:149
__DMA_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_dma.h:161
__DMA_HandleTypeDef::DMAmuxRequestGen
DMAMUX_RequestGen_TypeDef * DMAmuxRequestGen
Definition: stm32h7xx_hal_dma.h:174
__DMA_HandleTypeDef::XferErrorCallback
void(* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:157
__DMA_HandleTypeDef::State
__IO HAL_DMA_StateTypeDef State
Definition: stm32h7xx_hal_dma.h:145
__DMA_HandleTypeDef::DMAmuxChannelStatus
DMAMUX_ChannelStatus_TypeDef * DMAmuxChannelStatus
Definition: stm32h7xx_hal_dma.h:169
__DMA_HandleTypeDef::Instance
void * Instance
Definition: stm32h7xx_hal_dma.h:139
__DMA_HandleTypeDef::XferHalfCpltCallback
void(* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:151
__DMA_HandleTypeDef::StreamBaseAddress
uint32_t StreamBaseAddress
Definition: stm32h7xx_hal_dma.h:163
__DMA_HandleTypeDef::XferM1HalfCpltCallback
void(* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:155
__DMA_HandleTypeDef::XferM1CpltCallback
void(* XferM1CpltCallback)(struct __DMA_HandleTypeDef *hdma)
Definition: stm32h7xx_hal_dma.h:153
__DMA_HandleTypeDef::DMAmuxRequestGenStatusMask
uint32_t DMAmuxRequestGenStatusMask
Definition: stm32h7xx_hal_dma.h:178
__DMA_HandleTypeDef::Parent
void * Parent
Definition: stm32h7xx_hal_dma.h:147
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