29#ifndef _RTEMS_SCORE_SH_H
30#define _RTEMS_SCORE_SH_H
49#if defined(__SH2E__) || defined(__SH3E__)
54#elif defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
61#define SH4_USE_X_REGISTERS 0
63#if defined(__LITTLE_ENDIAN__)
67#warning FPU not supported
71#elif defined(__sh1__) || defined(__sh2__) || defined(__sh3__)
74#warning Cannot detect FPU support, assuming no FPU
80#define CPU_MODEL_NAME "SH-Multilib"
87#ifndef SH_HAS_SEPARATE_STACKS
88#define SH_HAS_SEPARATE_STACKS 1
95#define CPU_NAME "Hitachi SH"
99#if defined(__sh1__) || defined(__sh2__)
104#define SH_IRQDIS_VALUE 0xf0
106#define sh_disable_interrupts( _level ) \
111 : "r" (SH_IRQDIS_VALUE) );
113#define sh_enable_interrupts( _level ) \
114 __asm__ volatile( "ldc %0,sr\n\t" \
125#define sh_flash_interrupts( _level ) \
131 : : "r" (SH_IRQDIS_VALUE), "r" (_level) );
135#define SH_IRQDIS_MASK 0xf0
137#define sh_disable_interrupts( _level ) \
144 : "r" (SH_IRQDIS_MASK) \
147#define sh_enable_interrupts( _level ) \
148 __asm__ volatile( "ldc %0,sr\n\t" \
159#define sh_flash_interrupts( _level ) \
167 : : "r" (SH_IRQDIS_MASK), "r" (_level) : "r5");
171#define sh_get_interrupt_level( _level ) \
175 __asm__ volatile( "stc sr, %0" : "=r" (_tmpsr) ); \
176 _level = (_tmpsr & 0xf0) >> 4 ; \
179#define sh_set_interrupt_level( _newlevel ) \
183 __asm__ volatile ( "stc sr, %0" : "=r" (_tmpsr) ); \
184 _tmpsr = ( _tmpsr & ~0xf0 ) | ((_newlevel) << 4) ; \
185 __asm__ volatile( "ldc %0,sr" :: "r" (_tmpsr) ); \
193static inline uint32_t sh_swap_u32(
209static inline uint16_t sh_swap_u16(
215 __asm__
volatile (
"swap.b %1,%0" :
"=r" (swapped) :
"r" (value) );
220#define CPU_swap_u32( value ) sh_swap_u32( value )
221#define CPU_swap_u16( value ) sh_swap_u16( value )
223extern unsigned int sh_set_irq_priority(
237#define SH4_SR_MD 0x40000000
238#define SH4_SR_RB 0x20000000
239#define SH4_SR_BL 0x10000000
240#define SH4_SR_FD 0x00008000
241#define SH4_SR_M 0x00000200
243#define SH4_SR_Q 0x00000100
245#define SH4_SR_IMASK 0x000000f0
246#define SH4_SR_IMASK_S 4
247#define SH4_SR_S 0x00000002
251#define SH4_SR_T 0x00000001
252#define SH4_SR_RESERV 0x8fff7d0d
255#define SH4_FPSCR_FR 0x00200000
256#define SH4_FPSCR_SZ 0x00100000
257#define SH4_FPSCR_PR 0x00080000
260#define SH4_FPSCR_DN 0x00040000
261#define SH4_FPSCR_CAUSE 0x0003f000
262#define SH4_FPSCR_CAUSE_S 12
263#define SH4_FPSCR_ENABLE 0x00000f80
264#define SH4_FPSCR_ENABLE_s 7
265#define SH4_FPSCR_FLAG 0x0000007d
266#define SH4_FPSCR_FLAG_S 2
267#define SH4_FPSCR_RM 0x00000001
269#define SH4_FPSCR_RESERV 0xffd00000