RTEMS 6.1-rc4
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reg_spi.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from SPI.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_SPI
50#define LIBBSP_ARM_TMS570_SPI
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t GCR0; /*SPI Global Control Register 0*/
56 uint32_t GCR1; /*SPI Global Control Register 1*/
57 uint32_t INT0; /*SPI Interrupt Register*/
58 uint32_t LVL; /*SPI Interrupt Level Register*/
59 uint32_t FLG; /*SPI Flag Register*/
60 uint32_t PC0; /*SPI Pin Control Register 0*/
61 uint32_t PC1; /*SPI Pin Control Register 1*/
62 uint32_t PC2; /*SPI Pin Control Register 2*/
63 uint32_t PC3; /*SPI Pin Control Register 3*/
64 uint32_t PC4; /*SPI Pin Control Register 4*/
65 uint32_t PC5; /*SPI Pin Control Register 5*/
66 uint32_t PC6; /*SPI Pin Control Register 6*/
67 uint32_t PC7; /*SPI Pin Control Register 7*/
68 uint32_t PC8; /*SPI Pin Control Register 8*/
69 uint32_t DAT0; /*SPI Transmit Data Register 0*/
70 uint32_t DAT1; /*SPI Transmit Data Register 1*/
71 uint32_t BUF; /*SPI Receive Buffer Register*/
72 uint32_t EMU; /*SPI Emulation Register*/
73 uint32_t DELAY; /*SPI Delay Register*/
74 uint32_t DEF; /*SPI Default Chip Select Register*/
75 uint32_t FMT0; /*SPI Data Format Register 0*/
76 uint32_t FMT1; /*SPI Data Format Register 1*/
77 uint32_t FMT2; /*SPI Data Format Register 2*/
78 uint32_t FMT3; /*SPI Data Format Register 3*/
79 uint32_t INTVECT0; /*Interrupt Vector 0*/
80 uint32_t INTVECT1; /*Interrupt Vector 1*/
81 uint8_t reserved1 [4];
82 uint32_t PMCTRL; /*Parallel/Modulo Mode Control Register*/
83 uint32_t MIBSPIE; /*Multi-buffer Mode Enable Register*/
84 uint32_t TGITENST; /*TG Interrupt Enable Set Register*/
85 uint32_t TGITENCR; /*TG Interrupt Enable Clear Register*/
86 uint32_t TGITLVST; /*Transfer Group Interrupt Level Set Register*/
87 uint32_t TGITLVCR; /*Transfer Group Interrupt Level Clear Register*/
88 uint32_t TGINTFLG; /*Transfer Group Interrupt Flag Register*/
89 uint8_t reserved2 [8];
90 uint32_t TICKCNT; /*Tick Count Register*/
91 uint32_t LTGPEND; /*Last TG End Pointer*/
92 uint32_t TGCTRL[16]; /*TG Control Registers*/
93 uint32_t DMACTRL[8]; /*DMA Channel Control Register*/
94 uint32_t DMACOUNT[8]; /*DMA COUNT Register*/
95 uint32_t DMACNTLEN; /*DMA Large Count*/
96 uint8_t reserved3 [4];
97 uint32_t UERRCTRL; /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/
98 uint32_t UERRSTAT; /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/
99 uint32_t UERRADDRRX; /*RXRAM Uncorrectable Parity Error Address Register*/
100 uint32_t UERRADDRTX; /*TXRAM Uncorrectable Parity Error Address Register*/
101 uint32_t RXOVRN_BUF_ADDR; /*RXRAM Overrun Buffer Address Register*/
102 uint32_t IOLPBKTSTCR; /*I/O Loopback Test Control Register*/
103 uint32_t EXT_PRESCALE1; /*SPI Extended Prescale Register 1*/
104 uint32_t EXT_PRESCALE2; /*SPI Extended Prescale Register 2*/
105} tms570_spi_t;
106
107
108/*----------------------TMS570_SPI_GCR0----------------------*/
109/* field: nRESET - This is the local reset control for the module. */
110#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0)
111
112
113/*----------------------TMS570_SPI_GCR1----------------------*/
114/* field: SPIEN - SPI enable. This bit enables SPI transfers. */
115#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24)
116
117/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
118#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16)
119
120/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
121#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8)
122
123/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
124#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1)
125
126/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
127#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0)
128
129
130/*----------------------TMS570_SPI_INT0----------------------*/
131/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
132#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24)
133
134/* field: DMAREQEN - DMA request enable. */
135#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16)
136
137
138/*-----------------------TMS570_SPI_LVL-----------------------*/
139/* field: TXINTLVL - Transmit interrupt level. */
140#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9)
141
142/* field: RXINTLVL - Receive interrupt level. */
143#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8)
144
145/* field: RXOVRNINTLVL - Receive overrun interrupt level. */
146#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6)
147
148/* field: BITERRLVL - Bit error interrupt level. */
149#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4)
150
151/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
152#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3)
153
154/* field: PARERRLVL - Parity error interrupt level. */
155#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2)
156
157/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
158#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1)
159
160/* field: DLENERRLVL - Data length error interrupt level (line) select. */
161#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0)
162
163
164/*-----------------------TMS570_SPI_FLG-----------------------*/
165/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
166#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24)
167
168/* field: TXINTFLG - Transmitter-empty interrupt flag. */
169#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9)
170
171/* field: RXINTFLG - Receiver-full interrupt flag. */
172#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8)
173
174/* field: RXOVRNINTFLG - Receiver overrun flag. */
175#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6)
176
177/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
178#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4)
179
180/* field: DESYNCFLG - Desynchronization of slave device. */
181#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3)
182
183/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
184#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2)
185
186/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
187#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1)
188
189/* field: DLENERRFLG - Data-length error flag. */
190#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0)
191
192
193/*-----------------------TMS570_SPI_PC0-----------------------*/
194/* field: SOMIFUN - Slave out, master in function. */
195#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
196#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
197#define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
198
199/* field: SIMOFUN - Slave in, master out function. */
200#define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23)
201#define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23)
202#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
203
204/* field: SOMIFUN0 - SOMIFUN0 */
205#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11)
206
207/* field: SIMOFUN0 - Slave in, master out function. */
208#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10)
209
210/* field: CLKFUN - CLKFUN */
211#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9)
212
213/* field: ENAFUN - SPIENA function. */
214#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8)
215
216/* field: SCSFUN - SPISCSx function. */
217#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
218#define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7)
219#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
220
221
222/*-----------------------TMS570_SPI_PC1-----------------------*/
223/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
224#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
225#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
226#define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
227
228/* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */
229#define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23)
230#define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23)
231#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
232
233/* field: SOMIDIR0 - PISOMI0 direction. */
234#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11)
235
236/* field: SIMODIR0 - SPISIMO0 direction. */
237#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10)
238
239/* field: CLKDIR - SPICLK direction. */
240#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9)
241
242/* field: ENADIR - SPIENA direction. */
243#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8)
244
245/* field: SCSDIR - SPISCSx direction. */
246#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
247#define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7)
248#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
249
250
251/*-----------------------TMS570_SPI_PC2-----------------------*/
252/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
253#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
254#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
255#define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
256
257/* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */
258#define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23)
259#define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23)
260#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
261
262/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
263#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11)
264
265/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
266#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10)
267
268/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
269#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9)
270
271/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
272#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8)
273
274/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
275#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
276#define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7)
277#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
278
279
280/*-----------------------TMS570_SPI_PC3-----------------------*/
281/* field: SOMIDOUT - SPISOMIx data out write. */
282#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
283#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
284#define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
285
286/* field: SIMODOUT - SPISIMOx data out write. */
287#define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23)
288#define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23)
289#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
290
291/* field: SOMIDOUT0 - SPISOMI0 data out write. */
292#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11)
293
294/* field: SIMODOUT0 - SPISIMO0 data out write. */
295#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10)
296
297/* field: CLKDOUT - SPICLK data out write. */
298#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9)
299
300/* field: ENADOUT - SPIENA data out write. */
301#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8)
302
303/* field: SCSDOUT - SPISCSx data out write. */
304#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
305#define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
306#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
307
308
309/*-----------------------TMS570_SPI_PC4-----------------------*/
310/* field: SOMISET - SPISOMIx data out set. */
311#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
312#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
313#define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
314
315/* field: SIMOSET - SPISIMOx data out set. */
316#define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23)
317#define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23)
318#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
319
320/* field: SOMISET0 - SPISOMI0 data out set. */
321#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11)
322
323/* field: SIMOSET0 - purpose */
324#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10)
325
326/* field: CLKSET - SPICLK data out set. */
327#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9)
328
329/* field: ENASET - SPIENA data out set. */
330#define TMS570_SPI_PC4_ENASET BSP_BIT32(8)
331
332/* field: SCSSET - SPISCSx data out set. */
333#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
334#define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7)
335#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
336
337
338/*-----------------------TMS570_SPI_PC5-----------------------*/
339/* field: SOMICLR - SPISOMIx data out clear. */
340#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
341#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
342#define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
343
344/* field: SIMOCLR - SPISIMOx data out clear. */
345#define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23)
346#define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23)
347#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
348
349/* field: SOMICLR0 - SPISOMI0 data out cleart. */
350#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11)
351
352/* field: SIMOCLR0 - SPISIMO0 data out clear. */
353#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10)
354
355/* field: CLKCLR - SPICLK data out clear. */
356#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9)
357
358/* field: ENACLR - SPIENA data out clear. */
359#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8)
360
361/* field: SCSCLR - SPISCSx data out clear. */
362#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
363#define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
364#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
365
366
367/*-----------------------TMS570_SPI_PC6-----------------------*/
368/* field: SOMIPDR - SPISOMIx open drain enable. */
369#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
370#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
371#define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
372
373/* field: SIMOPDR - SPISIMOx open drain enable. */
374#define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23)
375#define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23)
376#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
377
378/* field: SOMIPDR0 - SOMI0 open-drain enable. */
379#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11)
380
381/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
382#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10)
383
384/* field: CLKPDR - CLK open drain enable. */
385#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9)
386
387/* field: ENAPDR - SPIENA pin open drain enable. */
388#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8)
389
390/* field: SCSPDR - SPISCSx open drain enable. */
391#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
392#define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7)
393#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
394
395
396/*-----------------------TMS570_SPI_PC7-----------------------*/
397/* field: SOMIDIS - SOMIx pull control enable/disable. */
398#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
399#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
400#define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
401
402/* field: SIMODIS - SIMOx pull control enable/disable. */
403#define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23)
404#define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23)
405#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
406
407/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
408#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11)
409
410/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
411#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10)
412
413/* field: CLKPDIS - CLK pull control enable/disable. */
414#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9)
415
416/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
417#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8)
418
419/* field: SCSPDIS - SCSx pull control enable/disable. */
420#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
421#define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
422#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
423
424
425/*-----------------------TMS570_SPI_PC8-----------------------*/
426/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
427#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
428#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
429#define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
430
431/* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */
432#define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23)
433#define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23)
434#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
435
436/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
437#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11)
438
439/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
440#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10)
441
442/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
443#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9)
444
445/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
446#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8)
447
448/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
449#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
450#define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7)
451#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
452
453
454/*----------------------TMS570_SPI_DAT0----------------------*/
455/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
456#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
457#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
458#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
459
460
461/*----------------------TMS570_SPI_DAT1----------------------*/
462/* field: CSHOLD - Chip select hold mode. */
463#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28)
464
465/* field: WDEL - Enable the delay counter at the end of the current transaction. */
466#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26)
467
468/* field: DFSEL - Data word format select */
469#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
470#define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25)
471#define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
472
473/* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */
474#define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23)
475#define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
476#define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
477
478/* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */
479#define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15)
480#define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
481#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
482
483
484/*-----------------------TMS570_SPI_BUF-----------------------*/
485/* field: RXEMPTY - Receive data buffer empty. */
486#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31)
487
488/* field: RXOVR - Receive data buffer overrun. */
489#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30)
490
491/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
492#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29)
493
494/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
495#define TMS570_SPI_BUF_BITERR BSP_BIT32(28)
496
497/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
498#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27)
499
500/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
501#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26)
502
503/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
504#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25)
505
506/* field: DLENERR - Data length error flag. */
507#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24)
508
509/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
510#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
511#define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
512#define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
513
514/* field: RXDATA - SPI receive data. */
515#define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15)
516#define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
517#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
518
519
520/*-----------------------TMS570_SPI_EMU-----------------------*/
521/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
522#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
523#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
524#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
525
526
527/*----------------------TMS570_SPI_DELAY----------------------*/
528/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
529#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
530#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
531#define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
532
533/* field: T2CDELAY - T2CDELAY */
534#define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23)
535#define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23)
536#define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
537
538/* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */
539#define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15)
540#define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15)
541#define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
542
543/* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */
544#define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7)
545#define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7)
546#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
547
548
549/*-----------------------TMS570_SPI_DEF-----------------------*/
550/* field: CDEF - Chip select default pattern. Master-mode only. */
551#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
552#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
553#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
554
555
556/*----------------------TMS570_SPI_FMTx----------------------*/
557/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
558#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31)
559#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
560#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
561
562/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
563#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23)
564
565/* field: PARITYENA - Parity enable for data format x. */
566#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22)
567
568/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
569#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21)
570
571/* field: SHIFTDIR - Shift direction for data format x. */
572#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20)
573
574/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
575#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19)
576
577/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
578#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18)
579
580/* field: POLARITY - POLARITY */
581#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17)
582
583/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
584#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16)
585
586/* field: PRESCALE - SPI data format x prescaler. */
587#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15)
588#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
589#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
590
591/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
592#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4)
593#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
594#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
595
596
597/*--------------------TMS570_SPI_INTVECT0--------------------*/
598/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
599#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
600#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
601#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
602
603/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
604#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0)
605
606
607/*--------------------TMS570_SPI_INTVECT1--------------------*/
608/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
609#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
610#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
611#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
612
613/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
614#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0)
615
616
617/*---------------------TMS570_SPI_PMCTRL---------------------*/
618/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
619#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29)
620
621/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
622#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
623#define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28)
624#define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28)
625
626/* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
627#define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25)
628#define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25)
629#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
630
631/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
632#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21)
633
634/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
635#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
636#define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20)
637#define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20)
638
639/* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
640#define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17)
641#define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17)
642#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
643
644/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
645#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13)
646
647/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
648#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
649#define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12)
650#define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12)
651
652/* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
653#define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9)
654#define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9)
655#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
656
657/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
658#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5)
659
660/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
661#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
662#define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4)
663#define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4)
664
665/* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
666#define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1)
667#define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1)
668#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
669
670
671/*---------------------TMS570_SPI_MIBSPIE---------------------*/
672/* field: RXRAM_ACCESS - Receive-RAM access control. */
673#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16)
674
675/* field: MSPIENA - Multi-buffer mode enable. */
676#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0)
677
678
679/*--------------------TMS570_SPI_TGITENST--------------------*/
680/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
681#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
682#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
683#define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
684
685/* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */
686#define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15)
687#define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
688#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
689
690
691/*--------------------TMS570_SPI_TGITENCR--------------------*/
692/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
693#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
694#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
695#define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
696
697/* field: CLR_INTENSUS - CLR INTENSUS */
698#define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15)
699#define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
700#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
701
702
703/*--------------------TMS570_SPI_TGITLVST--------------------*/
704/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
705#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
706#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
707#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
708
709/* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */
710#define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15)
711#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
712#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
713
714
715/*--------------------TMS570_SPI_TGITLVCR--------------------*/
716/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
717#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
718#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
719#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
720
721/* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */
722#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15)
723#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
724#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
725
726
727/*--------------------TMS570_SPI_TGINTFLG--------------------*/
728/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
729#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
730#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
731#define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
732
733/* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */
734#define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15)
735#define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
736#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
737
738
739/*---------------------TMS570_SPI_TICKCNT---------------------*/
740/* field: TICKENA - Tick counter enable. */
741#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31)
742
743/* field: RELOAD - Pre-load the tick counter. */
744#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30)
745
746/* field: CLKCTRL - Tick counter clock source control. */
747#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
748#define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29)
749#define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
750
751/* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */
752#define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15)
753#define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15)
754#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
755
756
757/*---------------------TMS570_SPI_LTGPEND---------------------*/
758/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
759#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
760#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
761#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
762
763/* field: LPEND - Last TG end pointer. */
764#define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14)
765#define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14)
766#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
767
768
769/*---------------------TMS570_SPI_TGCTRL---------------------*/
770/* field: TGENA - TGx enable. */
771#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31)
772
773/* field: ONESHOTx - Single transfer for TGx. */
774#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30)
775
776/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
777#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29)
778
779/* field: TGTDx - TG triggered. */
780#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28)
781
782
783/*---------------------TMS570_SPI_DMACTRL---------------------*/
784/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
785#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31)
786
787/* field: BUFIDx - Buffer utilized for DMA transfer. */
788#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
789#define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30)
790#define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
791
792/* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
793#define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23)
794#define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23)
795#define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
796
797/* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
798#define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19)
799#define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19)
800#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
801
802/* field: RXDMAENAx - Receive data DMA channel enable. */
803#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15)
804
805/* field: TXDAMENAx - Transmit data DMA channel enable. */
806#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14)
807
808/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
809#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13)
810
811/* field: ICOUNTx - Initial count of DMA transfers. */
812#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
813#define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12)
814#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
815
816/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
817#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6)
818
819/* field: COUNTx - Actual number of remaining DMA transfers. */
820#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
821#define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5)
822#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
823
824
825/*--------------------TMS570_SPI_DMACOUNT--------------------*/
826/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
827#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
828#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
829#define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
830
831/* field: COUNTx - The actual number of remaining DMA transfers. */
832#define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15)
833#define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15)
834#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
835
836
837/*--------------------TMS570_SPI_DMACNTLEN--------------------*/
838/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
839#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0)
840
841
842/*--------------------TMS570_SPI_UERRCTRL--------------------*/
843/* field: PTESTEN - Parity memory test enable. */
844#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8)
845
846/* field: EDEN - Error detection enable. These bits enable parity error detection. */
847#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
848#define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3)
849#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
850
851
852/*--------------------TMS570_SPI_UERRSTAT--------------------*/
853/* field: EDFLG1 - RXRAM. */
854#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1)
855
856/* field: EDFLG0 - Uncorrectable parity error detection flag. */
857#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0)
858
859
860/*-------------------TMS570_SPI_UERRADDRRX-------------------*/
861/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
862#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
863#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
864#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
865
866
867/*-------------------TMS570_SPI_UERRADDRTX-------------------*/
868/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
869#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
870#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
871#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
872
873
874/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/
875/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
876#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
877#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
878#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
879
880
881/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/
882/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
883#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24)
884
885/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
886#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20)
887
888/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
889#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19)
890
891/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
892#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18)
893
894/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
895#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17)
896
897/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
898#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16)
899
900/* field: IOLPBKSTENA - Module I/O loopback test enable key. */
901#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
902#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
903#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
904
905/* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */
906#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5)
907#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5)
908#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
909
910/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
911#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2)
912
913/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
914#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1)
915
916/* field: RXP_ENA - Enable analog loopback through the receive pin. */
917#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0)
918
919
920/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/
921/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */
922#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26)
923#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26)
924#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
925
926
927
928#endif /* LIBBSP_ARM_TMS570_SPI */
utility.h
This header file provides utility macros for BSPs.
tms570_spi_t
Definition: reg_spi.h:54
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