RTEMS 6.1-rc4
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reg_adc.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/* The header file is generated by make_header.py from ADC.json */
12/* Current script's version can be found at: */
13/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15/*
16 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17 *
18 * Czech Technical University in Prague
19 * Zikova 1903/4
20 * 166 36 Praha 6
21 * Czech Republic
22 *
23 * All rights reserved.
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions are met:
27 *
28 * 1. Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following disclaimer.
30 * 2. Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following disclaimer in the documentation
32 * and/or other materials provided with the distribution.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * The views and conclusions contained in the software and documentation are those
46 * of the authors and should not be interpreted as representing official policies,
47 * either expressed or implied, of the FreeBSD Project.
48*/
49#ifndef LIBBSP_ARM_TMS570_ADC
50#define LIBBSP_ARM_TMS570_ADC
51
52#include <bsp/utility.h>
53
54typedef struct{
55 uint32_t BUF0; /*Group 0-2 result buffer 0 register*/
56 uint32_t BUF1; /*Group 0-2 result buffer 1 register*/
57 uint32_t BUF2; /*Group 0-2 result buffer 2 register*/
58 uint32_t BUF3; /*Group 0-2 result buffer 3 register*/
59 uint32_t BUF4; /*Group 0-2 result buffer 4 register*/
60 uint32_t BUF5; /*Group 0-2 result buffer 5 register*/
61 uint32_t BUF6; /*Group 0-2 result buffer 6 register*/
62 uint32_t BUF7; /*Group 0-2 result buffer 7 register*/
63} tms570_gxbuf_t;
64
65typedef struct{
66 uint32_t RSTCR; /*ADC Reset Control Register*/
67 uint32_t OPMODECR; /*ADC Operating Mode Control Register*/
68 uint32_t CLOCKCR; /*ADC Clock Control Register*/
69 uint32_t CALCR; /*ADC Calibration Mode Control Register*/
70 uint32_t GxMODECR[3]; /*ADC Event Group Operating Mode Control Register*/
71 uint32_t EVSRC; /*ADC Trigger Source Select Register*/
72 uint32_t G1SRC; /*ADC Group1 Trigger Source Select Register*/
73 uint32_t G2SRC; /*ADC Group2 Trigger Source Select Register*/
74 uint32_t GxINTENA[3]; /*ADC Event Interrupt Enable Control Register*/
75 uint32_t GxINTFLG[3]; /*ADC Event Group Interrupt Flag Register*/
76 uint32_t GxINTCR[3]; /*ADC Event Group Threshold Interrupt Control Register*/
77 uint32_t EVDMACR; /*ADC Event Group DMA Control Register*/
78 uint32_t G1DMACR; /*ADC Group1 DMA Control Register*/
79 uint32_t G2DMACR; /*ADC Group2 DMA Control Register*/
80 uint32_t BNDCR; /*ADC Results Memory Configuration Register*/
81 uint32_t BNDEND; /*ADC Results Memory Size Configuration Register*/
82 uint32_t EVSAMP; /*ADC Event Group Sampling Time Configuration Register*/
83 uint32_t G1SAMP; /*ADC Group1 Sampling Time Configuration Register()*/
84 uint32_t G2SAMP; /*ADC Group2 Sampling Time Configuration Register*/
85 uint32_t EVSR; /*ADC Event Group Status Register*/
86 uint32_t G1SR; /*ADC Group1 Status Register*/
87 uint32_t G2SR; /*ADC Group2 Status Register*/
88 uint32_t GxSEL[3]; /*ADC Event Group Channel Select Register*/
89 uint32_t CALR; /*ADC Calibration and Error Offset Correction Register*/
90 uint32_t SMSTATE; /*ADC State Machine Status Register*/
91 uint32_t LASTCONV; /*ADC Channel Last Conversion Value Register*/
92 tms570_gxbuf_t GxBUF[3]; /*ADC Event Group Results Emulation FIFO Register*/
93 uint32_t EVEMUBUFFER; /*ADC Event Group Results Emulation FIFO Register*/
94 uint32_t G1EMUBUFFER; /*ADC Group1 Results Emulation FIFO Register*/
95 uint32_t G2EMUBUFFER; /*ADC Group2 Results Emulation FIFO Register*/
96 uint32_t EVTDIR; /*ADC ADEVT Pin Direction Control Register*/
97 uint32_t EVTOUT; /*ADC ADEVT Pin Output Value Control Register*/
98 uint32_t EVTIN; /*ADC ADEVT Pin Input Value Register*/
99 uint32_t EVTSET; /*ADC ADEVT Pin Set Register*/
100 uint32_t EVTCLR; /*ADC ADEVT Pin Clear Register*/
101 uint32_t EVTPDR; /*ADC ADEVT Pin Open Drain Enable Register*/
102 uint32_t EVTPDIS; /*ADC ADEVT Pin Pull Control Disable Register*/
103 uint32_t EVTPSEL; /*ADC ADEVT Pin Pull Control Select Register*/
104 uint32_t EVSAMPDISEN; /*ADC Event Group Sample Cap Discharge Control Register*/
105 uint32_t G1SAMPDISEN; /*ADC Group1 Sample Cap Discharge Control Register*/
106 uint32_t G2SAMPDISEN; /*ADC Group2 Sample Cap Discharge Control Register*/
107 uint32_t MAGINTCR1; /*ADC Magnitude Compare Interrupt Control Register 2*/
108 uint32_t MAGINT1MASK; /*ADC Magnitude Compare Mask Register 0*/
109 uint32_t MAGINTCR2; /*ADC Magnitude Compare Interrupt Control Register 2*/
110 uint32_t MAGINT2MASK; /*ADC Magnitude Compare Mask Register 0*/
111 uint32_t MAGINTCR3; /*ADC Magnitude Compare Interrupt Control Register 2*/
112 uint32_t MAGINT3MASK; /*ADC Magnitude Compare Mask Register 0*/
113 uint8_t reserved1 [24];
114 uint32_t MAGTHRINTENASET; /*ADC Magnitude Compare Interrupt Enable Set Register*/
115 uint32_t MAGTHRINTENACLR; /*ADC Magnitude Compare Interrupt Enable Clear Register*/
116 uint32_t MAGTHRINTFLG; /*ADC Magnitude Compare Interrupt Flag Register*/
117 uint32_t MAGTHRINTOFFSET; /*ADC Magnitude Compare Interrupt Offset Register*/
118 uint32_t GxFIFORESETCR[3]; /*ADC Event Group FIFO Reset Control Register*/
119 uint32_t EVRAMWRADDR; /*ADC Event Group RAM Write Address Register*/
120 uint32_t G1RAMWRADDR; /*ADC Group1 RAM Write Address Register*/
121 uint32_t G2RAMWRADDR; /*ADC Group2 RAM Write Address Register*/
122 uint32_t PARCR; /*ADC Parity Control Register*/
123 uint32_t PARADDR; /*ADC Parity Error Address Register*/
124 uint32_t PWRUPDLYCTRL; /*ADC Power-Up Delay Control Register*/
125} tms570_adc_t;
126
127
128/*----------------------TMS570_ADC_BUFx----------------------*/
129/* field: G2_EMPTY_10bit_mode - Group2 FIFO Empty. */
130#define TMS570_ADC_BUFx_G2_EMPTY_10bit_mode BSP_BIT32(15)
131
132/* field: G2_CHID_10bit_mode - Group2 Channel Id. */
133#define TMS570_ADC_BUFx_G2_CHID_10bit_mode(val) BSP_FLD32(val,10, 14)
134#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_GET(reg) BSP_FLD32GET(reg,10, 14)
135#define TMS570_ADC_BUFx_G2_CHID_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,10, 14)
136
137/* field: G2_DR_10bit_mode - Group2 Digital Conversion Result. */
138#define TMS570_ADC_BUFx_G2_DR_10bit_mode(val) BSP_FLD32(val,0, 9)
139#define TMS570_ADC_BUFx_G2_DR_10bit_mode_GET(reg) BSP_FLD32GET(reg,0, 9)
140#define TMS570_ADC_BUFx_G2_DR_10bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
141
142/* field: G2_EMPTY_12bit_mode - Group2 FIFO Empty. */
143#define TMS570_ADC_BUFx_G2_EMPTY_12bit_mode BSP_BIT32(31)
144
145/* field: G2_CHID_12bit_mode - Group2 Channel Id. */
146#define TMS570_ADC_BUFx_G2_CHID_12bit_mode(val) BSP_FLD32(val,16, 20)
147#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_GET(reg) BSP_FLD32GET(reg,16, 20)
148#define TMS570_ADC_BUFx_G2_CHID_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,16, 20)
149
150/* field: G2_DR_12bit_mode - Group2 Digital Conversion Result. */
151#define TMS570_ADC_BUFx_G2_DR_12bit_mode(val) BSP_FLD32(val,0, 11)
152#define TMS570_ADC_BUFx_G2_DR_12bit_mode_GET(reg) BSP_FLD32GET(reg,0, 11)
153#define TMS570_ADC_BUFx_G2_DR_12bit_mode_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
154
155
156/*----------------------TMS570_ADC_RSTCR----------------------*/
157/* field: RESET - This bit is used to reset the ADC internal state machines and control/status registers. */
158#define TMS570_ADC_RSTCR_RESET BSP_BIT32(0)
159
160
161/*--------------------TMS570_ADC_OPMODECR--------------------*/
162/* field: 10_12_BIT - This bit controls the resolution of the ADC core. */
163#define TMS570_ADC_OPMODECR_10_12_BIT BSP_BIT32(31)
164
165
166/*---------------------TMS570_ADC_CLOCKCR---------------------*/
167/* field: PS - ADC Clock Prescaler. These bits define the prescaler value for the ADC core clock (ADCLK). */
168#define TMS570_ADC_CLOCKCR_PS(val) BSP_FLD32(val,0, 4)
169#define TMS570_ADC_CLOCKCR_PS_GET(reg) BSP_FLD32GET(reg,0, 4)
170#define TMS570_ADC_CLOCKCR_PS_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
171
172
173/*----------------------TMS570_ADC_CALCR----------------------*/
174/* field: SELF_TEST - ADC Self Test Enable. */
175#define TMS570_ADC_CALCR_SELF_TEST BSP_BIT32(24)
176
177/* field: CAL_ST - ADC Calibration Conversion Start. */
178#define TMS570_ADC_CALCR_CAL_ST BSP_BIT32(16)
179
180/* field: BRIDGE_EN - Bridge Enable. */
181#define TMS570_ADC_CALCR_BRIDGE_EN BSP_BIT32(9)
182
183/* field: HILO - ADC Self Test mode and Calibration Mode Reference Source Selection. */
184#define TMS570_ADC_CALCR_HILO BSP_BIT32(8)
185
186/* field: CAL_EN - ADC Calibration Enable. */
187#define TMS570_ADC_CALCR_CAL_EN BSP_BIT32(0)
188
189
190/*--------------------TMS570_ADC_GxMODECR--------------------*/
191/* field: No_Reset_on_ChnSel - No Event Group Results Memory Reset on New Channel Select. */
192#define TMS570_ADC_GxMODECR_No_Reset_on_ChnSel BSP_BIT32(16)
193
194/* field: EV_DATA_FMT - Event Group Read Data Format. */
195#define TMS570_ADC_GxMODECR_EV_DATA_FMT(val) BSP_FLD32(val,8, 9)
196#define TMS570_ADC_GxMODECR_EV_DATA_FMT_GET(reg) BSP_FLD32GET(reg,8, 9)
197#define TMS570_ADC_GxMODECR_EV_DATA_FMT_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
198
199
200/*----------------------TMS570_ADC_EVSRC----------------------*/
201/* field: EV_EDG_BOTH - rising and falling edge detected on the selected trigger source. */
202#define TMS570_ADC_EVSRC_EV_EDG_BOTH BSP_BIT32(4)
203
204/* field: EV_EDG_SEL - Event Group Trigger Edge Polarity Select. */
205#define TMS570_ADC_EVSRC_EV_EDG_SEL BSP_BIT32(3)
206
207/* field: EV_SRC - Event Group Trigger Source. */
208#define TMS570_ADC_EVSRC_EV_SRC(val) BSP_FLD32(val,0, 2)
209#define TMS570_ADC_EVSRC_EV_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
210#define TMS570_ADC_EVSRC_EV_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
211
212
213/*----------------------TMS570_ADC_G1SRC----------------------*/
214/* field: GI_EDG_BOTH - Group1 Trigger Edge Polarity Select. */
215#define TMS570_ADC_G1SRC_GI_EDG_BOTH BSP_BIT32(4)
216
217/* field: G1_EDG_SEL - Group1 Trigger Edge Polarity Select. */
218#define TMS570_ADC_G1SRC_G1_EDG_SEL BSP_BIT32(3)
219
220/* field: G1_SRC - Group1 Trigger Source. */
221#define TMS570_ADC_G1SRC_G1_SRC(val) BSP_FLD32(val,0, 2)
222#define TMS570_ADC_G1SRC_G1_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
223#define TMS570_ADC_G1SRC_G1_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
224
225
226/*----------------------TMS570_ADC_G2SRC----------------------*/
227/* field: G2_EDG_BOTH - Group2 Trigger Edge Polarity Select. */
228#define TMS570_ADC_G2SRC_G2_EDG_BOTH BSP_BIT32(4)
229
230/* field: G2_EDG_SEL - Group2 Trigger Edge Polarity Select. */
231#define TMS570_ADC_G2SRC_G2_EDG_SEL BSP_BIT32(3)
232
233/* field: G2_SRC - Group2 Trigger Source. */
234#define TMS570_ADC_G2SRC_G2_SRC(val) BSP_FLD32(val,0, 2)
235#define TMS570_ADC_G2SRC_G2_SRC_GET(reg) BSP_FLD32GET(reg,0, 2)
236#define TMS570_ADC_G2SRC_G2_SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
237
238
239/*--------------------TMS570_ADC_GxINTENA--------------------*/
240/* field: EV_END_INT_EN - Event Group Conversion End Interrupt Enable. Please refer to Section 19.5. */
241#define TMS570_ADC_GxINTENA_EV_END_INT_EN BSP_BIT32(3)
242
243/* field: EV_OVR_INT_EN - write a new conversion result to the Event Group results memory which is already full. */
244#define TMS570_ADC_GxINTENA_EV_OVR_INT_EN BSP_BIT32(1)
245
246/* field: EV_THR_INT_EN - Event Group Threshold Interrupt Enable. */
247#define TMS570_ADC_GxINTENA_EV_THR_INT_EN BSP_BIT32(0)
248
249
250/*--------------------TMS570_ADC_GxINTFLG--------------------*/
251/* field: EV_END - Event Group Conversion End. */
252#define TMS570_ADC_GxINTFLG_EV_END BSP_BIT32(3)
253
254/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. This is a read-only bit; writes have no effect. It is not asource of an interrupt from the ADC module. */
255#define TMS570_ADC_GxINTFLG_EV_MEM_EMPTY BSP_BIT32(2)
256
257/* field: EV_MEM_OVERRUN - Event Group Memory Overrun. This is a read-only bit; writes have no effect. */
258#define TMS570_ADC_GxINTFLG_EV_MEM_OVERRUN BSP_BIT32(1)
259
260/* field: EV_THR_INT_FLG - Event Group Threshold Interrupt Flag. */
261#define TMS570_ADC_GxINTFLG_EV_THR_INT_FLG BSP_BIT32(0)
262
263
264/*---------------------TMS570_ADC_GxINTCR---------------------*/
265/* field: Sign_Extension - These bits always read the same as the bit 8 of this register. */
266#define TMS570_ADC_GxINTCR_Sign_Extension(val) BSP_FLD32(val,9, 15)
267#define TMS570_ADC_GxINTCR_Sign_Extension_GET(reg) BSP_FLD32GET(reg,9, 15)
268#define TMS570_ADC_GxINTCR_Sign_Extension_SET(reg,val) BSP_FLD32SET(reg, val,9, 15)
269
270/* field: EV_THR - Event Group Threshold Counter. */
271#define TMS570_ADC_GxINTCR_EV_THR(val) BSP_FLD32(val,0, 8)
272#define TMS570_ADC_GxINTCR_EV_THR_GET(reg) BSP_FLD32GET(reg,0, 8)
273#define TMS570_ADC_GxINTCR_EV_THR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
274
275
276/*---------------------TMS570_ADC_EVDMACR---------------------*/
277/* field: EV_BLOCKS - Number of Event Group Result buffers to be transferred using DMA if the ADC module is */
278#define TMS570_ADC_EVDMACR_EV_BLOCKS(val) BSP_FLD32(val,16, 24)
279#define TMS570_ADC_EVDMACR_EV_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
280#define TMS570_ADC_EVDMACR_EV_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
281
282/* field: DMA_EV_END - Event Group Conversion End DMA Transfer Enable. */
283#define TMS570_ADC_EVDMACR_DMA_EV_END BSP_BIT32(3)
284
285/* field: EV_BLK_XFER - Event Group Block DMA Transfer Enable. */
286#define TMS570_ADC_EVDMACR_EV_BLK_XFER BSP_BIT32(2)
287
288/* field: EV_DMA_EN - Event Group DMA Transfer Enable. */
289#define TMS570_ADC_EVDMACR_EV_DMA_EN BSP_BIT32(0)
290
291
292/*---------------------TMS570_ADC_G1DMACR---------------------*/
293/* field: G1_BLOCKS - Number of Group1 Result buffers to be transferred using DMA if the ADC module is configured */
294#define TMS570_ADC_G1DMACR_G1_BLOCKS(val) BSP_FLD32(val,16, 24)
295#define TMS570_ADC_G1DMACR_G1_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
296#define TMS570_ADC_G1DMACR_G1_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
297
298/* field: DMA_G1_END - Group1 Conversion End DMA Transfer Enable. */
299#define TMS570_ADC_G1DMACR_DMA_G1_END BSP_BIT32(3)
300
301/* field: G1_BLK_XFER - Group1 Block DMA Transfer Enable. */
302#define TMS570_ADC_G1DMACR_G1_BLK_XFER BSP_BIT32(2)
303
304/* field: G1_DMA_EN - Group1 DMA Transfer Enable. */
305#define TMS570_ADC_G1DMACR_G1_DMA_EN BSP_BIT32(0)
306
307
308/*---------------------TMS570_ADC_G2DMACR---------------------*/
309/* field: G2_BLOCKS - Number of Group2 Result buffers to be transferred using DMA if the ADC module is configured */
310#define TMS570_ADC_G2DMACR_G2_BLOCKS(val) BSP_FLD32(val,16, 24)
311#define TMS570_ADC_G2DMACR_G2_BLOCKS_GET(reg) BSP_FLD32GET(reg,16, 24)
312#define TMS570_ADC_G2DMACR_G2_BLOCKS_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
313
314/* field: DMA_G2_END - Group2 Conversion End DMA Transfer Enable. */
315#define TMS570_ADC_G2DMACR_DMA_G2_END BSP_BIT32(3)
316
317/* field: G2_BLK_XFER - Group2 Block DMA Transfer Enable. */
318#define TMS570_ADC_G2DMACR_G2_BLK_XFER BSP_BIT32(2)
319
320/* field: G2_DMA_EN - Group2 DMA Transfer Enable. */
321#define TMS570_ADC_G2DMACR_G2_DMA_EN BSP_BIT32(0)
322
323
324/*----------------------TMS570_ADC_BNDCR----------------------*/
325/* field: BNDA - Buffer Boundary A. */
326#define TMS570_ADC_BNDCR_BNDA(val) BSP_FLD32(val,16, 24)
327#define TMS570_ADC_BNDCR_BNDA_GET(reg) BSP_FLD32GET(reg,16, 24)
328#define TMS570_ADC_BNDCR_BNDA_SET(reg,val) BSP_FLD32SET(reg, val,16, 24)
329
330/* field: BNDB - Buffer Boundary B. */
331#define TMS570_ADC_BNDCR_BNDB(val) BSP_FLD32(val,0, 8)
332#define TMS570_ADC_BNDCR_BNDB_GET(reg) BSP_FLD32GET(reg,0, 8)
333#define TMS570_ADC_BNDCR_BNDB_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
334
335
336/*---------------------TMS570_ADC_BNDEND---------------------*/
337/* field: BUF_INIT_ACTIVE - ADC Results Memory Auto-initialization Status. */
338#define TMS570_ADC_BNDEND_BUF_INIT_ACTIVE BSP_BIT32(16)
339
340/* field: BNDEND - Buffer Boundary End. */
341#define TMS570_ADC_BNDEND_BNDEND(val) BSP_FLD32(val,0, 2)
342#define TMS570_ADC_BNDEND_BNDEND_GET(reg) BSP_FLD32GET(reg,0, 2)
343#define TMS570_ADC_BNDEND_BNDEND_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
344
345
346/*---------------------TMS570_ADC_EVSAMP---------------------*/
347/* field: EV_ACQ - Event Group Acquisition Time. */
348#define TMS570_ADC_EVSAMP_EV_ACQ(val) BSP_FLD32(val,0, 11)
349#define TMS570_ADC_EVSAMP_EV_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
350#define TMS570_ADC_EVSAMP_EV_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
351
352
353/*---------------------TMS570_ADC_G1SAMP---------------------*/
354/* field: G1_ACQ - Group1 Acquisition Time. These bits define the sampling window (SW) for the Group1 conversions. */
355#define TMS570_ADC_G1SAMP_G1_ACQ(val) BSP_FLD32(val,0, 11)
356#define TMS570_ADC_G1SAMP_G1_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
357#define TMS570_ADC_G1SAMP_G1_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
358
359
360/*---------------------TMS570_ADC_G2SAMP---------------------*/
361/* field: G2_ACQ - Group2 Acquisition Time. These bits define the sampling window (SW) for the Group2 conversions. */
362#define TMS570_ADC_G2SAMP_G2_ACQ(val) BSP_FLD32(val,0, 11)
363#define TMS570_ADC_G2SAMP_G2_ACQ_GET(reg) BSP_FLD32GET(reg,0, 11)
364#define TMS570_ADC_G2SAMP_G2_ACQ_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
365
366
367/*----------------------TMS570_ADC_EVSR----------------------*/
368/* field: EV_MEM_EMPTY - Event Group Results Memory Empty. */
369#define TMS570_ADC_EVSR_EV_MEM_EMPTY BSP_BIT32(3)
370
371/* field: EV_BUSY - Event Group Conversion Busy. */
372#define TMS570_ADC_EVSR_EV_BUSY BSP_BIT32(2)
373
374/* field: EV_STOP - Event Group Conversion Stopped. */
375#define TMS570_ADC_EVSR_EV_STOP BSP_BIT32(1)
376
377/* field: EV_END - Event Group Conversions Ended. */
378#define TMS570_ADC_EVSR_EV_END BSP_BIT32(0)
379
380
381/*----------------------TMS570_ADC_G1SR----------------------*/
382/* field: G1_MEM_EMPTY - Group1 Results Memory Empty. */
383#define TMS570_ADC_G1SR_G1_MEM_EMPTY BSP_BIT32(3)
384
385/* field: G1_BUSY - Group1 Conversion Busy. */
386#define TMS570_ADC_G1SR_G1_BUSY BSP_BIT32(2)
387
388/* field: G1_STOP - Group1 Conversion Stopped. */
389#define TMS570_ADC_G1SR_G1_STOP BSP_BIT32(1)
390
391/* field: G1_END - Group1 Conversions Ended. */
392#define TMS570_ADC_G1SR_G1_END BSP_BIT32(0)
393
394
395/*----------------------TMS570_ADC_G2SR----------------------*/
396/* field: G2_MEM_EMPTY - Group2 Results Memory Empty. */
397#define TMS570_ADC_G2SR_G2_MEM_EMPTY BSP_BIT32(3)
398
399/* field: G2_BUSY - Group2 Conversion Busy. */
400#define TMS570_ADC_G2SR_G2_BUSY BSP_BIT32(2)
401
402/* field: G2_STOP - Group2 Conversion Stopped. */
403#define TMS570_ADC_G2SR_G2_STOP BSP_BIT32(1)
404
405/* field: G2_END - Group2 Conversions Ended. */
406#define TMS570_ADC_G2SR_G2_END BSP_BIT32(0)
407
408
409/*----------------------TMS570_ADC_GxSEL----------------------*/
410/* field: EV_SEL - Event Group channels selected. */
411#define TMS570_ADC_GxSEL_EV_SEL(val) BSP_FLD32(val,0, 15)
412#define TMS570_ADC_GxSEL_EV_SEL_GET(reg) BSP_FLD32GET(reg,0, 15)
413#define TMS570_ADC_GxSEL_EV_SEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
414
415
416/*----------------------TMS570_ADC_CALR----------------------*/
417/* field: ADCALR - ADC Calibration Result and Offset Error Correction Value. */
418#define TMS570_ADC_CALR_ADCALR(val) BSP_FLD32(val,0, 11)
419#define TMS570_ADC_CALR_ADCALR_GET(reg) BSP_FLD32GET(reg,0, 11)
420#define TMS570_ADC_CALR_ADCALR_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
421
422
423/*---------------------TMS570_ADC_SMSTATE---------------------*/
424/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
425#define TMS570_ADC_SMSTATE_LAST_CONV(val) BSP_FLD32(val,0, 23)
426#define TMS570_ADC_SMSTATE_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
427#define TMS570_ADC_SMSTATE_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
428
429
430/*--------------------TMS570_ADC_LASTCONV--------------------*/
431/* field: LAST_CONV - ADC Input Channel's Last Converted Value. */
432#define TMS570_ADC_LASTCONV_LAST_CONV(val) BSP_FLD32(val,0, 23)
433#define TMS570_ADC_LASTCONV_LAST_CONV_GET(reg) BSP_FLD32GET(reg,0, 23)
434#define TMS570_ADC_LASTCONV_LAST_CONV_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
435
436
437/*----------------------TMS570_ADC_GxBUF----------------------*/
438/* field: ADEVT_DIR - ADEVT Pin Direction. */
439#define TMS570_ADC_GxBUF_ADEVT_DIR BSP_BIT32(0)
440
441
442/*-------------------TMS570_ADC_EVEMUBUFFER-------------------*/
443/* field: ADEVT_DIR - ADEVT Pin Direction. */
444#define TMS570_ADC_EVEMUBUFFER_ADEVT_DIR BSP_BIT32(0)
445
446
447/*-------------------TMS570_ADC_G1EMUBUFFER-------------------*/
448/* field: ADEVT_DIR - ADEVT Pin Direction. */
449#define TMS570_ADC_G1EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
450
451
452/*-------------------TMS570_ADC_G2EMUBUFFER-------------------*/
453/* field: ADEVT_DIR - ADEVT Pin Direction. */
454#define TMS570_ADC_G2EMUBUFFER_ADEVT_DIR BSP_BIT32(0)
455
456
457/*---------------------TMS570_ADC_EVTDIR---------------------*/
458/* field: ADEVT_DIR - ADEVT Pin Direction. */
459#define TMS570_ADC_EVTDIR_ADEVT_DIR BSP_BIT32(0)
460
461
462/*---------------------TMS570_ADC_EVTOUT---------------------*/
463/* field: ADEVT_OUT - ADEVT Pin Output Value. */
464#define TMS570_ADC_EVTOUT_ADEVT_OUT BSP_BIT32(0)
465
466
467/*----------------------TMS570_ADC_EVTIN----------------------*/
468/* field: ADEVT_IN - ADEVT Pin Input Value. This is a read-only bit which reflects the logic level on the ADEVT pin. */
469#define TMS570_ADC_EVTIN_ADEVT_IN BSP_BIT32(0)
470
471
472/*---------------------TMS570_ADC_EVTSET---------------------*/
473/* field: ADEVT_SET - ADEVT Pin Set. This bit drives the output of the ADEVT pin high. */
474#define TMS570_ADC_EVTSET_ADEVT_SET BSP_BIT32(0)
475
476
477/*---------------------TMS570_ADC_EVTCLR---------------------*/
478/* field: ADEVT_CLR - ADEVT Pin Clear. A read from this bit always returns the current state of the ADEVT pin. */
479#define TMS570_ADC_EVTCLR_ADEVT_CLR BSP_BIT32(0)
480
481
482/*---------------------TMS570_ADC_EVTPDR---------------------*/
483/* field: ADEVT_PDR - ADEVT Pin Open Drain Enable. */
484#define TMS570_ADC_EVTPDR_ADEVT_PDR BSP_BIT32(0)
485
486
487/*---------------------TMS570_ADC_EVTPDIS---------------------*/
488/* field: ADEVT_PDIS - ADEVT Pin Pull Control Disable. */
489#define TMS570_ADC_EVTPDIS_ADEVT_PDIS BSP_BIT32(0)
490
491
492/*---------------------TMS570_ADC_EVTPSEL---------------------*/
493/* field: ADEVT_PSEL - ADEVT Pin Pull Control Select. */
494#define TMS570_ADC_EVTPSEL_ADEVT_PSEL BSP_BIT32(0)
495
496
497/*-------------------TMS570_ADC_EVSAMPDISEN-------------------*/
498/* field: EV_SAMP_DIS_CYC - Event Group sample cap discharge cycles. */
499#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
500#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
501#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
502
503/* field: EV_SAMP_DIS_EN - Event Group sample cap discharge enable. */
504#define TMS570_ADC_EVSAMPDISEN_EV_SAMP_DIS_EN BSP_BIT32(0)
505
506
507/*-------------------TMS570_ADC_G1SAMPDISEN-------------------*/
508/* field: G1_SAMP_DIS_CYC - Group1 sample cap discharge cycles. */
509#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
510#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
511#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
512
513/* field: G1_SAMP_DIS_EN - Group1 sample cap discharge enable. */
514#define TMS570_ADC_G1SAMPDISEN_G1_SAMP_DIS_EN BSP_BIT32(0)
515
516
517/*-------------------TMS570_ADC_G2SAMPDISEN-------------------*/
518/* field: G2_SAMP_DIS_CYC - for which the ADC internal sampling capacitor is allowed to discharge before sampling the input */
519#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC(val) BSP_FLD32(val,8, 15)
520#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_GET(reg) BSP_FLD32GET(reg,8, 15)
521#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_CYC_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
522
523/* field: G2_SAMP_DIS_EN - Group2 sample cap discharge enable. */
524#define TMS570_ADC_G2SAMPDISEN_G2_SAMP_DIS_EN BSP_BIT32(0)
525
526
527/*--------------------TMS570_ADC_MAGINTCRx--------------------*/
528/* field: MAG_CHID2 - These bits specify the channel number from 0 to 31 for which the conversion result needs to be */
529#define TMS570_ADC_MAGINTCRx_MAG_CHID2(val) BSP_FLD32(val,26, 30)
530#define TMS570_ADC_MAGINTCRx_MAG_CHID2_GET(reg) BSP_FLD32GET(reg,26, 30)
531#define TMS570_ADC_MAGINTCRx_MAG_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,26, 30)
532
533/* field: MAG_THR2 - These bits specify the 10-bit compare value which the ADC will use for the comparison with the */
534#define TMS570_ADC_MAGINTCRx_MAG_THR2(val) BSP_FLD32(val,16, 25)
535#define TMS570_ADC_MAGINTCRx_MAG_THR2_GET(reg) BSP_FLD32GET(reg,16, 25)
536#define TMS570_ADC_MAGINTCRx_MAG_THR2_SET(reg,val) BSP_FLD32SET(reg, val,16, 25)
537
538/* field: COMP_CHID2 - These bits specify the channel number from 0 to 31 whose last conversion result is compared */
539#define TMS570_ADC_MAGINTCRx_COMP_CHID2(val) BSP_FLD32(val,8, 12)
540#define TMS570_ADC_MAGINTCRx_COMP_CHID2_GET(reg) BSP_FLD32GET(reg,8, 12)
541#define TMS570_ADC_MAGINTCRx_COMP_CHID2_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
542
543/* field: CHN_THR_COMP2 - Channel OR Threshold comparison. */
544#define TMS570_ADC_MAGINTCRx_CHN_THR_COMP2 BSP_BIT32(1)
545
546/* field: CMP_GE_LT2 - Greater than or equal to OR Less than comparison operator. */
547#define TMS570_ADC_MAGINTCRx_CMP_GE_LT2 BSP_BIT32(0)
548
549
550/*-------------------TMS570_ADC_MAGINTxMASK-------------------*/
551/* field: MAG_INT0_MASK - These bits specify the mask for the comparison in order to generate the magnitude compare */
552#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK(val) BSP_FLD32(val,0, 9)
553#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_GET(reg) BSP_FLD32GET(reg,0, 9)
554#define TMS570_ADC_MAGINTxMASK_MAG_INT0_MASK_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
555
556
557/*-----------------TMS570_ADC_MAGTHRINTENASET-----------------*/
558/* field: MAG_INT_ENA_SET - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
559#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET(val) BSP_FLD32(val,0, 2)
560#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_GET(reg) BSP_FLD32GET(reg,0, 2)
561#define TMS570_ADC_MAGTHRINTENASET_MAG_INT_ENA_SET_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
562
563
564/*-----------------TMS570_ADC_MAGTHRINTENACLR-----------------*/
565/* field: MAG_INT_ENA_CLR - Each of these three bits, when set, enable the corresponding magnitude compare interrupt. */
566#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR(val) BSP_FLD32(val,0, 2)
567#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_GET(reg) BSP_FLD32GET(reg,0, 2)
568#define TMS570_ADC_MAGTHRINTENACLR_MAG_INT_ENA_CLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
569
570
571/*------------------TMS570_ADC_MAGTHRINTFLG------------------*/
572/* field: MAG_INT_FLG - Magnitude Compare Interrupt Flags. */
573#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG(val) BSP_FLD32(val,0, 2)
574#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_GET(reg) BSP_FLD32GET(reg,0, 2)
575#define TMS570_ADC_MAGTHRINTFLG_MAG_INT_FLG_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
576
577
578/*-----------------TMS570_ADC_MAGTHRINTOFFSET-----------------*/
579/* field: MAG_INT_OFF - Magnitude Compare Interrupt Offset. */
580#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF(val) BSP_FLD32(val,0, 3)
581#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_GET(reg) BSP_FLD32GET(reg,0, 3)
582#define TMS570_ADC_MAGTHRINTOFFSET_MAG_INT_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
583
584
585/*------------------TMS570_ADC_GxFIFORESETCR------------------*/
586/* field: EV_FIFO_RESET - allows the ADC module to overwrite the contents of the Event Group results memory starting from */
587#define TMS570_ADC_GxFIFORESETCR_EV_FIFO_RESET BSP_BIT32(0)
588
589
590/*-------------------TMS570_ADC_EVRAMWRADDR-------------------*/
591/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
592#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
593#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
594#define TMS570_ADC_EVRAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
595
596
597/*-------------------TMS570_ADC_G1RAMWRADDR-------------------*/
598/* field: G1_RAM_ADDR - Group1 results memory write pointer. */
599#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR(val) BSP_FLD32(val,0, 8)
600#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
601#define TMS570_ADC_G1RAMWRADDR_G1_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
602
603
604/*-------------------TMS570_ADC_G2RAMWRADDR-------------------*/
605/* field: G2_RAM_ADDR - Group2 results memory write pointer. */
606#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR(val) BSP_FLD32(val,0, 8)
607#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_GET(reg) BSP_FLD32GET(reg,0, 8)
608#define TMS570_ADC_G2RAMWRADDR_G2_RAM_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
609
610
611/*----------------------TMS570_ADC_PARCR----------------------*/
612/* field: TEST - This bit maps the parity bits into the ADC results' RAM frame so that the application can access */
613#define TMS570_ADC_PARCR_TEST BSP_BIT32(8)
614
615/* field: PARITY_ENA - PARITY ENA */
616#define TMS570_ADC_PARCR_PARITY_ENA(val) BSP_FLD32(val,0, 3)
617#define TMS570_ADC_PARCR_PARITY_ENA_GET(reg) BSP_FLD32GET(reg,0, 3)
618#define TMS570_ADC_PARCR_PARITY_ENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
619
620
621/*---------------------TMS570_ADC_PARADDR---------------------*/
622/* field: ERROR_ADDRESS - These bits hold the address of the first parity error generated in the ADC results' RAM. */
623#define TMS570_ADC_PARADDR_ERROR_ADDRESS(val) BSP_FLD32(val,2, 11)
624#define TMS570_ADC_PARADDR_ERROR_ADDRESS_GET(reg) BSP_FLD32GET(reg,2, 11)
625#define TMS570_ADC_PARADDR_ERROR_ADDRESS_SET(reg,val) BSP_FLD32SET(reg, val,2, 11)
626
627
628/*------------------TMS570_ADC_PWRUPDLYCTRL------------------*/
629/* field: PWRUP_DLY - This register defines the number of VCLK cycles that the ADC state machine has to wait after */
630#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY(val) BSP_FLD32(val,0, 9)
631#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_GET(reg) BSP_FLD32GET(reg,0, 9)
632#define TMS570_ADC_PWRUPDLYCTRL_PWRUP_DLY_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
633
634
635
636#endif /* LIBBSP_ARM_TMS570_ADC */
utility.h
This header file provides utility macros for BSPs.
tms570_adc_t
Definition: reg_adc.h:65
tms570_gxbuf_t
Definition: reg_adc.h:54
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