nios2-utility.h File Reference

NIOS II Utility. More...

#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>

Go to the source code of this file.

Data Structures
struct	Nios2_MPU_Configuration
struct	Nios2_MPU_Region_descriptor

Macros
#define	NIOS2_CTLREG_INDEX_STATUS   0
#define	NIOS2_CTLREG_INDEX_ESTATUS   1
#define	NIOS2_CTLREG_INDEX_BSTATUS   2
#define	NIOS2_CTLREG_INDEX_IENABLE   3
#define	NIOS2_CTLREG_INDEX_IPENDING   4
#define	NIOS2_CTLREG_INDEX_CPUID   5
#define	NIOS2_CTLREG_INDEX_EXCEPTION   7
#define	NIOS2_CTLREG_INDEX_PTEADDR   8
#define	NIOS2_CTLREG_INDEX_TLBACC   9
#define	NIOS2_CTLREG_INDEX_TLBMISC   10
#define	NIOS2_CTLREG_INDEX_BADADDR   12
#define	NIOS2_CTLREG_INDEX_CONFIG   13
#define	NIOS2_CTLREG_INDEX_MPUBASE   14
#define	NIOS2_CTLREG_INDEX_MPUACC   15
#define	NIOS2_CONTEXT_OFFSET_R16   0
#define	NIOS2_CONTEXT_OFFSET_R17   4
#define	NIOS2_CONTEXT_OFFSET_R18   8
#define	NIOS2_CONTEXT_OFFSET_R19   12
#define	NIOS2_CONTEXT_OFFSET_R20   16
#define	NIOS2_CONTEXT_OFFSET_R21   20
#define	NIOS2_CONTEXT_OFFSET_R22   24
#define	NIOS2_CONTEXT_OFFSET_R23   28
#define	NIOS2_CONTEXT_OFFSET_FP   32
#define	NIOS2_CONTEXT_OFFSET_STATUS   36
#define	NIOS2_CONTEXT_OFFSET_SP   40
#define	NIOS2_CONTEXT_OFFSET_RA   44
#define	NIOS2_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE   48
#define	NIOS2_CONTEXT_OFFSET_STACK_MPUBASE   52
#define	NIOS2_CONTEXT_OFFSET_STACK_MPUACC   56
#define	NIOS2_ISR_STATUS_MASK_IIC   0xfffffffe
#define	NIOS2_ISR_STATUS_BITS_IIC   0x00000000
#define	NIOS2_ISR_STATUS_MASK_EIC_IL   0xfffffc0f
#define	NIOS2_ISR_STATUS_BITS_EIC_IL   0x000003f0
#define	NIOS2_ISR_STATUS_MASK_EIC_RSIE   0xf7ffffff
#define	NIOS2_ISR_STATUS_BITS_EIC_RSIE   0x00000000
#define	NIOS2_STATUS_RSIE   (1 << 23)
#define	NIOS2_STATUS_NMI   (1 << 22)
#define	NIOS2_STATUS_PRS_OFFSET   16
#define	NIOS2_STATUS_PRS_MASK   (0x3f << NIOS2_STATUS_PRS_OFFSET)
#define	NIOS2_STATUS_CRS_OFFSET   10
#define	NIOS2_STATUS_CRS_MASK   (0x3f << NIOS2_STATUS_CRS_OFFSET)
#define	NIOS2_STATUS_IL_OFFSET   4
#define	NIOS2_STATUS_IL_MASK   (0x3f << NIOS2_STATUS_IL_OFFSET)
#define	NIOS2_STATUS_IH   (1 << 3)
#define	NIOS2_STATUS_EH   (1 << 2)
#define	NIOS2_STATUS_U   (1 << 1)
#define	NIOS2_STATUS_PIE   (1 << 0)
#define	NIOS2_EXCEPTION_CAUSE_OFFSET   2
#define	NIOS2_EXCEPTION_CAUSE_MASK   (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET)
#define	NIOS2_PTEADDR_PTBASE_OFFSET   22
#define	NIOS2_PTEADDR_PTBASE_MASK   (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET)
#define	NIOS2_PTEADDR_VPN_OFFSET   2
#define	NIOS2_PTEADDR_VPN_MASK   (0xfffff << NIOS2_PTEADDR_VPN_OFFSET)
#define	NIOS2_TLBACC_IG_OFFSET   25
#define	NIOS2_TLBACC_IG_MASK   (0x3ff << NIOS2_TLBACC_IG_OFFSET)
#define	NIOS2_TLBACC_C   (1 << 24)
#define	NIOS2_TLBACC_R   (1 << 23)
#define	NIOS2_TLBACC_W   (1 << 22)
#define	NIOS2_TLBACC_X   (1 << 21)
#define	NIOS2_TLBACC_G   (1 << 20)
#define	NIOS2_TLBACC_PFN_OFFSET   2
#define	NIOS2_TLBACC_PFN_MASK   (0xfffff << NIOS2_TLBACC_PFN_OFFSET)
#define	NIOS2_TLBMISC_WAY_OFFSET   20
#define	NIOS2_TLBMISC_WAY_MASK   (0xf << NIOS2_TLBMISC_WAY_OFFSET)
#define	NIOS2_TLBMISC_RD   (1 << 19)
#define	NIOS2_TLBMISC_WE   (1 << 18)
#define	NIOS2_TLBMISC_PID_OFFSET   5
#define	NIOS2_TLBMISC_PID_MASK   (0x3fff << NIOS2_TLBMISC_PID_OFFSET)
#define	NIOS2_TLBMISC_DBL   (1 << 3)
#define	NIOS2_TLBMISC_BAD   (1 << 2)
#define	NIOS2_TLBMISC_PERM   (1 << 1)
#define	NIOS2_TLBMISC_D   (1 << 0)
#define	NIOS2_CONFIG_ANI   (1 << 1)
#define	NIOS2_CONFIG_PE   (1 << 0)
#define	NIOS2_MPUBASE_BASE_OFFSET   6
#define	NIOS2_MPUBASE_BASE_MASK   (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET)
#define	NIOS2_MPUBASE_INDEX_OFFSET   1
#define	NIOS2_MPUBASE_INDEX_MASK   (0x0000003e)
#define	NIOS2_MPUBASE_D   (1 << 0)
#define	NIOS2_MPUACC_MASK_OFFSET   6
#define	NIOS2_MPUACC_MASK_MASK   (0x7fffffc0)
#define	NIOS2_MPUACC_LIMIT_OFFSET   6
#define	NIOS2_MPUACC_LIMIT_MASK   (0xffffffc0)
#define	NIOS2_MPUACC_C   (1 << 5)
#define	NIOS2_MPUACC_PERM_OFFSET   2
#define	NIOS2_MPUACC_PERM_MASK   (0x0000001c)
#define	NIOS2_MPUACC_RD   (1 << 1)
#define	NIOS2_MPUACC_WR   (1 << 0)
#define	NIOS2_MPU_REGION_DESC_INST(index, base, end)
#define	NIOS2_MPU_REGION_DESC_DATA_RO(index, base, end)
#define	NIOS2_MPU_REGION_DESC_DATA_RW(index, base, end)
#define	NIOS2_MPU_REGION_DESC_DATA_IO(index, base, end)

Enumerations
enum	Nios2_MPU_Region_permissions {   NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0 , NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE , NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE , NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0 ,   NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE , NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY , NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4 , NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY ,   NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE }

Functions
uint32_t	_Nios2_ISR_Set_level (uint32_t new_level, uint32_t status)
void	_Nios2_MPU_Set_configuration (const Nios2_MPU_Configuration *config)
const Nios2_MPU_Configuration *	_Nios2_MPU_Get_configuration (void)
bool	_Nios2_MPU_Setup_region_registers (const Nios2_MPU_Configuration *config, const Nios2_MPU_Region_descriptor *desc, uint32_t *mpubase, uint32_t *mpuacc)
bool	_Nios2_MPU_Get_region_descriptor (const Nios2_MPU_Configuration *config, int index, bool data, Nios2_MPU_Region_descriptor *desc)
int	_Nios2_MPU_Get_disabled_region_index (const Nios2_MPU_Configuration *config, bool data, int begin, int end)
	Searches the region table part for a disabled region.
bool	_Nios2_MPU_Add_region (const Nios2_MPU_Configuration *config, const Nios2_MPU_Region_descriptor *desc, bool force)
	Adds a region according to region descriptor desc.
uint32_t	_Nios2_MPU_Disable_protected (void)
void	_Nios2_MPU_Reset (const Nios2_MPU_Configuration *config)

Variables
char	_Nios2_ISR_Status_mask []
	This global symbol specifies the status register mask used to disable interrupts.
char	_Nios2_ISR_Status_bits []
	This symbol specifies the status register bits used to disable interrupts.

Detailed Description

NIOS II Utility.

Macro Definition Documentation

NIOS2_MPU_REGION_DESC_DATA_IO

#define NIOS2_MPU_REGION_DESC_DATA_IO	(		index,
			base,
			end
	)

Value:

  { \
    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \
    true, false, false, true \
  }

NIOS2_MPU_REGION_DESC_DATA_RO

#define NIOS2_MPU_REGION_DESC_DATA_RO	(		index,
			base,
			end
	)

Value:

  { \
    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \
    true, true, false, true \
  }

NIOS2_MPU_REGION_DESC_DATA_RW

#define NIOS2_MPU_REGION_DESC_DATA_RW	(		index,
			base,
			end
	)

Value:

  { \
    (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \
    true, true, false, true \
  }

NIOS2_MPU_REGION_DESC_INST

#define NIOS2_MPU_REGION_DESC_INST	(		index,
			base,
			end
	)

Value:

  { \
    (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \
    false, false, false, true \
  }

Function Documentation

_Nios2_MPU_Add_region()

bool _Nios2_MPU_Add_region	(	const Nios2_MPU_Configuration *	config,
		const Nios2_MPU_Region_descriptor *	desc,
		bool	force
	)

Adds a region according to region descriptor desc.

If force is true, then an enabled region will be overwritten.

Return values

true	Successful operation.
false	Invalid region descriptor or region already in use.

_Nios2_MPU_Get_disabled_region_index()

int _Nios2_MPU_Get_disabled_region_index	(	const Nios2_MPU_Configuration *	config,
		bool	data,
		int	begin,
		int	end
	)

Searches the region table part for a disabled region.

The table will be searched between indices begin and end. The end index is not part of the search range. If end is negative, then the region count will be used. Thus a begin of 0 and a end of -1 will specify the complete table.

Return values

-1	No disabled region is available.
other	Index of disabled region.

Variable Documentation

_Nios2_ISR_Status_bits

char _Nios2_ISR_Status_bits[]

extern

This symbol specifies the status register bits used to disable interrupts.

The board support package must provide a global symbol with this name to specify the status register bits used in _CPU_ISR_Disable().

_Nios2_ISR_Status_mask

char _Nios2_ISR_Status_mask[]

extern

This global symbol specifies the status register mask used to disable interrupts.

The board support package must provide a global symbol with this name to specify the status register mask used in _CPU_ISR_Disable().