Interrupt code distribution ISR register, interrupt 0-31 (ISR0)

This group contains register bit definitions. More...

Macros
#define	GRSPWROUTER_ISR0_IB_SHIFT   0
#define	GRSPWROUTER_ISR0_IB_MASK   0xffffffffU
#define	GRSPWROUTER_ISR0_IB_GET(_reg)
#define	GRSPWROUTER_ISR0_IB_SET(_reg, _val)
#define	GRSPWROUTER_ISR0_IB(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

GRSPWROUTER_ISR0_IB

#define GRSPWROUTER_ISR0_IB

(

_val

)

Value:

  ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \
    GRSPWROUTER_ISR0_IB_MASK )

GRSPWROUTER_ISR0_IB_GET

#define GRSPWROUTER_ISR0_IB_GET

(

_reg

)

Value:

  ( ( ( _reg ) & GRSPWROUTER_ISR0_IB_MASK ) >> \
    GRSPWROUTER_ISR0_IB_SHIFT )

GRSPWROUTER_ISR0_IB_SET

#define GRSPWROUTER_ISR0_IB_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~GRSPWROUTER_ISR0_IB_MASK ) | \
    ( ( ( _val ) << GRSPWROUTER_ISR0_IB_SHIFT ) & \
      GRSPWROUTER_ISR0_IB_MASK ) )