AMD Zynq UltraScale+ MPSoC and RFSoC - Application Processing Unit

This group contains the BSP for the Application Processing Unit (APU) contained in AMD Zynq UltraScale+ MPSoC and RFSoC devices. More...

Files
file	console.c
	This source file contains this BSP's console configuration.
file	management_apu.c
	This source file contains the management console implementation.
file	management_cfc400x.c
	This source file contains the management console implementation.
file	cache.c
	This source file contains the implementation of zynqmp_ecc_init().
file	ddr.c
	This source file contains the implementation of DDR ECC support.
file	ocm.c
	This source file contains the implementation of OCM ECC support.
file	bsp_fdt.c
	This source file contains the implementatin of bsp_fdt_get().
file	bsp.h
	This header file provides BSP-specific interfaces.
file	ecc.h
	This header file provides internal APIs for managing ECC events.
file	ecc_priv.h
	This header file provides internal APIs for managing ECC events.
file	irq.h
	This header file provides the BSP's IRQ definitions.
file	jffs2_xqspipsu.h
	XilinxZynqMP QSPI JFFS2 flash driver definitions.
file	xil-compat.h
	This header file provides BSP-specific interfaces.
file	tm27.h
	This header file provides functionality for the tm27 test.
file	bspstart.c
	This source file contains the implementation of bsp_start().
file	bspstartecc_cfc400x.c
	This source file contains the implementation of zynqmp_ecc_init_bsp().
file	bspstartecc_hw.c
	This source file contains the implementation of zynqmp_ecc_init().
file	bspstartecc_qemu.c
	This source file contains the implementation of zynqmp_ecc_init().
file	bspstartecc_zu3eg.c
	This source file contains the implementation of zynqmp_ecc_init_bsp().
file	bspstarthooks.c
	This source file contains the implementation of this BSP's startup hooks.
file	bspstartmmu.c
	This source file contains the default MMU tables and setup.
file	i2c-clocks.c
	This source file contains the implementation of zynqmp_clock_i2c0() and zynqmp_clock_i2c1().
file	mmu-config.c
	This source file contains the definition of aarch64_mmu_config_table and aarch64_mmu_config_table_size.

Macros
#define	BSP_ARM_GIC_CPUIF_BASE   0xf9020000
#define	BSP_ARM_GIC_DIST_BASE   0xf9010000
#define	BSP_FDT_IS_SUPPORTED
#define	NANDPSU_BASEADDR   0xFF100000

Functions
BSP_START_TEXT_SECTION void	zynqmp_setup_mmu_and_cache (void)
	Zynq UltraScale+ MPSoC specific set up of the MMU.
BSP_START_TEXT_SECTION void	zynqmp_setup_secondary_cpu_mmu_and_cache (void)
	Zynq UltraScale+ MPSoC specific set up of the MMU for non-primary cores.
void	zynqmp_management_console_termios_init (void)
void	zynqmp_debug_console_flush (void)
uint32_t	zynqmp_clock_i2c0 (void)
uint32_t	zynqmp_clock_i2c1 (void)
void	zynqmp_configure_management_console (struct rtems_termios_device_context *base)
	Zynq UltraScale+ MPSoC specific set up of a management console.

Variables
unsigned int	zynqmp_dtb_len
unsigned char	zynqmp_dtb []

Detailed Description

This group contains the BSP for the Application Processing Unit (APU) contained in AMD Zynq UltraScale+ MPSoC and RFSoC devices.

Function Documentation

zynqmp_configure_management_console()

void zynqmp_configure_management_console

(

struct rtems_termios_device_context *

base

)

Zynq UltraScale+ MPSoC specific set up of a management console.

Some systems may have a management interface which needs special initialization. Provide in the application to override the defaults in the BSP. This will only be called if the interface is found in the device tree.

zynqmp_setup_mmu_and_cache()

BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache

(

void

)

Zynq UltraScale+ MPSoC specific set up of the MMU.

Provide in the application to override the defaults in the BSP.

zynqmp_setup_secondary_cpu_mmu_and_cache()

BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache

(

void

)

Zynq UltraScale+ MPSoC specific set up of the MMU for non-primary cores.

Provide in the application to override the defaults in the BSP.