#include "fsl_common.h"

Macros
CTRL0 - CTRL0 Register
#define	AI_PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK)

#define	AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U)

#define	AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U)

#define	AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK)

#define	AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U)

#define	AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U)

#define	AI_PHY_LDO_CTRL0_LIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)

#define	AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U)

#define	AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U)

#define	AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK)

#define	AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U)

#define	AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U)

#define	AI_PHY_LDO_CTRL0_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK)

#define	AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U)

#define	AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U)

#define	AI_BANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK)

#define	AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U)

#define	AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U)

#define	AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x)

#define	AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)

#define	AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)

#define	AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)

#define	AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U)

#define	AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U)

#define	AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)

#define	AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)

#define	AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)

#define	AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x)

#define	AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)

#define	AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)

#define	AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK)

#define	AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U)

#define	AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U)

#define	AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK)

#define	AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U)

#define	AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U)

#define	AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK)

#define	AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U)

#define	AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U)

#define	AI_PLL1G_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK)

#define	AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)

#define	AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U)

#define	AI_PLL1G_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK)

#define	AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL)

#define	AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U)

#define	AI_PLL1G_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK)

#define	AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL)

#define	AI_PLL1G_CTRL0_ENABLE_SHIFT (15U)

#define	AI_PLL1G_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK)

#define	AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL)

#define	AI_PLL1G_CTRL0_BYPASS_SHIFT (16U)

#define	AI_PLL1G_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK)

#define	AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL)

#define	AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U)

#define	AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK)

#define	AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)

#define	AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U)

#define	AI_PLLAUDIO_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK)

#define	AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL)

#define	AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U)

#define	AI_PLLAUDIO_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK)

#define	AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL)

#define	AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U)

#define	AI_PLLAUDIO_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK)

#define	AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL)

#define	AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U)

#define	AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK)

#define	AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL)

#define	AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U)

#define	AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK)

#define	AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL)

#define	AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U)

#define	AI_PLLVIDEO_CTRL0_POWER_UP(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK)

#define	AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL)

#define	AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U)

#define	AI_PLLVIDEO_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK)

#define	AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL)

#define	AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U)

#define	AI_PLLVIDEO_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK)

#define	AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL)

#define	AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U)

#define	AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK)

#define	AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL)

#define	AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U)

STAT0 - STAT0 Register
#define	AI_PHY_LDO_STAT0_LINREG_STAT(x) (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK)

#define	AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU)

#define	AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U)

#define	AI_BANDGAP_STAT0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK)

#define	AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U)

#define	AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U)

#define	AI_RCOSC400M_STAT0_CLK1M_ERR(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK)

#define	AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U)

#define	AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U)

CTRL1 - CTRL1 Register
#define	AI_RCOSC400M_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK)

#define	AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU)

#define	AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U)

#define	AI_RCOSC400M_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK)

#define	AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U)

#define	AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U)

#define	AI_RCOSC400M_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK)

#define	AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U)

#define	AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U)

CTRL2 - CTRL2 Register
#define	AI_RCOSC400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK)

#define	AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U)

#define	AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U)

#define	AI_RCOSC400M_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK)

#define	AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U)

#define	AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U)

#define	AI_RCOSC400M_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK)

#define	AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U)

#define	AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U)

#define	AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK)

#define	AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)

#define	AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)

CTRL3 - CTRL3 Register
#define	AI_RCOSC400M_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK)

#define	AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U)

#define	AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U)

#define	AI_RCOSC400M_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK)

#define	AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U)

#define	AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U)

#define	AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK)

#define	AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U)

#define	AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U)

#define	AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK)

#define	AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U)

#define	AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U)

STAT1 - STAT1 Register
#define	AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK)

#define	AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U)

#define	AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U)

STAT2 - STAT2 Register
#define	AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x)

#define	AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)

#define	AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)

Functions
uint32_t	ANATOP_AI_Access (anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata)
	AI interface access.

void	ANATOP_AI_Write (anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata)
	AI interface writing.

uint32_t	ANATOP_AI_Read (anatop_ai_itf_t itf, anatop_ai_reg_t addr)
	AI interface reading.

void	ANATOP_AI_WriteWithMaskShift (anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
	AI interface write with mask and shift.

Driver version
#define	FSL_ANATOP_AI_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
	Anatop AI driver version 1.0.0.

enum	_anatop_ai_itf { kAI_Itf_Ldo = 0 , kAI_Itf_1g = 1 , kAI_Itf_Audio = 2 , kAI_Itf_Video = 3 , kAI_Itf_400m = 4 , kAI_Itf_Temp = 5 , kAI_Itf_Bandgap = 6 }
	Anatop AI ITF enumeration. More...

enum	_anatop_ai_reg { kAI_PHY_LDO_CTRL0 = 0x0 , kAI_PHY_LDO_CTRL0_SET = 0x4 , kAI_PHY_LDO_CTRL0_CLR = 0x8 , kAI_PHY_LDO_CTRL0_TOG = 0xC , kAI_PHY_LDO_STAT0 = 0x50 , kAI_PHY_LDO_STAT0_SET = 0x54 , kAI_PHY_LDO_STAT0_CLR = 0x58 , kAI_PHY_LDO_STAT0_TOG = 0x5C , kAI_BANDGAP_CTRL0 = 0x0 , kAI_BANDGAP_STAT0 = 0x50 , kAI_RCOSC400M_CTRL0 = 0x0 , kAI_RCOSC400M_CTRL0_SET = 0x4 , kAI_RCOSC400M_CTRL0_CLR = 0x8 , kAI_RCOSC400M_CTRL0_TOG = 0xC , kAI_RCOSC400M_CTRL1 = 0x10 , kAI_RCOSC400M_CTRL1_SET = 0x14 , kAI_RCOSC400M_CTRL1_CLR = 0x18 , kAI_RCOSC400M_CTRL1_TOG = 0x1C , kAI_RCOSC400M_CTRL2 = 0x20 , kAI_RCOSC400M_CTRL2_SET = 0x24 , kAI_RCOSC400M_CTRL2_CLR = 0x28 , kAI_RCOSC400M_CTRL2_TOG = 0x2C , kAI_RCOSC400M_CTRL3 = 0x30 , kAI_RCOSC400M_CTRL3_SET = 0x34 , kAI_RCOSC400M_CTRL3_CLR = 0x38 , kAI_RCOSC400M_CTRL3_TOG = 0x3C , kAI_RCOSC400M_STAT0 = 0x50 , kAI_RCOSC400M_STAT0_SET = 0x54 , kAI_RCOSC400M_STAT0_CLR = 0x58 , kAI_RCOSC400M_STAT0_TOG = 0x5C , kAI_RCOSC400M_STAT1 = 0x60 , kAI_RCOSC400M_STAT1_SET = 0x64 , kAI_RCOSC400M_STAT1_CLR = 0x68 , kAI_RCOSC400M_STAT1_TOG = 0x6C , kAI_RCOSC400M_STAT2 = 0x70 , kAI_RCOSC400M_STAT2_SET = 0x74 , kAI_RCOSC400M_STAT2_CLR = 0x78 , kAI_RCOSC400M_STAT2_TOG = 0x7C , kAI_PLL1G_CTRL0 = 0x0 , kAI_PLL1G_CTRL0_SET = 0x4 , kAI_PLL1G_CTRL0_CLR = 0x8 , kAI_PLL1G_CTRL1 = 0x10 , kAI_PLL1G_CTRL1_SET = 0x14 , kAI_PLL1G_CTRL1_CLR = 0x18 , kAI_PLL1G_CTRL2 = 0x20 , kAI_PLL1G_CTRL2_SET = 0x24 , kAI_PLL1G_CTRL2_CLR = 0x28 , kAI_PLL1G_CTRL3 = 0x30 , kAI_PLL1G_CTRL3_SET = 0x34 , kAI_PLL1G_CTRL3_CLR = 0x38 , kAI_PLLAUDIO_CTRL0 = 0x0 , kAI_PLLAUDIO_CTRL0_SET = 0x4 , kAI_PLLAUDIO_CTRL0_CLR = 0x8 , kAI_PLLAUDIO_CTRL1 = 0x10 , kAI_PLLAUDIO_CTRL1_SET = 0x14 , kAI_PLLAUDIO_CTRL1_CLR = 0x18 , kAI_PLLAUDIO_CTRL2 = 0x20 , kAI_PLLAUDIO_CTRL2_SET = 0x24 , kAI_PLLAUDIO_CTRL2_CLR = 0x28 , kAI_PLLAUDIO_CTRL3 = 0x30 , kAI_PLLAUDIO_CTRL3_SET = 0x34 , kAI_PLLAUDIO_CTRL3_CLR = 0x38 , kAI_PLLVIDEO_CTRL0 = 0x0 , kAI_PLLVIDEO_CTRL0_SET = 0x4 , kAI_PLLVIDEO_CTRL0_CLR = 0x8 , kAI_PLLVIDEO_CTRL1 = 0x10 , kAI_PLLVIDEO_CTRL1_SET = 0x14 , kAI_PLLVIDEO_CTRL1_CLR = 0x18 , kAI_PLLVIDEO_CTRL2 = 0x20 , kAI_PLLVIDEO_CTRL2_SET = 0x24 , kAI_PLLVIDEO_CTRL2_CLR = 0x28 , kAI_PLLVIDEO_CTRL3 = 0x30 , kAI_PLLVIDEO_CTRL3_SET = 0x34 , kAI_PLLVIDEO_CTRL3_CLR = 0x38 }
	The enumeration of ANATOP AI Register. More...

typedef enum _anatop_ai_itf	anatop_ai_itf_t
	Anatop AI ITF enumeration.

typedef enum _anatop_ai_reg	anatop_ai_reg_t
	The enumeration of ANATOP AI Register.

Function Documentation

◆ ANATOP_AI_Access()

uint32_t ANATOP_AI_Access	(	anatop_ai_itf_t	itf,
		bool	isWrite,
		anatop_ai_reg_t	addr,
		uint32_t	wdata
	)

AI interface access.

Parameters

itf	AI interface name
isWrite	write enable
addr	address
wdata	data to be set

◆ ANATOP_AI_Read()

uint32_t ANATOP_AI_Read	(	anatop_ai_itf_t	itf,
		anatop_ai_reg_t	addr
	)

AI interface reading.

Parameters

itf	AI interface name
addr	address

Returns: data read

◆ ANATOP_AI_Write()

void ANATOP_AI_Write	(	anatop_ai_itf_t	itf,
		anatop_ai_reg_t	addr,
		uint32_t	wdata
	)

AI interface writing.

Parameters

itf	AI interface name
addr	address
wdata	data to be set

◆ ANATOP_AI_WriteWithMaskShift()

void ANATOP_AI_WriteWithMaskShift	(	anatop_ai_itf_t	itf,
		anatop_ai_reg_t	addr,
		uint32_t	wdata,
		uint32_t	mask,
		uint32_t	shift
	)

AI interface write with mask and shift.

Parameters

itf	AI interface name
addr	address
wdata	data to be written
mask	bit field mask
shift	bit field shift

Macros

Functions

Driver version

Function Documentation

◆ ANATOP_AI_Access()

◆ ANATOP_AI_Read()

◆ ANATOP_AI_Write()

◆ ANATOP_AI_WriteWithMaskShift()