37#ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
38#define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H
50#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
51#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
52#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
53#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
54#define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
56#define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7)
57#define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
58#define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
60#define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
61#define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
62#define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
64#define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12)
65#define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
66#define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
67#define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9)
68#define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
69#define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
71#define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12)
72#define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
73#define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
74#define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9)
75#define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
76#define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
78#define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7)
79#define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7)
80#define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
82#define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12)
83#define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12)
84#define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
85#define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9)
86#define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9)
87#define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9)
89#define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2)
90#define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2)
91#define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
92 uint32_t reserved_20[55];
94#define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
95#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
96#define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
97#define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19)
98#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19)
99#define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
100#define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
101#define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
102#define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
103#define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
104#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
105#define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
112#define GIC_DIST_ICDDCR_RWP BSP_BIT32(31)
113#define GIC_DIST_ICDDCR_E1NWF BSP_BIT32(7)
114#define GIC_DIST_ICDDCR_DS BSP_BIT32(6)
115#define GIC_DIST_ICDDCR_ARE_NS BSP_BIT32(5)
116#define GIC_DIST_ICDDCR_ARE_S BSP_BIT32(4)
117#define GIC_DIST_ICDDCR_ENABLE_GRP1S BSP_BIT32(2)
118#define GIC_DIST_ICDDCR_ENABLE_GRP1NS BSP_BIT32(1)
119#define GIC_DIST_ICDDCR_ENABLE_GRP0 BSP_BIT32(0)
121#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
122#define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
124#define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15)
125#define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15)
126#define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15)
127#define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10)
128#define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7)
129#define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7)
130#define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
131#define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4)
132#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4)
133#define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
135#define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31)
136#define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31)
137#define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
138#define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19)
139#define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19)
140#define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
141#define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15)
142#define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15)
143#define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
144#define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11)
145#define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11)
146#define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
147 uint32_t gicd_typer2;
148 uint32_t gicd_statusr;
149 uint32_t reserved_14[11];
150 uint32_t gicd_setspi_nsr;
151 uint32_t reserved_44[1];
152 uint32_t gicd_clrspi_nsr;
153 uint32_t reserved_4c[1];
154 uint32_t gicd_setspi_sr;
155 uint32_t reserved_54[1];
156 uint32_t gicd_clrspi_sr;
157 uint32_t reserved_5c[9];
159 uint32_t icdiser[32];
160 uint32_t icdicer[32];
161 uint32_t icdispr[32];
162 uint32_t icdicpr[32];
164 uint32_t gicd_icactiver[32];
165 uint8_t icdipr[1024];
166 uint8_t icdiptr[1024];
167 uint32_t icdicfr[64];
169 uint32_t icdigmr[32];
170 uint32_t reserved_d80[32];
171 uint32_t gicd_nsacr[64];
173#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25)
174#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25)
175#define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
176#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23)
177#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23)
178#define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
179#define GIC_DIST_ICDSGIR_NSATT BSP_BIT32(15)
180#define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3)
181#define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3)
182#define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
183 uint32_t reserved_f04[3];
184 uint32_t gicd_cpendsgir[4];
185 uint32_t gicd_spendsgir[4];
186 uint32_t reserved_f80[20];
187 uint32_t gicd_inmir[32];
188 uint32_t gicd_igroupre[32];
189 uint32_t reserved_1080[96];
190 uint32_t gicd_isenablere[32];
191 uint32_t reserved_1280[96];
192 uint32_t gicd_icenablere[32];
193 uint32_t reserved_1480[96];
194 uint32_t gicd_ispendre[32];
195 uint32_t reserved_1680[96];
196 uint32_t gicd_icpendre[32];
197 uint32_t reserved_1880[96];
198 uint32_t gicd_isactivere[32];
199 uint32_t reserved_1a80[96];
200 uint32_t gicd_icactivere[32];
201 uint32_t reserved_1c80[224];
202 uint8_t gicd_ipriorityre[1024];
203 uint32_t reserved_2400[768];
204 uint32_t gicd_icfgre[64];
205 uint32_t reserved_3100[192];
206 uint32_t gicd_igrpmodre[32];
207 uint32_t reserved_3480[96];
208 uint32_t gicd_nsacre[32];
209 uint32_t reserved_3680[288];
210 uint32_t gicd_inmire[32];
211 uint32_t reserved_3b80[2400];
212 uint64_t gicd_irouter[992];
213 uint64_t gicd_iroutere[4096];
220#define GIC_REDIST_ICRRCR_UWP BSP_BIT32(31)
221#define GIC_REDIST_ICRRCR_DPG1S BSP_BIT32(26)
222#define GIC_REDIST_ICRRCR_DPG1NS BSP_BIT32(25)
223#define GIC_REDIST_ICRRCR_DPG0 BSP_BIT32(24)
224#define GIC_REDIST_ICRRCR_RWP BSP_BIT32(4)
225#define GIC_REDIST_ICRRCR_ENABLE_LPI BSP_BIT32(0)
228#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE(val) BSP_FLD64(val, 32, 63)
229#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_GET(reg) BSP_FLD64GET(reg, 32, 63)
230#define GIC_REDIST_ICRTYPER_AFFINITY_VALUE_SET(reg, val) BSP_FLD64SET(reg, val, 32, 63)
231#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY(val) BSP_FLD64(val, 24, 25)
232#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_GET(reg) BSP_FLD64GET(reg, 24, 25)
233#define GIC_REDIST_ICRTYPER_COMMON_LPI_AFFINITY_SET(reg, val) BSP_FLD64SET(reg, val, 24, 25)
234#define GIC_REDIST_ICRTYPER_CPU_NUMBER(val) BSP_FLD64(val, 8, 23)
235#define GIC_REDIST_ICRTYPER_CPU_NUMBER_GET(reg) BSP_FLD64GET(reg, 8, 23)
236#define GIC_REDIST_ICRTYPER_CPU_NUMBER_SET(reg, val) BSP_FLD64SET(reg, val, 8, 23)
237#define GIC_REDIST_ICRTYPER_DPGS BSP_BIT64(5)
238#define GIC_REDIST_ICRTYPER_LAST BSP_BIT64(4)
239#define GIC_REDIST_ICRTYPER_DIRECT_LPI BSP_BIT64(3)
240#define GIC_REDIST_ICRTYPER_VLPIS BSP_BIT64(1)
241#define GIC_REDIST_ICRTYPER_PLPIS BSP_BIT64(0)
244#define GIC_REDIST_ICRWAKER_CHILDREN_ASLEEP BSP_BIT32(2)
245#define GIC_REDIST_ICRWAKER_PROCESSOR_SLEEP BSP_BIT32(1)
250 uint32_t reserved_0_80[32];
252 uint32_t icspigrpr[32];
254 uint32_t icspiser[32];
256 uint32_t icspicer[32];
258 uint32_t icspispendr[32];
260 uint32_t icspicpendr[32];
262 uint32_t icspisar[32];
264 uint32_t icspicar[32];
266 uint8_t icspiprior[32];
267 uint32_t reserved_420_bfc[504];
269 uint32_t icspicfgr[2];
270 uint32_t reserved_c08_cfc[62];
272 uint32_t icspigrpmodr[64];
This header file provides utility macros for BSPs.
Definition: arm-gic-regs.h:48
Definition: arm-gic-regs.h:108
Definition: arm-gic-regs.h:217
Definition: arm-gic-regs.h:249