RTEMS 6.1-rc4
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aarch64-mmu.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef LIBBSP_AARCH64_SHARED_AARCH64_MMU_H
38#define LIBBSP_AARCH64_SHARED_AARCH64_MMU_H
39
40#include <bsp/fatal.h>
41#include <bsp/linker-symbols.h>
42#include <bsp/start.h>
43#include <bsp/utility.h>
44#include <bspopts.h>
47
48#ifdef __cplusplus
49extern "C" {
50#endif /* __cplusplus */
51
52typedef struct {
53 uintptr_t begin;
54 uintptr_t end;
55 uint64_t flags;
57
58#define AARCH64_MMU_DEFAULT_SECTIONS \
59 { \
60 .begin = (uintptr_t) bsp_section_fast_text_begin, \
61 .end = (uintptr_t) bsp_section_fast_text_end, \
62 .flags = AARCH64_MMU_CODE_CACHED \
63 }, { \
64 .begin = (uintptr_t) bsp_section_fast_data_begin, \
65 .end = (uintptr_t) bsp_section_fast_data_end, \
66 .flags = AARCH64_MMU_DATA_RW_CACHED \
67 }, { \
68 .begin = (uintptr_t) bsp_section_start_begin, \
69 .end = (uintptr_t) bsp_section_start_end, \
70 .flags = AARCH64_MMU_CODE_CACHED \
71 }, { \
72 .begin = (uintptr_t) bsp_section_vector_begin, \
73 .end = (uintptr_t) bsp_section_vector_end, \
74 .flags = AARCH64_MMU_DATA_RW_CACHED \
75 }, { \
76 .begin = (uintptr_t) bsp_section_text_begin, \
77 .end = (uintptr_t) bsp_section_text_end, \
78 .flags = AARCH64_MMU_CODE_CACHED \
79 }, { \
80 .begin = (uintptr_t) bsp_section_rodata_begin, \
81 .end = (uintptr_t) bsp_section_rodata_end, \
82 .flags = AARCH64_MMU_DATA_RO_CACHED \
83 }, { \
84 .begin = (uintptr_t) bsp_section_data_begin, \
85 .end = (uintptr_t) bsp_section_data_end, \
86 .flags = AARCH64_MMU_DATA_RW_CACHED \
87 }, { \
88 .begin = (uintptr_t) bsp_section_bss_begin, \
89 .end = (uintptr_t) bsp_section_bss_end, \
90 .flags = AARCH64_MMU_DATA_RW_CACHED \
91 }, { \
92 .begin = (uintptr_t) bsp_section_rtemsstack_begin, \
93 .end = (uintptr_t) bsp_section_rtemsstack_end, \
94 .flags = AARCH64_MMU_DATA_RW_CACHED \
95 }, { \
96 .begin = (uintptr_t) bsp_section_noinit_begin, \
97 .end = (uintptr_t) bsp_section_noinit_end, \
98 .flags = AARCH64_MMU_DATA_RW_CACHED \
99 }, { \
100 .begin = (uintptr_t) bsp_section_work_begin, \
101 .end = (uintptr_t) bsp_section_work_end, \
102 .flags = AARCH64_MMU_DATA_RW_CACHED \
103 }, { \
104 .begin = (uintptr_t) bsp_section_stack_begin, \
105 .end = (uintptr_t) bsp_section_stack_end, \
106 .flags = AARCH64_MMU_DATA_RW_CACHED \
107 }, { \
108 .begin = (uintptr_t) bsp_section_nocache_begin, \
109 .end = (uintptr_t) bsp_section_nocache_end, \
110 .flags = AARCH64_MMU_DEVICE \
111 }, { \
112 .begin = (uintptr_t) bsp_section_nocachenoload_begin, \
113 .end = (uintptr_t) bsp_section_nocachenoload_end, \
114 .flags = AARCH64_MMU_DEVICE \
115 }, { \
116 .begin = (uintptr_t) bsp_translation_table_base, \
117 .end = (uintptr_t) bsp_translation_table_end, \
118 .flags = AARCH64_MMU_DATA_RW_CACHED \
119 }, { \
120/*
121 * The vector table must be in writable and executable memory as it stores both
122 * exception code and the mutable pointer to which it jumps
123 */ \
124 .begin = (uintptr_t) bsp_start_vector_table_begin, \
125 .end = (uintptr_t) bsp_start_vector_table_end, \
126 .flags = AARCH64_MMU_CODE_RW_CACHED \
127 }
128
136
143extern const size_t aarch64_mmu_config_table_size;
144
149typedef struct {
153 uint64_t *ttb;
154
160 size_t used_page_tables;
162
167
191);
192
209 const aarch64_mmu_config_entry *config_table,
210 size_t config_count
211);
212
213BSP_START_TEXT_SECTION static inline void
214aarch64_mmu_enable( const aarch64_mmu_control *control )
215{
216 uint64_t sctlr;
217
218 /* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
219
220 /* Flush and invalidate cache */
222
223 _AArch64_Write_ttbr0_el1( (uintptr_t) control->ttb );
224 _AARCH64_Instruction_synchronization_barrier();
225
226 /* Enable MMU and cache */
227 sctlr = _AArch64_Read_sctlr_el1();
228 sctlr |= AARCH64_SCTLR_EL1_I | AARCH64_SCTLR_EL1_C | AARCH64_SCTLR_EL1_M;
229 _AArch64_Write_sctlr_el1( sctlr );
230}
231
232BSP_START_TEXT_SECTION static inline void
233aarch64_mmu_disable( void )
234{
235 uint64_t sctlr;
236
237 /*
238 * Flush data cache before disabling the MMU. While the MMU is disabled, all
239 * accesses are treated as uncached device memory.
240 */
242
243 /* Disable MMU */
244 sctlr = _AArch64_Read_sctlr_el1();
245 sctlr &= ~(AARCH64_SCTLR_EL1_M);
246 _AArch64_Write_sctlr_el1( sctlr );
247}
248
249BSP_START_TEXT_SECTION static inline void aarch64_mmu_setup( void )
250{
251 /* Set TCR */
252 /* 256TB/48 bits mappable (64-0x10) */
253 _AArch64_Write_tcr_el1(
254 AARCH64_TCR_EL1_T0SZ( 0x10 ) | AARCH64_TCR_EL1_IRGN0( 0x1 ) |
255 AARCH64_TCR_EL1_ORGN0( 0x1 ) | AARCH64_TCR_EL1_SH0( 0x3 ) |
256 AARCH64_TCR_EL1_TG0( 0x0 ) | AARCH64_TCR_EL1_IPS( 0x5ULL ) |
257 AARCH64_TCR_EL1_EPD1
258 );
259
260 /* Set MAIR */
261 _AArch64_Write_mair_el1(
262 AARCH64_MAIR_EL1_ATTR0( 0x0 ) | AARCH64_MAIR_EL1_ATTR1( 0x4 ) |
263 AARCH64_MAIR_EL1_ATTR2( 0x44 ) | AARCH64_MAIR_EL1_ATTR3( 0xFF )
264 );
265}
266
267#ifdef __cplusplus
268}
269#endif /* __cplusplus */
270
271#endif /* LIBBSP_AARCH64_SHARED_AARCH64_MMU_H */
aarch64_mmu_control aarch64_mmu_instance
This object is used to maintain the MMU translation tables.
Definition: mmu-setup.c:45
const aarch64_mmu_config_entry aarch64_mmu_config_table[]
This is the AArch64 MMU configuration table.
Definition: mmu-config.c:44
rtems_status_code aarch64_mmu_set_translation_table_entries(aarch64_mmu_control *control, const aarch64_mmu_config_entry *config)
Sets the MMU translation table entries associated with the memory region.
Definition: mmu-setup.c:260
void aarch64_mmu_setup_translation_table(aarch64_mmu_control *control, const aarch64_mmu_config_entry *config_table, size_t config_count)
Sets up the MMU translation table.
Definition: mmu-setup.c:294
const size_t aarch64_mmu_config_table_size
This is the count of entries in the AArch64 MMU configuration table.
Definition: mmu-config.c:70
This header file provides the API to read and write the AArch64 system registers.
This header file provides fatal codes for RTEMS_FATAL_SOURCE_BSP.
void rtems_cache_flush_entire_data(void)
Flushes the entire data cache.
Definition: cacheimpl.h:213
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
This header file provides utility macros for BSPs.
This header file provides interfaces to BSP-specific linker symbols and sections.
Definitions used in MMU setup.
Definition: aarch64-mmu.h:52
This structure represents the state to maintain the MMU translation tables.
Definition: aarch64-mmu.h:146
Definition: deflate.c:114
Definition: intercom.c:87