RTEMS 6.1-rc2
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xil_mpu.h
1/******************************************************************************
2* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
64#ifndef XIL_MPU_H
65#define XIL_MPU_H
66
67#ifdef __cplusplus
68extern "C" {
69#endif /* __cplusplus */
70#include "xil_types.h"
71/***************************** Include Files *********************************/
72
73/***************** Macros (Inline Functions) Definitions *********************/
74#define MPU_REG_DISABLED 0U
75#define MPU_REG_ENABLED 1U
76#define MAX_POSSIBLE_MPU_REGS 16U
77/**************************** Type Definitions *******************************/
78struct XMpuConfig{
79 u32 RegionStatus; /* Enabled or disabled */
80 INTPTR BaseAddress;/* MPU region base address */
81 u64 Size; /* MPU region size address */
82 u32 Attribute; /* MPU region size attribute */
83};
84
85typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS];
86
87extern XMpu_Config Mpu_Config;
88/************************** Constant Definitions *****************************/
89
90/************************** Variable Definitions *****************************/
91
92/************************** Function Prototypes ******************************/
97void Xil_SetTlbAttributes(INTPTR addr, u32 attrib);
98void Xil_EnableMPU(void);
99void Xil_DisableMPU(void);
100u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
101u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib);
102void Xil_GetMPUConfig (XMpu_Config mpuconfig);
103u32 Xil_GetNumOfFreeRegions (void);
104u32 Xil_GetNextMPURegion(void);
105u32 Xil_DisableMPURegionByRegNum (u32 reg_num);
106u16 Xil_GetMPUFreeRegMask (void);
107u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib);
108void* Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags);
109
110#ifdef __cplusplus
111}
112#endif /* __cplusplus */
113
114#endif /* XIL_MPU_H */
void Xil_DisableMPU(void)
Disable MPU for Cortex R5 processors. This function invalidates I cache and flush the D Caches,...
Definition: xil_mpu.c:259
void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
This function sets the memory attributes for a section covering 1MB, of memory in the translation tab...
Definition: xil_mpu.c:142
void Xil_GetMPUConfig(XMpu_Config mpuconfig)
The MPU configuration table is passed to the caller.
Definition: xil_mpu.c:364
u32 Xil_GetNextMPURegion(void)
Returns the next available free MPU region.
Definition: xil_mpu.c:577
u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
Set the memory attributes for a section of memory in the translation table.
Definition: xil_mpu.c:162
u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib)
Update the MPU configuration for the requested region number in the global MPU configuration table.
Definition: xil_mpu.c:317
u32 Xil_GetNumOfFreeRegions(void)
Returns the total number of free MPU regions available.
Definition: xil_mpu.c:384
u16 Xil_GetMPUFreeRegMask(void)
Returns the total number of free MPU regions available in the form of a mask. A bit of 1 in the retur...
Definition: xil_mpu.c:409
u32 Xil_SetMPURegionByRegNum(u32 reg_num, INTPTR addr, u64 size, u32 attrib)
Enables the corresponding region number as passed by the user.
Definition: xil_mpu.c:474
u32 Xil_DisableMPURegionByRegNum(u32 reg_num)
Disables the corresponding region number as passed by the user.
Definition: xil_mpu.c:432
void * Xil_MemMap(UINTPTR Physaddr, size_t size, u32 flags)
Memory mapping for Cortex-R5F. If successful, the mapped region will include all of the memory reques...
Definition: xil_mpu.c:620
void Xil_EnableMPU(void)
Enable MPU for Cortex R5 processor. This function invalidates I cache and flush the D Caches,...
Definition: xil_mpu.c:210