Header file of FMC HAL module. More...

#include "stm32h7xx_hal_def.h"

Data Structures
struct	FMC_NORSRAM_InitTypeDef
	FMC NORSRAM Configuration Structure definition. More...

struct	FMC_NORSRAM_TimingTypeDef
	FMC NORSRAM Timing parameters structure definition. More...

struct	FMC_NAND_InitTypeDef
	FMC NAND Configuration Structure definition. More...

struct	FMC_NAND_PCC_TimingTypeDef
	FMC NAND Timing parameters structure definition. More...

struct	FMC_SDRAM_InitTypeDef
	FMC SDRAM Configuration Structure definition. More...

struct	FMC_SDRAM_TimingTypeDef
	FMC SDRAM Timing parameters structure definition. More...

struct	FMC_SDRAM_CommandTypeDef
	SDRAM command parameters structure definition. More...

Macros
#define	IS_FMC_NORSRAM_BANK(__BANK__)

#define	IS_FMC_MUX(__MUX__)

#define	IS_FMC_MEMORY(__MEMORY__)

#define	IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__)

#define	IS_FMC_PAGESIZE(__SIZE__)

#define	IS_FMC_WRITE_FIFO(__FIFO__)

#define	IS_FMC_ACCESS_MODE(__MODE__)

#define	IS_FMC_BURSTMODE(__STATE__)

#define	IS_FMC_WAIT_POLARITY(__POLARITY__)

#define	IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__)

#define	IS_FMC_WRITE_OPERATION(__OPERATION__)

#define	IS_FMC_WAITE_SIGNAL(__SIGNAL__)

#define	IS_FMC_EXTENDED_MODE(__MODE__)

#define	IS_FMC_ASYNWAIT(__STATE__)

#define	IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))

#define	IS_FMC_WRITE_BURST(__BURST__)

#define	IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)

#define	IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)

#define	IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))

#define	IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))

#define	IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)

#define	IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)

#define	IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))

#define	IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)

#define	IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)

#define	IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)

#define	IS_FMC_WAIT_FEATURE(__FEATURE__)

#define	IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__)

#define	IS_FMC_ECC_STATE(__STATE__)

#define	IS_FMC_ECCPAGE_SIZE(__SIZE__)

#define	IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)

#define	IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)

#define	IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)

#define	IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)

#define	IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)

#define	IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)

#define	IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)

#define	IS_FMC_SDMEMORY_WIDTH(__WIDTH__)

#define	IS_FMC_WRITE_PROTECTION(__WRITE__)

#define	IS_FMC_SDCLOCK_PERIOD(__PERIOD__)

#define	IS_FMC_READ_BURST(__RBURST__)

#define	IS_FMC_READPIPE_DELAY(__DELAY__)

#define	IS_FMC_COMMAND_MODE(__COMMAND__)

#define	IS_FMC_COMMAND_TARGET(__TARGET__)

#define	IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

#define	IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

#define	IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))

#define	IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

#define	IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))

#define	IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

#define	IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

#define	IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))

#define	IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)

#define	IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)

#define	IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)

#define	IS_FMC_SDRAM_BANK(__BANK__)

#define	IS_FMC_COLUMNBITS_NUMBER(__COLUMN__)

#define	IS_FMC_ROWBITS_NUMBER(__ROW__)

#define	IS_FMC_INTERNALBANK_NUMBER(__NUMBER__)

#define	IS_FMC_CAS_LATENCY(__LATENCY__)

#define	FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef

#define	FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef

#define	FMC_NAND_TypeDef FMC_Bank3_TypeDef

#define	FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef

#define	FMC_NORSRAM_DEVICE FMC_Bank1_R

#define	FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R

#define	FMC_NAND_DEVICE FMC_Bank3_R

#define	FMC_SDRAM_DEVICE FMC_Bank5_6_R

#define	FMC_NORSRAM_BANK1 (0x00000000U)

#define	FMC_NORSRAM_BANK2 (0x00000002U)

#define	FMC_NORSRAM_BANK3 (0x00000004U)

#define	FMC_NORSRAM_BANK4 (0x00000006U)

#define	FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)

#define	FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)

#define	FMC_MEMORY_TYPE_SRAM (0x00000000U)

#define	FMC_MEMORY_TYPE_PSRAM (0x00000004U)

#define	FMC_MEMORY_TYPE_NOR (0x00000008U)

#define	FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)

#define	FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)

#define	FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)

#define	FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)

#define	FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)

#define	FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)

#define	FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)

#define	FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)

#define	FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)

#define	FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)

#define	FMC_WAIT_TIMING_DURING_WS (0x00000800U)

#define	FMC_WRITE_OPERATION_DISABLE (0x00000000U)

#define	FMC_WRITE_OPERATION_ENABLE (0x00001000U)

#define	FMC_WAIT_SIGNAL_DISABLE (0x00000000U)

#define	FMC_WAIT_SIGNAL_ENABLE (0x00002000U)

#define	FMC_EXTENDED_MODE_DISABLE (0x00000000U)

#define	FMC_EXTENDED_MODE_ENABLE (0x00004000U)

#define	FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)

#define	FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)

#define	FMC_PAGE_SIZE_NONE (0x00000000U)

#define	FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0

#define	FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1

#define	FMC_PAGE_SIZE_512

#define	FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2

#define	FMC_WRITE_BURST_DISABLE (0x00000000U)

#define	FMC_WRITE_BURST_ENABLE (0x00080000U)

#define	FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)

#define	FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)

#define	FMC_ACCESS_MODE_A (0x00000000U)

#define	FMC_ACCESS_MODE_B (0x10000000U)

#define	FMC_ACCESS_MODE_C (0x20000000U)

#define	FMC_ACCESS_MODE_D (0x30000000U)

#define	FMC_NAND_BANK3 (0x00000100U)

#define	FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)

#define	FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)

#define	FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)

#define	FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)

#define	FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)

#define	FMC_NAND_ECC_DISABLE (0x00000000U)

#define	FMC_NAND_ECC_ENABLE (0x00000040U)

#define	FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)

#define	FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)

#define	FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)

#define	FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)

#define	FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)

#define	FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)

#define	FMC_SDRAM_BANK1 (0x00000000U)

#define	FMC_SDRAM_BANK2 (0x00000001U)

#define	FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U)

#define	FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U)

#define	FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U)

#define	FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U)

#define	FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U)

#define	FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U)

#define	FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U)

#define	FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U)

#define	FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U)

#define	FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U)

#define	FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U)

#define	FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U)

#define	FMC_SDRAM_CAS_LATENCY_1 (0x00000080U)

#define	FMC_SDRAM_CAS_LATENCY_2 (0x00000100U)

#define	FMC_SDRAM_CAS_LATENCY_3 (0x00000180U)

#define	FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U)

#define	FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U)

#define	FMC_SDRAM_CLOCK_DISABLE (0x00000000U)

#define	FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U)

#define	FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U)

#define	FMC_SDRAM_RBURST_DISABLE (0x00000000U)

#define	FMC_SDRAM_RBURST_ENABLE (0x00001000U)

#define	FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U)

#define	FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U)

#define	FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U)

#define	FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U)

#define	FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U)

#define	FMC_SDRAM_CMD_PALL (0x00000002U)

#define	FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U)

#define	FMC_SDRAM_CMD_LOAD_MODE (0x00000004U)

#define	FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U)

#define	FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U)

#define	FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2

#define	FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1

#define	FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U)

#define	FMC_SDRAM_NORMAL_MODE (0x00000000U)

#define	FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0

#define	FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1

#define	FMC_IT_RISING_EDGE (0x00000008U)

#define	FMC_IT_LEVEL (0x00000010U)

#define	FMC_IT_FALLING_EDGE (0x00000020U)

#define	FMC_IT_REFRESH_ERROR (0x00004000U)

#define	FMC_FLAG_RISING_EDGE (0x00000001U)

#define	FMC_FLAG_LEVEL (0x00000002U)

#define	FMC_FLAG_FALLING_EDGE (0x00000004U)

#define	FMC_FLAG_FEMPT (0x00000040U)

#define	FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE

#define	FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY

#define	FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE

#define	__FMC_ENABLE() (FMC_Bank1_R->BTCR[0] \|= FMC_BCR1_FMCEN)
	Enable the FMC Peripheral.

#define	__FMC_DISABLE() (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)
	Disable the FMC Peripheral.

#define	__FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)
	Enable the NORSRAM device access.

#define	__FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__)
	Disable the NORSRAM device access.

#define	__FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
	Enable the NAND device access.

#define	__FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
	Disable the NAND device access.

#define	__FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
	Enable the NAND device interrupt.

#define	__FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
	Disable the NAND device interrupt.

#define	__FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
	Get flag status of the NAND device.

#define	__FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
	Clear flag status of the NAND device.

#define	__FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
	Enable the SDRAM device interrupt.

#define	__FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
	Disable the SDRAM device interrupt.

#define	__FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
	Get flag status of the SDRAM device.

#define	__FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
	Clear flag status of the SDRAM device.

Functions
HAL_StatusTypeDef	FMC_NORSRAM_Init (FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init)

HAL_StatusTypeDef	FMC_NORSRAM_Timing_Init (FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank)

HAL_StatusTypeDef	FMC_NORSRAM_Extended_Timing_Init (FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode)

HAL_StatusTypeDef	FMC_NORSRAM_DeInit (FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank)

HAL_StatusTypeDef	FMC_NORSRAM_WriteOperation_Enable (FMC_NORSRAM_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_NORSRAM_WriteOperation_Disable (FMC_NORSRAM_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_Init (FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init)

HAL_StatusTypeDef	FMC_NAND_CommonSpace_Timing_Init (FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_AttributeSpace_Timing_Init (FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_DeInit (FMC_NAND_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_ECC_Enable (FMC_NAND_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_ECC_Disable (FMC_NAND_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_NAND_GetECC (FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout)

HAL_StatusTypeDef	FMC_SDRAM_Init (FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init)

HAL_StatusTypeDef	FMC_SDRAM_Timing_Init (FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank)

HAL_StatusTypeDef	FMC_SDRAM_DeInit (FMC_SDRAM_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_SDRAM_WriteProtection_Enable (FMC_SDRAM_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_SDRAM_WriteProtection_Disable (FMC_SDRAM_TypeDef *Device, uint32_t Bank)

HAL_StatusTypeDef	FMC_SDRAM_SendCommand (FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout)

HAL_StatusTypeDef	FMC_SDRAM_ProgramRefreshRate (FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)

HAL_StatusTypeDef	FMC_SDRAM_SetAutoRefreshNumber (FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)

uint32_t	FMC_SDRAM_GetModeStatus (FMC_SDRAM_TypeDef *Device, uint32_t Bank)

Detailed Description

Header file of FMC HAL module.

Author: MCD Application Team

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Data Structures

Macros

Functions

Detailed Description