RTEMS 6.1-rc2
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This header file defines the IRQAMP register block interface. More...
#include <stdint.h>
Go to the source code of this file.
Data Structures | |
struct | irqamp_timestamp |
This structure defines the IRQ(A)MP Timestamp register block memory map. More... | |
struct | irqamp |
This structure defines the IRQ(A)MP register block memory map. More... | |
Macros | |
#define | IRQAMP_ITCNT_TCNT_SHIFT 0 |
#define | IRQAMP_ITCNT_TCNT_MASK 0xffffffffU |
#define | IRQAMP_ITCNT_TCNT_GET(_reg) |
#define | IRQAMP_ITCNT_TCNT_SET(_reg, _val) |
#define | IRQAMP_ITCNT_TCNT(_val) |
#define | IRQAMP_ITSTMPC_TSTAMP_SHIFT 27 |
#define | IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U |
#define | IRQAMP_ITSTMPC_TSTAMP_GET(_reg) |
#define | IRQAMP_ITSTMPC_TSTAMP_SET(_reg, _val) |
#define | IRQAMP_ITSTMPC_TSTAMP(_val) |
#define | IRQAMP_ITSTMPC_S1 0x4000000U |
#define | IRQAMP_ITSTMPC_S2 0x2000000U |
#define | IRQAMP_ITSTMPC_KS 0x20U |
#define | IRQAMP_ITSTMPC_TSISEL_SHIFT 0 |
#define | IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU |
#define | IRQAMP_ITSTMPC_TSISEL_GET(_reg) |
#define | IRQAMP_ITSTMPC_TSISEL_SET(_reg, _val) |
#define | IRQAMP_ITSTMPC_TSISEL(_val) |
#define | IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0 |
#define | IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU |
#define | IRQAMP_ITSTMPAS_TASSERTION_GET(_reg) |
#define | IRQAMP_ITSTMPAS_TASSERTION_SET(_reg, _val) |
#define | IRQAMP_ITSTMPAS_TASSERTION(_val) |
#define | IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0 |
#define | IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU |
#define | IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET(_reg) |
#define | IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET(_reg, _val) |
#define | IRQAMP_ITSTMPAC_TACKNOWLEDGE(_val) |
#define | IRQAMP_ILEVEL_IL_15_1_SHIFT 1 |
#define | IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU |
#define | IRQAMP_ILEVEL_IL_15_1_GET(_reg) |
#define | IRQAMP_ILEVEL_IL_15_1_SET(_reg, _val) |
#define | IRQAMP_ILEVEL_IL_15_1(_val) |
#define | IRQAMP_IPEND_EIP_31_16_SHIFT 16 |
#define | IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U |
#define | IRQAMP_IPEND_EIP_31_16_GET(_reg) |
#define | IRQAMP_IPEND_EIP_31_16_SET(_reg, _val) |
#define | IRQAMP_IPEND_EIP_31_16(_val) |
#define | IRQAMP_IPEND_IP_15_1_SHIFT 1 |
#define | IRQAMP_IPEND_IP_15_1_MASK 0xfffeU |
#define | IRQAMP_IPEND_IP_15_1_GET(_reg) |
#define | IRQAMP_IPEND_IP_15_1_SET(_reg, _val) |
#define | IRQAMP_IPEND_IP_15_1(_val) |
#define | IRQAMP_IFORCE0_IF_15_1_SHIFT 1 |
#define | IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU |
#define | IRQAMP_IFORCE0_IF_15_1_GET(_reg) |
#define | IRQAMP_IFORCE0_IF_15_1_SET(_reg, _val) |
#define | IRQAMP_IFORCE0_IF_15_1(_val) |
#define | IRQAMP_ICLEAR_EIC_31_16_SHIFT 16 |
#define | IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U |
#define | IRQAMP_ICLEAR_EIC_31_16_GET(_reg) |
#define | IRQAMP_ICLEAR_EIC_31_16_SET(_reg, _val) |
#define | IRQAMP_ICLEAR_EIC_31_16(_val) |
#define | IRQAMP_ICLEAR_IC_15_1_SHIFT 1 |
#define | IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU |
#define | IRQAMP_ICLEAR_IC_15_1_GET(_reg) |
#define | IRQAMP_ICLEAR_IC_15_1_SET(_reg, _val) |
#define | IRQAMP_ICLEAR_IC_15_1(_val) |
#define | IRQAMP_MPSTAT_NCPU_SHIFT 28 |
#define | IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U |
#define | IRQAMP_MPSTAT_NCPU_GET(_reg) |
#define | IRQAMP_MPSTAT_NCPU_SET(_reg, _val) |
#define | IRQAMP_MPSTAT_NCPU(_val) |
#define | IRQAMP_MPSTAT_BA 0x8000000U |
#define | IRQAMP_MPSTAT_ER 0x4000000U |
#define | IRQAMP_MPSTAT_EIRQ_SHIFT 16 |
#define | IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U |
#define | IRQAMP_MPSTAT_EIRQ_GET(_reg) |
#define | IRQAMP_MPSTAT_EIRQ_SET(_reg, _val) |
#define | IRQAMP_MPSTAT_EIRQ(_val) |
#define | IRQAMP_MPSTAT_STATUS_SHIFT 0 |
#define | IRQAMP_MPSTAT_STATUS_MASK 0xfU |
#define | IRQAMP_MPSTAT_STATUS_GET(_reg) |
#define | IRQAMP_MPSTAT_STATUS_SET(_reg, _val) |
#define | IRQAMP_MPSTAT_STATUS(_val) |
#define | IRQAMP_BRDCST_BM15_1_SHIFT 1 |
#define | IRQAMP_BRDCST_BM15_1_MASK 0xfffeU |
#define | IRQAMP_BRDCST_BM15_1_GET(_reg) |
#define | IRQAMP_BRDCST_BM15_1_SET(_reg, _val) |
#define | IRQAMP_BRDCST_BM15_1(_val) |
#define | IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0 |
#define | IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU |
#define | IRQAMP_ERRSTAT_ERRMODE_3_0_GET(_reg) |
#define | IRQAMP_ERRSTAT_ERRMODE_3_0_SET(_reg, _val) |
#define | IRQAMP_ERRSTAT_ERRMODE_3_0(_val) |
#define | IRQAMP_WDOGCTRL_NWDOG_SHIFT 27 |
#define | IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U |
#define | IRQAMP_WDOGCTRL_NWDOG_GET(_reg) |
#define | IRQAMP_WDOGCTRL_NWDOG_SET(_reg, _val) |
#define | IRQAMP_WDOGCTRL_NWDOG(_val) |
#define | IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16 |
#define | IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U |
#define | IRQAMP_WDOGCTRL_WDOGIRQ_GET(_reg) |
#define | IRQAMP_WDOGCTRL_WDOGIRQ_SET(_reg, _val) |
#define | IRQAMP_WDOGCTRL_WDOGIRQ(_val) |
#define | IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0 |
#define | IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU |
#define | IRQAMP_WDOGCTRL_WDOGMSK_GET(_reg) |
#define | IRQAMP_WDOGCTRL_WDOGMSK_SET(_reg, _val) |
#define | IRQAMP_WDOGCTRL_WDOGMSK(_val) |
#define | IRQAMP_ASMPCTRL_NCTRL_SHIFT 28 |
#define | IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U |
#define | IRQAMP_ASMPCTRL_NCTRL_GET(_reg) |
#define | IRQAMP_ASMPCTRL_NCTRL_SET(_reg, _val) |
#define | IRQAMP_ASMPCTRL_NCTRL(_val) |
#define | IRQAMP_ASMPCTRL_ICF 0x2U |
#define | IRQAMP_ASMPCTRL_L 0x1U |
#define | IRQAMP_ICSELR_ICSEL0_SHIFT 28 |
#define | IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U |
#define | IRQAMP_ICSELR_ICSEL0_GET(_reg) |
#define | IRQAMP_ICSELR_ICSEL0_SET(_reg, _val) |
#define | IRQAMP_ICSELR_ICSEL0(_val) |
#define | IRQAMP_ICSELR_ICSEL1_SHIFT 24 |
#define | IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U |
#define | IRQAMP_ICSELR_ICSEL1_GET(_reg) |
#define | IRQAMP_ICSELR_ICSEL1_SET(_reg, _val) |
#define | IRQAMP_ICSELR_ICSEL1(_val) |
#define | IRQAMP_ICSELR_ICSEL2_SHIFT 20 |
#define | IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U |
#define | IRQAMP_ICSELR_ICSEL2_GET(_reg) |
#define | IRQAMP_ICSELR_ICSEL2_SET(_reg, _val) |
#define | IRQAMP_ICSELR_ICSEL2(_val) |
#define | IRQAMP_ICSELR_ICSEL3_SHIFT 16 |
#define | IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U |
#define | IRQAMP_ICSELR_ICSEL3_GET(_reg) |
#define | IRQAMP_ICSELR_ICSEL3_SET(_reg, _val) |
#define | IRQAMP_ICSELR_ICSEL3(_val) |
#define | IRQAMP_PIMASK_EIM_31_16_SHIFT 16 |
#define | IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U |
#define | IRQAMP_PIMASK_EIM_31_16_GET(_reg) |
#define | IRQAMP_PIMASK_EIM_31_16_SET(_reg, _val) |
#define | IRQAMP_PIMASK_EIM_31_16(_val) |
#define | IRQAMP_PIMASK_IM15_1_SHIFT 1 |
#define | IRQAMP_PIMASK_IM15_1_MASK 0xfffeU |
#define | IRQAMP_PIMASK_IM15_1_GET(_reg) |
#define | IRQAMP_PIMASK_IM15_1_SET(_reg, _val) |
#define | IRQAMP_PIMASK_IM15_1(_val) |
#define | IRQAMP_PIFORCE_FC_15_1_SHIFT 17 |
#define | IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U |
#define | IRQAMP_PIFORCE_FC_15_1_GET(_reg) |
#define | IRQAMP_PIFORCE_FC_15_1_SET(_reg, _val) |
#define | IRQAMP_PIFORCE_FC_15_1(_val) |
#define | IRQAMP_PIFORCE_IF15_1_SHIFT 1 |
#define | IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU |
#define | IRQAMP_PIFORCE_IF15_1_GET(_reg) |
#define | IRQAMP_PIFORCE_IF15_1_SET(_reg, _val) |
#define | IRQAMP_PIFORCE_IF15_1(_val) |
#define | IRQAMP_PEXTACK_EID_4_0_SHIFT 0 |
#define | IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU |
#define | IRQAMP_PEXTACK_EID_4_0_GET(_reg) |
#define | IRQAMP_PEXTACK_EID_4_0_SET(_reg, _val) |
#define | IRQAMP_PEXTACK_EID_4_0(_val) |
#define | IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3 |
#define | IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U |
#define | IRQAMP_BADDR_BOOTADDR_31_3_GET(_reg) |
#define | IRQAMP_BADDR_BOOTADDR_31_3_SET(_reg, _val) |
#define | IRQAMP_BADDR_BOOTADDR_31_3(_val) |
#define | IRQAMP_BADDR_AS 0x1U |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24 |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_0_GET(_reg) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_0_SET(_reg, _val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_0(_val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16 |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_1_GET(_reg) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_1_SET(_reg, _val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_1(_val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8 |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_2_GET(_reg) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_2_SET(_reg, _val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_2(_val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0 |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_3_GET(_reg) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_3_SET(_reg, _val) |
#define | IRQAMP_IRQMAP_IRQMAP_4_N_3(_val) |
Typedefs | |
typedef struct irqamp_timestamp | irqamp_timestamp |
This structure defines the IRQ(A)MP Timestamp register block memory map. | |
typedef struct irqamp | irqamp |
This structure defines the IRQ(A)MP register block memory map. | |
This header file defines the IRQAMP register block interface.