Interrupt pending register (IPEND)

This group contains register bit definitions. More...

Macros
#define	IRQAMP_IPEND_EIP_31_16_SHIFT   16
#define	IRQAMP_IPEND_EIP_31_16_MASK   0xffff0000U
#define	IRQAMP_IPEND_EIP_31_16_GET(_reg)
#define	IRQAMP_IPEND_EIP_31_16_SET(_reg, _val)
#define	IRQAMP_IPEND_EIP_31_16(_val)
#define	IRQAMP_IPEND_IP_15_1_SHIFT   1
#define	IRQAMP_IPEND_IP_15_1_MASK   0xfffeU
#define	IRQAMP_IPEND_IP_15_1_GET(_reg)
#define	IRQAMP_IPEND_IP_15_1_SET(_reg, _val)
#define	IRQAMP_IPEND_IP_15_1(_val)

Detailed Description

This group contains register bit definitions.

Macro Definition Documentation

IRQAMP_IPEND_EIP_31_16

#define IRQAMP_IPEND_EIP_31_16

(

_val

)

Value:

  ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
    IRQAMP_IPEND_EIP_31_16_MASK )

IRQAMP_IPEND_EIP_31_16_GET

#define IRQAMP_IPEND_EIP_31_16_GET

(

_reg

)

Value:

  ( ( ( _reg ) & IRQAMP_IPEND_EIP_31_16_MASK ) >> \
    IRQAMP_IPEND_EIP_31_16_SHIFT )

IRQAMP_IPEND_EIP_31_16_SET

#define IRQAMP_IPEND_EIP_31_16_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \
    ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
      IRQAMP_IPEND_EIP_31_16_MASK ) )

IRQAMP_IPEND_IP_15_1

#define IRQAMP_IPEND_IP_15_1

(

_val

)

Value:

  ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
    IRQAMP_IPEND_IP_15_1_MASK )

IRQAMP_IPEND_IP_15_1_GET

#define IRQAMP_IPEND_IP_15_1_GET

(

_reg

)

Value:

  ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> \
    IRQAMP_IPEND_IP_15_1_SHIFT )

IRQAMP_IPEND_IP_15_1_SET

#define IRQAMP_IPEND_IP_15_1_SET	(		_reg,
			_val
	)

Value:

  ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \
    ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
      IRQAMP_IPEND_IP_15_1_MASK ) )