Functions
void	Xil_DCacheEnable (void)
	Enable the Data cache.

void	Xil_DCacheDisable (void)
	Disable the Data cache.

void	Xil_DCacheInvalidate (void)
	Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.

void	Xil_DCacheInvalidateRange (INTPTR adr, u32 len)
	Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache,the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

void	Xil_DCacheFlush (void)
	Flush the Data cache.

void	Xil_DCacheFlushRange (INTPTR adr, u32 len)
	Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing those bytes is invalidated.If the cacheline is modified (dirty), the written to system memory before the lines are invalidated.

void	Xil_DCacheInvalidateLine (INTPTR adr)
	Invalidate a Data cache line. The cacheline is cleaned and invalidated.

void	Xil_DCacheFlushLine (INTPTR adr)
	Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.

void	Xil_DCacheStoreLine (INTPTR adr)
	Store a Data cache line. If the byte specified by the address (adr) is cached by the Data cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory.After the store completes, the cacheline is marked as unmodified (not dirty).

void	Xil_ICacheEnable (void)
	Enable the instruction cache.

void	Xil_ICacheDisable (void)
	Disable the instruction cache.

void	Xil_ICacheInvalidate (void)
	Invalidate the entire instruction cache.

void	Xil_ICacheInvalidateRange (INTPTR adr, u32 len)
	Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cachelineis modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

void	Xil_ICacheInvalidateLine (INTPTR adr)
	Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Detailed Description

Cache functions provide access to cache related operations such as flush and invalidate for instruction and data caches. It gives option to perform the cache operations on a single cacheline, a range of memory and an entire cache.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -----------------------------------------------
5.00    pkp  02/20/14 First release
6.2   mus  01/27/17 Updated to support IAR compiler

Function Documentation

◆ Xil_DCacheDisable()

void Xil_DCacheDisable ( void )

Disable the Data cache.

Returns: None.

Returns: None.

◆ Xil_DCacheEnable()

void Xil_DCacheEnable ( void )

Enable the Data cache.

Returns: None.

Returns: None.

◆ Xil_DCacheFlush()

void Xil_DCacheFlush ( void )

Flush the Data cache.

Returns: None.

Flush the Data cache.

Returns: None.

◆ Xil_DCacheFlushLine()

void Xil_DCacheFlushLine ( INTPTR adr )

Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.

Parameters

adr	64bit address of the data to be flushed.

Returns: None.

Note: The bottom 6 bits are set to 0, forced by architecture.

Parameters

adr	32bit address of the data to be flushed.

Returns: None.

Note: The bottom 5 bits are set to 0, forced by architecture.

◆ Xil_DCacheFlushRange()

void Xil_DCacheFlushRange	(	INTPTR	adr,
		u32	len
	)

Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing those bytes is invalidated.If the cacheline is modified (dirty), the written to system memory before the lines are invalidated.

Parameters

adr	32bit start address of the range to be flushed.
len	Length of the range to be flushed in bytes

Returns: None.

◆ Xil_DCacheInvalidate()

void Xil_DCacheInvalidate ( void )

Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.

Returns: None.

Note: In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.

Returns: None.

◆ Xil_DCacheInvalidateLine()

void Xil_DCacheInvalidateLine ( INTPTR adr )

Invalidate a Data cache line. The cacheline is cleaned and invalidated.

Parameters

adr	64bit address of the data to be flushed.

Returns: None.

Note: In Cortex-A53, functionality to simply invalid the cachelines is not present. Such operations are a problem for an environment that supports virtualisation. It would allow one OS to invalidate a line belonging to another OS. This could lead to the other OS crashing because of the loss of essential data. Hence, such operations are promoted to clean and invalidate which avoids such corruption.

Invalidate a Data cache line. The cacheline is cleaned and invalidated.

Parameters

adr	32bit address of the data to be flushed.

Returns: None.

Note: The bottom 5 bits are set to 0, forced by architecture.

◆ Xil_DCacheInvalidateRange()

void Xil_DCacheInvalidateRange	(	INTPTR	adr,
		u32	len
	)

Invalidate the Data cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache,the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Parameters

adr	32bit start address of the range to be invalidated.
len	Length of range to be invalidated in bytes.

Returns: None.

◆ Xil_DCacheStoreLine()

void Xil_DCacheStoreLine ( INTPTR adr )

Store a Data cache line. If the byte specified by the address (adr) is cached by the Data cache and the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory.After the store completes, the cacheline is marked as unmodified (not dirty).

Parameters

adr	32bit address of the data to be stored

Returns: None.

Note: The bottom 5 bits are set to 0, forced by architecture.

◆ Xil_ICacheDisable()

void Xil_ICacheDisable ( void )

Disable the instruction cache.

Returns: None.

Returns: None.

◆ Xil_ICacheEnable()

void Xil_ICacheEnable ( void )

Enable the instruction cache.

Returns: None.

Returns: None.

◆ Xil_ICacheInvalidate()

void Xil_ICacheInvalidate ( void )

Invalidate the entire instruction cache.

Returns: None.

Returns: None.

◆ Xil_ICacheInvalidateLine()

void Xil_ICacheInvalidateLine ( INTPTR adr )

Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Parameters

adr	64bit address of the instruction to be invalidated.

Returns: None.

Note: The bottom 6 bits are set to 0, forced by architecture.

Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Parameters

adr	32bit address of the instruction to be invalidated.

Returns: None.

Note: The bottom 5 bits are set to 0, forced by architecture.

◆ Xil_ICacheInvalidateRange()

void Xil_ICacheInvalidateRange	(	INTPTR	adr,
		u32	len
	)

Invalidate the instruction cache for the given address range. If the bytes specified by the address (adr) are cached by the Data cache, the cacheline containing that byte is invalidated. If the cachelineis modified (dirty), the modified contents are lost and are NOT written to system memory before the line is invalidated.

Parameters

adr	32bit start address of the range to be invalidated.
len	Length of the range to be invalidated in bytes.

Returns: None.

Functions

Detailed Description

Function Documentation

◆ Xil_DCacheDisable()

◆ Xil_DCacheEnable()

◆ Xil_DCacheFlush()

◆ Xil_DCacheFlushLine()

◆ Xil_DCacheFlushRange()

◆ Xil_DCacheInvalidate()

◆ Xil_DCacheInvalidateLine()

◆ Xil_DCacheInvalidateRange()

◆ Xil_DCacheStoreLine()

◆ Xil_ICacheDisable()

◆ Xil_ICacheEnable()

◆ Xil_ICacheInvalidate()

◆ Xil_ICacheInvalidateLine()

◆ Xil_ICacheInvalidateRange()