Macros
#define	Xil_ExceptionEnableMask(Mask)
	Enable Exceptions.

#define	Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
	Enable the IRQ exception.

#define	Xil_ExceptionDisableMask(Mask)
	Disable Exceptions.

#define	Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

#define	Xil_EnableNestedInterrupts()
	Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_DisableNestedInterrupts()
	Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_ExceptionEnableMask(Mask)
	Enable Exceptions.

#define	Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
	Enable the IRQ exception.

#define	Xil_ExceptionDisableMask(Mask)
	Disable Exceptions.

#define	Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

#define	Xil_EnableNestedInterrupts()
	Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_DisableNestedInterrupts()
	Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_ExceptionEnableMask(Mask)
	Enable Exceptions.

#define	Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
	Enable the IRQ exception.

#define	Xil_ExceptionDisableMask(Mask)
	Disable Exceptions.

#define	Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

#define	Xil_EnableNestedInterrupts()
	Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_DisableNestedInterrupts()
	Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_ExceptionEnableMask(Mask)
	Enable Exceptions.

#define	Xil_ExceptionEnable() Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
	Enable the IRQ exception.

#define	Xil_ExceptionDisableMask(Mask)
	Disable Exceptions.

#define	Xil_ExceptionDisable() Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

#define	Xil_EnableNestedInterrupts()
	Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

#define	Xil_DisableNestedInterrupts()
	Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

Functions
void	Xil_ExceptionRegisterHandler (u32 Exception_id, Xil_ExceptionHandler Handler, void *Data)

void	Xil_ExceptionRemoveHandler (u32 Exception_id)

void	Xil_GetExceptionRegisterHandler (u32 Exception_id, Xil_ExceptionHandler Handler, void *Data)

void	Xil_ExceptionInit (void)

void	Xil_DataAbortHandler (void *CallBackRef)

void	Xil_PrefetchAbortHandler (void *CallBackRef)

void	Xil_UndefinedExceptionHandler (void *CallBackRef)

Detailed Description

ARM processors specific exception related APIs for cortex A53,A9 and R5 can utilized for enabling/disabling IRQ, registering/removing handler for exceptions or initializing exception vector table with null handler.

MODIFICATION HISTORY:

Ver   Who      Date     Changes
----- -------- -------- -----------------------------------------------
5.2 pkp      28/05/15 First release
6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
6.7   mna      26/04/18 Add API Xil_GetExceptionRegisterHandler.
6.7   asa      18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
7.0   mus      01/03/19 Tweak Xil_ExceptionEnableMask and
                        Xil_ExceptionDisableMask macros to support legacy
                        examples for Cortexa72 EL3 exception level.
7.3   mus      04/15/20 Added Xil_EnableNestedInterrupts and
                        Xil_DisableNestedInterrupts macros for ARMv8.
                        For Cortexa72, these macro's would not be supported
                        at EL3, as Cortexa72 is using GIC-500(GICv3),  which
                        triggeres only FIQ at EL3. Fix for CR#1062506
7.6   mus      09/17/21 Updated flag checking to fix warning reported with
                        -Wundef compiler option CR#1110261
7.7   mus      01/31/22 Few of the #defines in xil_exception.h in are treated
                        in different way based on "versal" flag. In existing
                        flow, this flag is defined only in xparameters.h and
                        BSP compiler flags, it is not defined in application
                        compiler flags. So, including xil_exception.h in
                        application source file, without including
                        xparameters.h results  in incorrect behavior.
                        Including xparameters.h in xil_exception.h to avoid
                        such issues. It fixes CR#1120498.
7.7 sk   03/02/22 Define XExc_VectorTableEntry structure to fix
              misra_c_2012_rule_5_6 violation.
7.7 sk   03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_
              rule_8_4 violation.

Macro Definition Documentation

◆ Xil_DisableNestedInterrupts [1/4]

#define Xil_DisableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
        __asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \

Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is meant to be called in the interrupt service routines. This macro cannot be used independently. It can only be used when nesting of interrupts have been enabled by using the macro Xil_EnableNestedInterrupts(). In a typical flow, the user first calls the Xil_EnableNestedInterrupts in the ISR at the appropriate point. The user then must call this macro before exiting the interrupt service routine. This macro puts the ARM back in IRQ/FIQ mode and hence sets back the I and F bits.

◆ Xil_DisableNestedInterrupts [2/4]

#define Xil_DisableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
        __asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \

Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is meant to be called in the interrupt service routines. This macro cannot be used independently. It can only be used when nesting of interrupts have been enabled by using the macro Xil_EnableNestedInterrupts(). In a typical flow, the user first calls the Xil_EnableNestedInterrupts in the ISR at the appropriate point. The user then must call this macro before exiting the interrupt service routine. This macro puts the ARM back in IRQ/FIQ mode and hence sets back the I and F bits.

◆ Xil_DisableNestedInterrupts [3/4]

#define Xil_DisableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
        __asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \

Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is meant to be called in the interrupt service routines. This macro cannot be used independently. It can only be used when nesting of interrupts have been enabled by using the macro Xil_EnableNestedInterrupts(). In a typical flow, the user first calls the Xil_EnableNestedInterrupts in the ISR at the appropriate point. The user then must call this macro before exiting the interrupt service routine. This macro puts the ARM back in IRQ/FIQ mode and hence sets back the I and F bits.

◆ Xil_DisableNestedInterrupts [4/4]

#define Xil_DisableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
        __asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
        __asm__ __volatile__ ("ldmfd   sp!, {lr}"); \

Disable the nested interrupts by setting the I and F bits. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is meant to be called in the interrupt service routines. This macro cannot be used independently. It can only be used when nesting of interrupts have been enabled by using the macro Xil_EnableNestedInterrupts(). In a typical flow, the user first calls the Xil_EnableNestedInterrupts in the ISR at the appropriate point. The user then must call this macro before exiting the interrupt service routine. This macro puts the ARM back in IRQ/FIQ mode and hence sets back the I and F bits.

◆ Xil_EnableNestedInterrupts [1/4]

#define Xil_EnableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("mrs     lr, spsr");  \
        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
        __asm__ __volatile__ ("stmfd   sp!, {lr}");

Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is supposed to be used from interrupt handlers. In the interrupt handler the interrupts are disabled by default (I and F are 1). To allow nesting of interrupts, this macro should be used. It clears the I and F bits by changing the ARM mode to system mode. Once these bits are cleared and provided the preemption of interrupt conditions are met in the GIC, nesting of interrupts will start happening. Caution: This macro must be used with caution. Before calling this macro, the user must ensure that the source of the current IRQ is appropriately cleared. Otherwise, as soon as we clear the I and F bits, there can be an infinite loop of interrupts with an eventual crash (all the stack space getting consumed).

◆ Xil_EnableNestedInterrupts [2/4]

#define Xil_EnableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("mrs     lr, spsr");  \
        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
        __asm__ __volatile__ ("stmfd   sp!, {lr}");

Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is supposed to be used from interrupt handlers. In the interrupt handler the interrupts are disabled by default (I and F are 1). To allow nesting of interrupts, this macro should be used. It clears the I and F bits by changing the ARM mode to system mode. Once these bits are cleared and provided the preemption of interrupt conditions are met in the GIC, nesting of interrupts will start happening. Caution: This macro must be used with caution. Before calling this macro, the user must ensure that the source of the current IRQ is appropriately cleared. Otherwise, as soon as we clear the I and F bits, there can be an infinite loop of interrupts with an eventual crash (all the stack space getting consumed).

◆ Xil_EnableNestedInterrupts [3/4]

#define Xil_EnableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("mrs     lr, spsr");  \
        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
        __asm__ __volatile__ ("stmfd   sp!, {lr}");

Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is supposed to be used from interrupt handlers. In the interrupt handler the interrupts are disabled by default (I and F are 1). To allow nesting of interrupts, this macro should be used. It clears the I and F bits by changing the ARM mode to system mode. Once these bits are cleared and provided the preemption of interrupt conditions are met in the GIC, nesting of interrupts will start happening. Caution: This macro must be used with caution. Before calling this macro, the user must ensure that the source of the current IRQ is appropriately cleared. Otherwise, as soon as we clear the I and F bits, there can be an infinite loop of interrupts with an eventual crash (all the stack space getting consumed).

◆ Xil_EnableNestedInterrupts [4/4]

#define Xil_EnableNestedInterrupts ( )

Value:

        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("mrs     lr, spsr");  \
        __asm__ __volatile__ ("stmfd   sp!, {lr}"); \
        __asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
        __asm__ __volatile__ ("stmfd   sp!, {lr}");

Enable nested interrupts by clearing the I and F bits in CPSR. This API is defined for cortex-a9 and cortex-r5.

Returns: None.

Note: This macro is supposed to be used from interrupt handlers. In the interrupt handler the interrupts are disabled by default (I and F are 1). To allow nesting of interrupts, this macro should be used. It clears the I and F bits by changing the ARM mode to system mode. Once these bits are cleared and provided the preemption of interrupt conditions are met in the GIC, nesting of interrupts will start happening. Caution: This macro must be used with caution. Before calling this macro, the user must ensure that the source of the current IRQ is appropriately cleared. Otherwise, as soon as we clear the I and F bits, there can be an infinite loop of interrupts with an eventual crash (all the stack space getting consumed).

◆ Xil_ExceptionDisable [1/4]

#define Xil_ExceptionDisable ( ) Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

Disable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionDisable [2/4]

#define Xil_ExceptionDisable ( ) Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

Disable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionDisable [3/4]

#define Xil_ExceptionDisable ( ) Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

Disable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionDisable [4/4]

#define Xil_ExceptionDisable ( ) Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)

Disable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionDisableMask [1/4]

#define Xil_ExceptionDisableMask ( Mask )

Value:

        {                                   \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
        }

Disable Exceptions.

Parameters

Mask	Value for disabling the exceptions.

Returns: None.

Note: If bit is 1, exception is disabled. C-Style signature: Xil_ExceptionDisableMask(Mask)

◆ Xil_ExceptionDisableMask [2/4]

#define Xil_ExceptionDisableMask ( Mask )

Value:

        {                                   \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
        }

Disable Exceptions.

Parameters

Mask	Value for disabling the exceptions.

Returns: None.

Note: If bit is 1, exception is disabled. C-Style signature: Xil_ExceptionDisableMask(Mask)

◆ Xil_ExceptionDisableMask [3/4]

#define Xil_ExceptionDisableMask ( Mask )

Value:

        {                                   \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
        }

Disable Exceptions.

Parameters

Mask	Value for disabling the exceptions.

Returns: None.

Note: If bit is 1, exception is disabled. C-Style signature: Xil_ExceptionDisableMask(Mask)

◆ Xil_ExceptionDisableMask [4/4]

#define Xil_ExceptionDisableMask ( Mask )

Value:

        {                                   \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
        }

Disable Exceptions.

Parameters

Mask	Value for disabling the exceptions.

Returns: None.

Note: If bit is 1, exception is disabled. C-Style signature: Xil_ExceptionDisableMask(Mask)

◆ Xil_ExceptionEnable [1/4]

#define Xil_ExceptionEnable ( ) Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)

Enable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionEnable [2/4]

#define Xil_ExceptionEnable ( ) Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)

Enable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionEnable [3/4]

#define Xil_ExceptionEnable ( ) Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)

Enable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionEnable [4/4]

#define Xil_ExceptionEnable ( ) Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)

Enable the IRQ exception.

Returns: None.

Note: None.

◆ Xil_ExceptionEnableMask [1/4]

#define Xil_ExceptionEnableMask ( Mask )

Value:

        {                               \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
        }

Enable Exceptions.

Parameters

Mask	Value for enabling the exceptions.

Returns: None.

Note: If bit is 0, exception is enabled. C-Style signature: void Xil_ExceptionEnableMask(Mask)

◆ Xil_ExceptionEnableMask [2/4]

#define Xil_ExceptionEnableMask ( Mask )

Value:

        {                               \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
        }

Enable Exceptions.

Parameters

Mask	Value for enabling the exceptions.

Returns: None.

Note: If bit is 0, exception is enabled. C-Style signature: void Xil_ExceptionEnableMask(Mask)

◆ Xil_ExceptionEnableMask [3/4]

#define Xil_ExceptionEnableMask ( Mask )

Value:

        {                               \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
        }

Enable Exceptions.

Parameters

Mask	Value for enabling the exceptions.

Returns: None.

Note: If bit is 0, exception is enabled. C-Style signature: void Xil_ExceptionEnableMask(Mask)

◆ Xil_ExceptionEnableMask [4/4]

#define Xil_ExceptionEnableMask ( Mask )

Value:

        {                               \
          register u32 Reg __asm("cpsr"); \
          mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
        }

Enable Exceptions.

Parameters

Mask	Value for enabling the exceptions.

Returns: None.

Note: If bit is 0, exception is enabled. C-Style signature: void Xil_ExceptionEnableMask(Mask)

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ Xil_DisableNestedInterrupts [1/4]

◆ Xil_DisableNestedInterrupts [2/4]

◆ Xil_DisableNestedInterrupts [3/4]

◆ Xil_DisableNestedInterrupts [4/4]

◆ Xil_EnableNestedInterrupts [1/4]

◆ Xil_EnableNestedInterrupts [2/4]

◆ Xil_EnableNestedInterrupts [3/4]

◆ Xil_EnableNestedInterrupts [4/4]

◆ Xil_ExceptionDisable [1/4]

◆ Xil_ExceptionDisable [2/4]

◆ Xil_ExceptionDisable [3/4]

◆ Xil_ExceptionDisable [4/4]

◆ Xil_ExceptionDisableMask [1/4]

◆ Xil_ExceptionDisableMask [2/4]

◆ Xil_ExceptionDisableMask [3/4]

◆ Xil_ExceptionDisableMask [4/4]

◆ Xil_ExceptionEnable [1/4]

◆ Xil_ExceptionEnable [2/4]

◆ Xil_ExceptionEnable [3/4]

◆ Xil_ExceptionEnable [4/4]

◆ Xil_ExceptionEnableMask [1/4]

◆ Xil_ExceptionEnableMask [2/4]

◆ Xil_ExceptionEnableMask [3/4]

◆ Xil_ExceptionEnableMask [4/4]