DS_ADDR - DMA System Address
#define	USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)

#define	USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)

#define	USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

BLK_ATT - Block Attributes
#define	USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)

#define	USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)

#define	USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

#define	USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)

#define	USDHC_BLK_ATT_BLKCNT_SHIFT (16U)

#define	USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

CMD_ARG - Command Argument
#define	USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_ARG_CMDARG_SHIFT (0U)

#define	USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMD_XFR_TYP - Command Transfer Type
#define	USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)

#define	USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)

#define	USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)

#define	USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)

#define	USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

#define	USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)

#define	USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)

#define	USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

#define	USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)

#define	USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)

#define	USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

#define	USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)

#define	USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)

#define	USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)

#define	USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)

#define	USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMD_RSP0 - Command Response0
#define	USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)

#define	USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMD_RSP1 - Command Response1
#define	USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)

#define	USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMD_RSP2 - Command Response2
#define	USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)

#define	USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMD_RSP3 - Command Response3
#define	USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)

#define	USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

DATA_BUFF_ACC_PORT - Data Buffer Access Port
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

PRES_STATE - Present State
#define	USDHC_PRES_STATE_CIHB_MASK (0x1U)

#define	USDHC_PRES_STATE_CIHB_SHIFT (0U)

#define	USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

#define	USDHC_PRES_STATE_CDIHB_MASK (0x2U)

#define	USDHC_PRES_STATE_CDIHB_SHIFT (1U)

#define	USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

#define	USDHC_PRES_STATE_DLA_MASK (0x4U)

#define	USDHC_PRES_STATE_DLA_SHIFT (2U)

#define	USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

#define	USDHC_PRES_STATE_SDSTB_MASK (0x8U)

#define	USDHC_PRES_STATE_SDSTB_SHIFT (3U)

#define	USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

#define	USDHC_PRES_STATE_IPGOFF_MASK (0x10U)

#define	USDHC_PRES_STATE_IPGOFF_SHIFT (4U)

#define	USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

#define	USDHC_PRES_STATE_HCKOFF_MASK (0x20U)

#define	USDHC_PRES_STATE_HCKOFF_SHIFT (5U)

#define	USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

#define	USDHC_PRES_STATE_PEROFF_MASK (0x40U)

#define	USDHC_PRES_STATE_PEROFF_SHIFT (6U)

#define	USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

#define	USDHC_PRES_STATE_SDOFF_MASK (0x80U)

#define	USDHC_PRES_STATE_SDOFF_SHIFT (7U)

#define	USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

#define	USDHC_PRES_STATE_WTA_MASK (0x100U)

#define	USDHC_PRES_STATE_WTA_SHIFT (8U)

#define	USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

#define	USDHC_PRES_STATE_RTA_MASK (0x200U)

#define	USDHC_PRES_STATE_RTA_SHIFT (9U)

#define	USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

#define	USDHC_PRES_STATE_BWEN_MASK (0x400U)

#define	USDHC_PRES_STATE_BWEN_SHIFT (10U)

#define	USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

#define	USDHC_PRES_STATE_BREN_MASK (0x800U)

#define	USDHC_PRES_STATE_BREN_SHIFT (11U)

#define	USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

#define	USDHC_PRES_STATE_RTR_MASK (0x1000U)

#define	USDHC_PRES_STATE_RTR_SHIFT (12U)

#define	USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

#define	USDHC_PRES_STATE_TSCD_MASK (0x8000U)

#define	USDHC_PRES_STATE_TSCD_SHIFT (15U)

#define	USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

#define	USDHC_PRES_STATE_CINST_MASK (0x10000U)

#define	USDHC_PRES_STATE_CINST_SHIFT (16U)

#define	USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

#define	USDHC_PRES_STATE_CDPL_MASK (0x40000U)

#define	USDHC_PRES_STATE_CDPL_SHIFT (18U)

#define	USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

#define	USDHC_PRES_STATE_WPSPL_MASK (0x80000U)

#define	USDHC_PRES_STATE_WPSPL_SHIFT (19U)

#define	USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

#define	USDHC_PRES_STATE_CLSL_MASK (0x800000U)

#define	USDHC_PRES_STATE_CLSL_SHIFT (23U)

#define	USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

#define	USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)

#define	USDHC_PRES_STATE_DLSL_SHIFT (24U)

#define	USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

PROT_CTRL - Protocol Control
#define	USDHC_PROT_CTRL_LCTL_MASK (0x1U)

#define	USDHC_PROT_CTRL_LCTL_SHIFT (0U)

#define	USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)

#define	USDHC_PROT_CTRL_DTW_MASK (0x6U)

#define	USDHC_PROT_CTRL_DTW_SHIFT (1U)

#define	USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

#define	USDHC_PROT_CTRL_D3CD_MASK (0x8U)

#define	USDHC_PROT_CTRL_D3CD_SHIFT (3U)

#define	USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

#define	USDHC_PROT_CTRL_EMODE_MASK (0x30U)

#define	USDHC_PROT_CTRL_EMODE_SHIFT (4U)

#define	USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

#define	USDHC_PROT_CTRL_CDTL_MASK (0x40U)

#define	USDHC_PROT_CTRL_CDTL_SHIFT (6U)

#define	USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

#define	USDHC_PROT_CTRL_CDSS_MASK (0x80U)

#define	USDHC_PROT_CTRL_CDSS_SHIFT (7U)

#define	USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

#define	USDHC_PROT_CTRL_DMASEL_MASK (0x300U)

#define	USDHC_PROT_CTRL_DMASEL_SHIFT (8U)

#define	USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

#define	USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)

#define	USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)

#define	USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

#define	USDHC_PROT_CTRL_CREQ_MASK (0x20000U)

#define	USDHC_PROT_CTRL_CREQ_SHIFT (17U)

#define	USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

#define	USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)

#define	USDHC_PROT_CTRL_RWCTL_SHIFT (18U)

#define	USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

#define	USDHC_PROT_CTRL_IABG_MASK (0x80000U)

#define	USDHC_PROT_CTRL_IABG_SHIFT (19U)

#define	USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

#define	USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)

#define	USDHC_PROT_CTRL_WECINT_SHIFT (24U)

#define	USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

#define	USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)

#define	USDHC_PROT_CTRL_WECINS_SHIFT (25U)

#define	USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

#define	USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)

#define	USDHC_PROT_CTRL_WECRM_SHIFT (26U)

#define	USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

#define	USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)

#define	USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)

#define	USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

SYS_CTRL - System Control
#define	USDHC_SYS_CTRL_DVS_MASK (0xF0U)

#define	USDHC_SYS_CTRL_DVS_SHIFT (4U)

#define	USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

#define	USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)

#define	USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)

#define	USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

#define	USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)

#define	USDHC_SYS_CTRL_DTOCV_SHIFT (16U)

#define	USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

#define	USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)

#define	USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)

#define	USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

#define	USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)

#define	USDHC_SYS_CTRL_RSTA_SHIFT (24U)

#define	USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

#define	USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)

#define	USDHC_SYS_CTRL_RSTC_SHIFT (25U)

#define	USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

#define	USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)

#define	USDHC_SYS_CTRL_RSTD_SHIFT (26U)

#define	USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

#define	USDHC_SYS_CTRL_INITA_MASK (0x8000000U)

#define	USDHC_SYS_CTRL_INITA_SHIFT (27U)

#define	USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

#define	USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)

#define	USDHC_SYS_CTRL_RSTT_SHIFT (28U)

#define	USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

INT_STATUS - Interrupt Status
#define	USDHC_INT_STATUS_CC_MASK (0x1U)

#define	USDHC_INT_STATUS_CC_SHIFT (0U)

#define	USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

#define	USDHC_INT_STATUS_TC_MASK (0x2U)

#define	USDHC_INT_STATUS_TC_SHIFT (1U)

#define	USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

#define	USDHC_INT_STATUS_BGE_MASK (0x4U)

#define	USDHC_INT_STATUS_BGE_SHIFT (2U)

#define	USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

#define	USDHC_INT_STATUS_DINT_MASK (0x8U)

#define	USDHC_INT_STATUS_DINT_SHIFT (3U)

#define	USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

#define	USDHC_INT_STATUS_BWR_MASK (0x10U)

#define	USDHC_INT_STATUS_BWR_SHIFT (4U)

#define	USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

#define	USDHC_INT_STATUS_BRR_MASK (0x20U)

#define	USDHC_INT_STATUS_BRR_SHIFT (5U)

#define	USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

#define	USDHC_INT_STATUS_CINS_MASK (0x40U)

#define	USDHC_INT_STATUS_CINS_SHIFT (6U)

#define	USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

#define	USDHC_INT_STATUS_CRM_MASK (0x80U)

#define	USDHC_INT_STATUS_CRM_SHIFT (7U)

#define	USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

#define	USDHC_INT_STATUS_CINT_MASK (0x100U)

#define	USDHC_INT_STATUS_CINT_SHIFT (8U)

#define	USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

#define	USDHC_INT_STATUS_RTE_MASK (0x1000U)

#define	USDHC_INT_STATUS_RTE_SHIFT (12U)

#define	USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

#define	USDHC_INT_STATUS_TP_MASK (0x4000U)

#define	USDHC_INT_STATUS_TP_SHIFT (14U)

#define	USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

#define	USDHC_INT_STATUS_CTOE_MASK (0x10000U)

#define	USDHC_INT_STATUS_CTOE_SHIFT (16U)

#define	USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

#define	USDHC_INT_STATUS_CCE_MASK (0x20000U)

#define	USDHC_INT_STATUS_CCE_SHIFT (17U)

#define	USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

#define	USDHC_INT_STATUS_CEBE_MASK (0x40000U)

#define	USDHC_INT_STATUS_CEBE_SHIFT (18U)

#define	USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

#define	USDHC_INT_STATUS_CIE_MASK (0x80000U)

#define	USDHC_INT_STATUS_CIE_SHIFT (19U)

#define	USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

#define	USDHC_INT_STATUS_DTOE_MASK (0x100000U)

#define	USDHC_INT_STATUS_DTOE_SHIFT (20U)

#define	USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

#define	USDHC_INT_STATUS_DCE_MASK (0x200000U)

#define	USDHC_INT_STATUS_DCE_SHIFT (21U)

#define	USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

#define	USDHC_INT_STATUS_DEBE_MASK (0x400000U)

#define	USDHC_INT_STATUS_DEBE_SHIFT (22U)

#define	USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

#define	USDHC_INT_STATUS_AC12E_MASK (0x1000000U)

#define	USDHC_INT_STATUS_AC12E_SHIFT (24U)

#define	USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

#define	USDHC_INT_STATUS_TNE_MASK (0x4000000U)

#define	USDHC_INT_STATUS_TNE_SHIFT (26U)

#define	USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

#define	USDHC_INT_STATUS_DMAE_MASK (0x10000000U)

#define	USDHC_INT_STATUS_DMAE_SHIFT (28U)

#define	USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

INT_STATUS_EN - Interrupt Status Enable
#define	USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)

#define	USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)

#define	USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

#define	USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)

#define	USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)

#define	USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

#define	USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)

#define	USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)

#define	USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

#define	USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)

#define	USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)

#define	USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)

#define	USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)

#define	USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

#define	USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)

#define	USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)

#define	USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)

#define	USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)

#define	USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

#define	USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)

#define	USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)

#define	USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)

#define	USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)

#define	USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)

#define	USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)

#define	USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

#define	USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)

#define	USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)

#define	USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

#define	USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)

#define	USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)

#define	USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)

#define	USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)

#define	USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

#define	USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)

#define	USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)

#define	USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)

#define	USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)

#define	USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

#define	USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)

#define	USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)

#define	USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)

#define	USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)

#define	USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

#define	USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)

#define	USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)

#define	USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)

#define	USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)

#define	USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

#define	USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)

#define	USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)

#define	USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

#define	USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)

#define	USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)

#define	USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

INT_SIGNAL_EN - Interrupt Signal Enable
#define	USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)

#define	USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)

#define	USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)

#define	USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)

#define	USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)

#define	USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)

#define	USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

HOST_CTRL_CAP - Host Controller Capabilities
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)

#define	USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)

#define	USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

#define	USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)

#define	USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)

#define	USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)

#define	USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)

#define	USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)

#define	USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

#define	USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)

#define	USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)

#define	USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)

#define	USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)

#define	USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

#define	USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)

#define	USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)

#define	USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)

#define	USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)

#define	USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

#define	USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)

#define	USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)

#define	USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

#define	USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)

#define	USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)

#define	USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

#define	USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)

#define	USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)

#define	USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

WTMK_LVL - Watermark Level
#define	USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)

#define	USDHC_WTMK_LVL_RD_WML_SHIFT (0U)

#define	USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

#define	USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)

#define	USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)

#define	USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)

#define	USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)

#define	USDHC_WTMK_LVL_WR_WML_SHIFT (16U)

#define	USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

#define	USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)

#define	USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)

#define	USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)

MIX_CTRL - Mixer Control
#define	USDHC_MIX_CTRL_DMAEN_MASK (0x1U)

#define	USDHC_MIX_CTRL_DMAEN_SHIFT (0U)

#define	USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

#define	USDHC_MIX_CTRL_BCEN_MASK (0x2U)

#define	USDHC_MIX_CTRL_BCEN_SHIFT (1U)

#define	USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

#define	USDHC_MIX_CTRL_AC12EN_MASK (0x4U)

#define	USDHC_MIX_CTRL_AC12EN_SHIFT (2U)

#define	USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

#define	USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)

#define	USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)

#define	USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

#define	USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)

#define	USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)

#define	USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

#define	USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)

#define	USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)

#define	USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

#define	USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)

#define	USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)

#define	USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

#define	USDHC_MIX_CTRL_AC23EN_MASK (0x80U)

#define	USDHC_MIX_CTRL_AC23EN_SHIFT (7U)

#define	USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

#define	USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)

#define	USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)

#define	USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

#define	USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)

#define	USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)

#define	USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

FORCE_EVENT - Force Event
#define	USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)

#define	USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)

#define	USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)

#define	USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)

#define	USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)

#define	USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)

#define	USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)

#define	USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)

#define	USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)

#define	USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)

#define	USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)

#define	USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)

#define	USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)

#define	USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)

#define	USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)

#define	USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)

#define	USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)

#define	USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)

#define	USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)

#define	USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)

#define	USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)

#define	USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)

#define	USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

ADMA_ERR_STATUS - ADMA Error Status
#define	USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMA_SYS_ADDR - ADMA System Address
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

DLL_CTRL - DLL (Delay Line) Control
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_STATUS - DLL Status
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

VEND_SPEC - Vendor Specific Register
#define	USDHC_VEND_SPEC_VSELECT_MASK (0x2U)

#define	USDHC_VEND_SPEC_VSELECT_SHIFT (1U)

#define	USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

MMC_BOOT - MMC Boot
#define	USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)

#define	USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)

#define	USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)

#define	USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)

#define	USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)

#define	USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)

#define	USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

#define	USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)

#define	USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)

#define	USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

VEND_SPEC2 - Vendor Specific 2 Register
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

TUNING_CTRL - Tuning Control
#define	USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

#define	USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)

#define	USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)

#define	USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

DS_ADDR - DMA System Address
#define	USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)

#define	USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)

#define	USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

BLK_ATT - Block Attributes
#define	USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)

#define	USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)

#define	USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

#define	USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)

#define	USDHC_BLK_ATT_BLKCNT_SHIFT (16U)

#define	USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

CMD_ARG - Command Argument
#define	USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_ARG_CMDARG_SHIFT (0U)

#define	USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMD_XFR_TYP - Command Transfer Type
#define	USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)

#define	USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)

#define	USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)

#define	USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)

#define	USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

#define	USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)

#define	USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)

#define	USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

#define	USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)

#define	USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)

#define	USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

#define	USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)

#define	USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)

#define	USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)

#define	USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)

#define	USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMD_RSP0 - Command Response0
#define	USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)

#define	USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMD_RSP1 - Command Response1
#define	USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)

#define	USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMD_RSP2 - Command Response2
#define	USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)

#define	USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMD_RSP3 - Command Response3
#define	USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)

#define	USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

DATA_BUFF_ACC_PORT - Data Buffer Access Port
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

PRES_STATE - Present State
#define	USDHC_PRES_STATE_CIHB_MASK (0x1U)

#define	USDHC_PRES_STATE_CIHB_SHIFT (0U)

#define	USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

#define	USDHC_PRES_STATE_CDIHB_MASK (0x2U)

#define	USDHC_PRES_STATE_CDIHB_SHIFT (1U)

#define	USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

#define	USDHC_PRES_STATE_DLA_MASK (0x4U)

#define	USDHC_PRES_STATE_DLA_SHIFT (2U)

#define	USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

#define	USDHC_PRES_STATE_SDSTB_MASK (0x8U)

#define	USDHC_PRES_STATE_SDSTB_SHIFT (3U)

#define	USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

#define	USDHC_PRES_STATE_IPGOFF_MASK (0x10U)

#define	USDHC_PRES_STATE_IPGOFF_SHIFT (4U)

#define	USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

#define	USDHC_PRES_STATE_HCKOFF_MASK (0x20U)

#define	USDHC_PRES_STATE_HCKOFF_SHIFT (5U)

#define	USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

#define	USDHC_PRES_STATE_PEROFF_MASK (0x40U)

#define	USDHC_PRES_STATE_PEROFF_SHIFT (6U)

#define	USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

#define	USDHC_PRES_STATE_SDOFF_MASK (0x80U)

#define	USDHC_PRES_STATE_SDOFF_SHIFT (7U)

#define	USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

#define	USDHC_PRES_STATE_WTA_MASK (0x100U)

#define	USDHC_PRES_STATE_WTA_SHIFT (8U)

#define	USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

#define	USDHC_PRES_STATE_RTA_MASK (0x200U)

#define	USDHC_PRES_STATE_RTA_SHIFT (9U)

#define	USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

#define	USDHC_PRES_STATE_BWEN_MASK (0x400U)

#define	USDHC_PRES_STATE_BWEN_SHIFT (10U)

#define	USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

#define	USDHC_PRES_STATE_BREN_MASK (0x800U)

#define	USDHC_PRES_STATE_BREN_SHIFT (11U)

#define	USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

#define	USDHC_PRES_STATE_RTR_MASK (0x1000U)

#define	USDHC_PRES_STATE_RTR_SHIFT (12U)

#define	USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

#define	USDHC_PRES_STATE_TSCD_MASK (0x8000U)

#define	USDHC_PRES_STATE_TSCD_SHIFT (15U)

#define	USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

#define	USDHC_PRES_STATE_CINST_MASK (0x10000U)

#define	USDHC_PRES_STATE_CINST_SHIFT (16U)

#define	USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

#define	USDHC_PRES_STATE_CDPL_MASK (0x40000U)

#define	USDHC_PRES_STATE_CDPL_SHIFT (18U)

#define	USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

#define	USDHC_PRES_STATE_WPSPL_MASK (0x80000U)

#define	USDHC_PRES_STATE_WPSPL_SHIFT (19U)

#define	USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

#define	USDHC_PRES_STATE_CLSL_MASK (0x800000U)

#define	USDHC_PRES_STATE_CLSL_SHIFT (23U)

#define	USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

#define	USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)

#define	USDHC_PRES_STATE_DLSL_SHIFT (24U)

#define	USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

PROT_CTRL - Protocol Control
#define	USDHC_PROT_CTRL_DTW_MASK (0x6U)

#define	USDHC_PROT_CTRL_DTW_SHIFT (1U)

#define	USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

#define	USDHC_PROT_CTRL_D3CD_MASK (0x8U)

#define	USDHC_PROT_CTRL_D3CD_SHIFT (3U)

#define	USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

#define	USDHC_PROT_CTRL_EMODE_MASK (0x30U)

#define	USDHC_PROT_CTRL_EMODE_SHIFT (4U)

#define	USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

#define	USDHC_PROT_CTRL_CDTL_MASK (0x40U)

#define	USDHC_PROT_CTRL_CDTL_SHIFT (6U)

#define	USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

#define	USDHC_PROT_CTRL_CDSS_MASK (0x80U)

#define	USDHC_PROT_CTRL_CDSS_SHIFT (7U)

#define	USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

#define	USDHC_PROT_CTRL_DMASEL_MASK (0x300U)

#define	USDHC_PROT_CTRL_DMASEL_SHIFT (8U)

#define	USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

#define	USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)

#define	USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)

#define	USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

#define	USDHC_PROT_CTRL_CREQ_MASK (0x20000U)

#define	USDHC_PROT_CTRL_CREQ_SHIFT (17U)

#define	USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

#define	USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)

#define	USDHC_PROT_CTRL_RWCTL_SHIFT (18U)

#define	USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

#define	USDHC_PROT_CTRL_IABG_MASK (0x80000U)

#define	USDHC_PROT_CTRL_IABG_SHIFT (19U)

#define	USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

#define	USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)

#define	USDHC_PROT_CTRL_WECINT_SHIFT (24U)

#define	USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

#define	USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)

#define	USDHC_PROT_CTRL_WECINS_SHIFT (25U)

#define	USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

#define	USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)

#define	USDHC_PROT_CTRL_WECRM_SHIFT (26U)

#define	USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

SYS_CTRL - System Control
#define	USDHC_SYS_CTRL_DVS_MASK (0xF0U)

#define	USDHC_SYS_CTRL_DVS_SHIFT (4U)

#define	USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

#define	USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)

#define	USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)

#define	USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

#define	USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)

#define	USDHC_SYS_CTRL_DTOCV_SHIFT (16U)

#define	USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

#define	USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)

#define	USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)

#define	USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

#define	USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)

#define	USDHC_SYS_CTRL_RSTA_SHIFT (24U)

#define	USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

#define	USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)

#define	USDHC_SYS_CTRL_RSTC_SHIFT (25U)

#define	USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

#define	USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)

#define	USDHC_SYS_CTRL_RSTD_SHIFT (26U)

#define	USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

#define	USDHC_SYS_CTRL_INITA_MASK (0x8000000U)

#define	USDHC_SYS_CTRL_INITA_SHIFT (27U)

#define	USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

#define	USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)

#define	USDHC_SYS_CTRL_RSTT_SHIFT (28U)

#define	USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

INT_STATUS - Interrupt Status
#define	USDHC_INT_STATUS_CC_MASK (0x1U)

#define	USDHC_INT_STATUS_CC_SHIFT (0U)

#define	USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

#define	USDHC_INT_STATUS_TC_MASK (0x2U)

#define	USDHC_INT_STATUS_TC_SHIFT (1U)

#define	USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

#define	USDHC_INT_STATUS_BGE_MASK (0x4U)

#define	USDHC_INT_STATUS_BGE_SHIFT (2U)

#define	USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

#define	USDHC_INT_STATUS_DINT_MASK (0x8U)

#define	USDHC_INT_STATUS_DINT_SHIFT (3U)

#define	USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

#define	USDHC_INT_STATUS_BWR_MASK (0x10U)

#define	USDHC_INT_STATUS_BWR_SHIFT (4U)

#define	USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

#define	USDHC_INT_STATUS_BRR_MASK (0x20U)

#define	USDHC_INT_STATUS_BRR_SHIFT (5U)

#define	USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

#define	USDHC_INT_STATUS_CINS_MASK (0x40U)

#define	USDHC_INT_STATUS_CINS_SHIFT (6U)

#define	USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

#define	USDHC_INT_STATUS_CRM_MASK (0x80U)

#define	USDHC_INT_STATUS_CRM_SHIFT (7U)

#define	USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

#define	USDHC_INT_STATUS_CINT_MASK (0x100U)

#define	USDHC_INT_STATUS_CINT_SHIFT (8U)

#define	USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

#define	USDHC_INT_STATUS_RTE_MASK (0x1000U)

#define	USDHC_INT_STATUS_RTE_SHIFT (12U)

#define	USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

#define	USDHC_INT_STATUS_TP_MASK (0x4000U)

#define	USDHC_INT_STATUS_TP_SHIFT (14U)

#define	USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

#define	USDHC_INT_STATUS_CTOE_MASK (0x10000U)

#define	USDHC_INT_STATUS_CTOE_SHIFT (16U)

#define	USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

#define	USDHC_INT_STATUS_CCE_MASK (0x20000U)

#define	USDHC_INT_STATUS_CCE_SHIFT (17U)

#define	USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

#define	USDHC_INT_STATUS_CEBE_MASK (0x40000U)

#define	USDHC_INT_STATUS_CEBE_SHIFT (18U)

#define	USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

#define	USDHC_INT_STATUS_CIE_MASK (0x80000U)

#define	USDHC_INT_STATUS_CIE_SHIFT (19U)

#define	USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

#define	USDHC_INT_STATUS_DTOE_MASK (0x100000U)

#define	USDHC_INT_STATUS_DTOE_SHIFT (20U)

#define	USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

#define	USDHC_INT_STATUS_DCE_MASK (0x200000U)

#define	USDHC_INT_STATUS_DCE_SHIFT (21U)

#define	USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

#define	USDHC_INT_STATUS_DEBE_MASK (0x400000U)

#define	USDHC_INT_STATUS_DEBE_SHIFT (22U)

#define	USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

#define	USDHC_INT_STATUS_AC12E_MASK (0x1000000U)

#define	USDHC_INT_STATUS_AC12E_SHIFT (24U)

#define	USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

#define	USDHC_INT_STATUS_TNE_MASK (0x4000000U)

#define	USDHC_INT_STATUS_TNE_SHIFT (26U)

#define	USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

#define	USDHC_INT_STATUS_DMAE_MASK (0x10000000U)

#define	USDHC_INT_STATUS_DMAE_SHIFT (28U)

#define	USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

INT_STATUS_EN - Interrupt Status Enable
#define	USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)

#define	USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)

#define	USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

#define	USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)

#define	USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)

#define	USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

#define	USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)

#define	USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)

#define	USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

#define	USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)

#define	USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)

#define	USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)

#define	USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)

#define	USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

#define	USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)

#define	USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)

#define	USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)

#define	USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)

#define	USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

#define	USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)

#define	USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)

#define	USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)

#define	USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)

#define	USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)

#define	USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)

#define	USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

#define	USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)

#define	USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)

#define	USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

#define	USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)

#define	USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)

#define	USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)

#define	USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)

#define	USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

#define	USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)

#define	USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)

#define	USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)

#define	USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)

#define	USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

#define	USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)

#define	USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)

#define	USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)

#define	USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)

#define	USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

#define	USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)

#define	USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)

#define	USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)

#define	USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)

#define	USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

#define	USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)

#define	USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)

#define	USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

#define	USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)

#define	USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)

#define	USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

INT_SIGNAL_EN - Interrupt Signal Enable
#define	USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)

#define	USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)

#define	USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)

#define	USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)

#define	USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)

#define	USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)

#define	USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

HOST_CTRL_CAP - Host Controller Capabilities
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

#define	USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)

#define	USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)

#define	USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

#define	USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)

#define	USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)

#define	USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)

#define	USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)

#define	USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

#define	USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)

#define	USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)

#define	USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)

#define	USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)

#define	USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

#define	USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)

#define	USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)

#define	USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

#define	USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)

#define	USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)

#define	USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

#define	USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)

#define	USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)

#define	USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

WTMK_LVL - Watermark Level
#define	USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)

#define	USDHC_WTMK_LVL_RD_WML_SHIFT (0U)

#define	USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

#define	USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)

#define	USDHC_WTMK_LVL_WR_WML_SHIFT (16U)

#define	USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

MIX_CTRL - Mixer Control
#define	USDHC_MIX_CTRL_DMAEN_MASK (0x1U)

#define	USDHC_MIX_CTRL_DMAEN_SHIFT (0U)

#define	USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

#define	USDHC_MIX_CTRL_BCEN_MASK (0x2U)

#define	USDHC_MIX_CTRL_BCEN_SHIFT (1U)

#define	USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

#define	USDHC_MIX_CTRL_AC12EN_MASK (0x4U)

#define	USDHC_MIX_CTRL_AC12EN_SHIFT (2U)

#define	USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

#define	USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)

#define	USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)

#define	USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

#define	USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)

#define	USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)

#define	USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

#define	USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)

#define	USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)

#define	USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

#define	USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)

#define	USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)

#define	USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

#define	USDHC_MIX_CTRL_AC23EN_MASK (0x80U)

#define	USDHC_MIX_CTRL_AC23EN_SHIFT (7U)

#define	USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

#define	USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)

#define	USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)

#define	USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

#define	USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)

#define	USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)

#define	USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

#define	USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)

#define	USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)

#define	USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

FORCE_EVENT - Force Event
#define	USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)

#define	USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)

#define	USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)

#define	USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)

#define	USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)

#define	USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)

#define	USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)

#define	USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)

#define	USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)

#define	USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)

#define	USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)

#define	USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)

#define	USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)

#define	USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)

#define	USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)

#define	USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)

#define	USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)

#define	USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)

#define	USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)

#define	USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)

#define	USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)

#define	USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)

#define	USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

ADMA_ERR_STATUS - ADMA Error Status
#define	USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMA_SYS_ADDR - ADMA System Address
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

DLL_CTRL - DLL (Delay Line) Control
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_STATUS - DLL Status
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

STROBE_DLL_CTRL - Strobe DLL control
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)

STROBE_DLL_STATUS - Strobe DLL status
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)

VEND_SPEC - Vendor Specific Register
#define	USDHC_VEND_SPEC_VSELECT_MASK (0x2U)

#define	USDHC_VEND_SPEC_VSELECT_SHIFT (1U)

#define	USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

MMC_BOOT - MMC Boot
#define	USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)

#define	USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)

#define	USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)

#define	USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)

#define	USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)

#define	USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)

#define	USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

#define	USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)

#define	USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)

#define	USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

VEND_SPEC2 - Vendor Specific 2 Register
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

TUNING_CTRL - Tuning Control
#define	USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

#define	USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)

#define	USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)

#define	USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

DS_ADDR - DMA System Address
#define	USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)

#define	USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)

#define	USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

BLK_ATT - Block Attributes
#define	USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)

#define	USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)

#define	USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

#define	USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)

#define	USDHC_BLK_ATT_BLKCNT_SHIFT (16U)

#define	USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

CMD_ARG - Command Argument
#define	USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_ARG_CMDARG_SHIFT (0U)

#define	USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMD_XFR_TYP - Command Transfer Type
#define	USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)

#define	USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)

#define	USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)

#define	USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)

#define	USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

#define	USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)

#define	USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)

#define	USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

#define	USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)

#define	USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)

#define	USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

#define	USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)

#define	USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)

#define	USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

#define	USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)

#define	USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)

#define	USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMD_RSP0 - Command Response0
#define	USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)

#define	USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMD_RSP1 - Command Response1
#define	USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)

#define	USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMD_RSP2 - Command Response2
#define	USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)

#define	USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMD_RSP3 - Command Response3
#define	USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)

#define	USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)

#define	USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

DATA_BUFF_ACC_PORT - Data Buffer Access Port
#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)

#define	USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

PRES_STATE - Present State
#define	USDHC_PRES_STATE_CIHB_MASK (0x1U)

#define	USDHC_PRES_STATE_CIHB_SHIFT (0U)

#define	USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

#define	USDHC_PRES_STATE_CDIHB_MASK (0x2U)

#define	USDHC_PRES_STATE_CDIHB_SHIFT (1U)

#define	USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

#define	USDHC_PRES_STATE_DLA_MASK (0x4U)

#define	USDHC_PRES_STATE_DLA_SHIFT (2U)

#define	USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

#define	USDHC_PRES_STATE_SDSTB_MASK (0x8U)

#define	USDHC_PRES_STATE_SDSTB_SHIFT (3U)

#define	USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

#define	USDHC_PRES_STATE_IPGOFF_MASK (0x10U)

#define	USDHC_PRES_STATE_IPGOFF_SHIFT (4U)

#define	USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

#define	USDHC_PRES_STATE_HCKOFF_MASK (0x20U)

#define	USDHC_PRES_STATE_HCKOFF_SHIFT (5U)

#define	USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

#define	USDHC_PRES_STATE_PEROFF_MASK (0x40U)

#define	USDHC_PRES_STATE_PEROFF_SHIFT (6U)

#define	USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

#define	USDHC_PRES_STATE_SDOFF_MASK (0x80U)

#define	USDHC_PRES_STATE_SDOFF_SHIFT (7U)

#define	USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

#define	USDHC_PRES_STATE_WTA_MASK (0x100U)

#define	USDHC_PRES_STATE_WTA_SHIFT (8U)

#define	USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

#define	USDHC_PRES_STATE_RTA_MASK (0x200U)

#define	USDHC_PRES_STATE_RTA_SHIFT (9U)

#define	USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

#define	USDHC_PRES_STATE_BWEN_MASK (0x400U)

#define	USDHC_PRES_STATE_BWEN_SHIFT (10U)

#define	USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

#define	USDHC_PRES_STATE_BREN_MASK (0x800U)

#define	USDHC_PRES_STATE_BREN_SHIFT (11U)

#define	USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

#define	USDHC_PRES_STATE_RTR_MASK (0x1000U)

#define	USDHC_PRES_STATE_RTR_SHIFT (12U)

#define	USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

#define	USDHC_PRES_STATE_TSCD_MASK (0x8000U)

#define	USDHC_PRES_STATE_TSCD_SHIFT (15U)

#define	USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

#define	USDHC_PRES_STATE_CINST_MASK (0x10000U)

#define	USDHC_PRES_STATE_CINST_SHIFT (16U)

#define	USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

#define	USDHC_PRES_STATE_CDPL_MASK (0x40000U)

#define	USDHC_PRES_STATE_CDPL_SHIFT (18U)

#define	USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

#define	USDHC_PRES_STATE_WPSPL_MASK (0x80000U)

#define	USDHC_PRES_STATE_WPSPL_SHIFT (19U)

#define	USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

#define	USDHC_PRES_STATE_CLSL_MASK (0x800000U)

#define	USDHC_PRES_STATE_CLSL_SHIFT (23U)

#define	USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

#define	USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)

#define	USDHC_PRES_STATE_DLSL_SHIFT (24U)

#define	USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

PROT_CTRL - Protocol Control
#define	USDHC_PROT_CTRL_DTW_MASK (0x6U)

#define	USDHC_PROT_CTRL_DTW_SHIFT (1U)

#define	USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

#define	USDHC_PROT_CTRL_D3CD_MASK (0x8U)

#define	USDHC_PROT_CTRL_D3CD_SHIFT (3U)

#define	USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

#define	USDHC_PROT_CTRL_EMODE_MASK (0x30U)

#define	USDHC_PROT_CTRL_EMODE_SHIFT (4U)

#define	USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

#define	USDHC_PROT_CTRL_CDTL_MASK (0x40U)

#define	USDHC_PROT_CTRL_CDTL_SHIFT (6U)

#define	USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

#define	USDHC_PROT_CTRL_CDSS_MASK (0x80U)

#define	USDHC_PROT_CTRL_CDSS_SHIFT (7U)

#define	USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

#define	USDHC_PROT_CTRL_DMASEL_MASK (0x300U)

#define	USDHC_PROT_CTRL_DMASEL_SHIFT (8U)

#define	USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

#define	USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)

#define	USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)

#define	USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

#define	USDHC_PROT_CTRL_CREQ_MASK (0x20000U)

#define	USDHC_PROT_CTRL_CREQ_SHIFT (17U)

#define	USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

#define	USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)

#define	USDHC_PROT_CTRL_RWCTL_SHIFT (18U)

#define	USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

#define	USDHC_PROT_CTRL_IABG_MASK (0x80000U)

#define	USDHC_PROT_CTRL_IABG_SHIFT (19U)

#define	USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)

#define	USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

#define	USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)

#define	USDHC_PROT_CTRL_WECINT_SHIFT (24U)

#define	USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

#define	USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)

#define	USDHC_PROT_CTRL_WECINS_SHIFT (25U)

#define	USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

#define	USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)

#define	USDHC_PROT_CTRL_WECRM_SHIFT (26U)

#define	USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)

#define	USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

SYS_CTRL - System Control
#define	USDHC_SYS_CTRL_DVS_MASK (0xF0U)

#define	USDHC_SYS_CTRL_DVS_SHIFT (4U)

#define	USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

#define	USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)

#define	USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)

#define	USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

#define	USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)

#define	USDHC_SYS_CTRL_DTOCV_SHIFT (16U)

#define	USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

#define	USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)

#define	USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)

#define	USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

#define	USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)

#define	USDHC_SYS_CTRL_RSTA_SHIFT (24U)

#define	USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

#define	USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)

#define	USDHC_SYS_CTRL_RSTC_SHIFT (25U)

#define	USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

#define	USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)

#define	USDHC_SYS_CTRL_RSTD_SHIFT (26U)

#define	USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

#define	USDHC_SYS_CTRL_INITA_MASK (0x8000000U)

#define	USDHC_SYS_CTRL_INITA_SHIFT (27U)

#define	USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

#define	USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)

#define	USDHC_SYS_CTRL_RSTT_SHIFT (28U)

#define	USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

INT_STATUS - Interrupt Status
#define	USDHC_INT_STATUS_CC_MASK (0x1U)

#define	USDHC_INT_STATUS_CC_SHIFT (0U)

#define	USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

#define	USDHC_INT_STATUS_TC_MASK (0x2U)

#define	USDHC_INT_STATUS_TC_SHIFT (1U)

#define	USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

#define	USDHC_INT_STATUS_BGE_MASK (0x4U)

#define	USDHC_INT_STATUS_BGE_SHIFT (2U)

#define	USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

#define	USDHC_INT_STATUS_DINT_MASK (0x8U)

#define	USDHC_INT_STATUS_DINT_SHIFT (3U)

#define	USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

#define	USDHC_INT_STATUS_BWR_MASK (0x10U)

#define	USDHC_INT_STATUS_BWR_SHIFT (4U)

#define	USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

#define	USDHC_INT_STATUS_BRR_MASK (0x20U)

#define	USDHC_INT_STATUS_BRR_SHIFT (5U)

#define	USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

#define	USDHC_INT_STATUS_CINS_MASK (0x40U)

#define	USDHC_INT_STATUS_CINS_SHIFT (6U)

#define	USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

#define	USDHC_INT_STATUS_CRM_MASK (0x80U)

#define	USDHC_INT_STATUS_CRM_SHIFT (7U)

#define	USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

#define	USDHC_INT_STATUS_CINT_MASK (0x100U)

#define	USDHC_INT_STATUS_CINT_SHIFT (8U)

#define	USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

#define	USDHC_INT_STATUS_RTE_MASK (0x1000U)

#define	USDHC_INT_STATUS_RTE_SHIFT (12U)

#define	USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

#define	USDHC_INT_STATUS_TP_MASK (0x4000U)

#define	USDHC_INT_STATUS_TP_SHIFT (14U)

#define	USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

#define	USDHC_INT_STATUS_CTOE_MASK (0x10000U)

#define	USDHC_INT_STATUS_CTOE_SHIFT (16U)

#define	USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

#define	USDHC_INT_STATUS_CCE_MASK (0x20000U)

#define	USDHC_INT_STATUS_CCE_SHIFT (17U)

#define	USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

#define	USDHC_INT_STATUS_CEBE_MASK (0x40000U)

#define	USDHC_INT_STATUS_CEBE_SHIFT (18U)

#define	USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

#define	USDHC_INT_STATUS_CIE_MASK (0x80000U)

#define	USDHC_INT_STATUS_CIE_SHIFT (19U)

#define	USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

#define	USDHC_INT_STATUS_DTOE_MASK (0x100000U)

#define	USDHC_INT_STATUS_DTOE_SHIFT (20U)

#define	USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

#define	USDHC_INT_STATUS_DCE_MASK (0x200000U)

#define	USDHC_INT_STATUS_DCE_SHIFT (21U)

#define	USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

#define	USDHC_INT_STATUS_DEBE_MASK (0x400000U)

#define	USDHC_INT_STATUS_DEBE_SHIFT (22U)

#define	USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

#define	USDHC_INT_STATUS_AC12E_MASK (0x1000000U)

#define	USDHC_INT_STATUS_AC12E_SHIFT (24U)

#define	USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

#define	USDHC_INT_STATUS_TNE_MASK (0x4000000U)

#define	USDHC_INT_STATUS_TNE_SHIFT (26U)

#define	USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

#define	USDHC_INT_STATUS_DMAE_MASK (0x10000000U)

#define	USDHC_INT_STATUS_DMAE_SHIFT (28U)

#define	USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

INT_STATUS_EN - Interrupt Status Enable
#define	USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)

#define	USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)

#define	USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

#define	USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)

#define	USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)

#define	USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

#define	USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)

#define	USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)

#define	USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

#define	USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)

#define	USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)

#define	USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)

#define	USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)

#define	USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

#define	USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)

#define	USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)

#define	USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)

#define	USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)

#define	USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

#define	USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)

#define	USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)

#define	USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

#define	USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)

#define	USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)

#define	USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

#define	USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)

#define	USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)

#define	USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

#define	USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)

#define	USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)

#define	USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

#define	USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)

#define	USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)

#define	USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)

#define	USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)

#define	USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

#define	USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)

#define	USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)

#define	USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)

#define	USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)

#define	USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

#define	USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)

#define	USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)

#define	USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

#define	USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)

#define	USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)

#define	USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

#define	USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)

#define	USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)

#define	USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

#define	USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)

#define	USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)

#define	USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

#define	USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)

#define	USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)

#define	USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

#define	USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)

#define	USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)

#define	USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

INT_SIGNAL_EN - Interrupt Signal Enable
#define	USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)

#define	USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)

#define	USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)

#define	USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)

#define	USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)

#define	USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)

#define	USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)

#define	USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)

#define	USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)

#define	USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)

#define	USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)

#define	USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)

#define	USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)

#define	USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)

#define	USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)

#define	USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)

#define	USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)

#define	USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)

#define	USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)

#define	USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)

#define	USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)

#define	USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)

#define	USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)

#define	USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)

#define	USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status
#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)

#define	USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)

#define	USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)

#define	USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

HOST_CTRL_CAP - Host Controller Capabilities
#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)

#define	USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)

#define	USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)

#define	USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)

#define	USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

#define	USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)

#define	USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)

#define	USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

#define	USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)

#define	USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)

#define	USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)

#define	USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)

#define	USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

#define	USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)

#define	USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)

#define	USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

#define	USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)

#define	USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)

#define	USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

#define	USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)

#define	USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)

#define	USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

#define	USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)

#define	USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)

#define	USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

#define	USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)

#define	USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)

#define	USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

WTMK_LVL - Watermark Level
#define	USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)

#define	USDHC_WTMK_LVL_RD_WML_SHIFT (0U)

#define	USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

#define	USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)

#define	USDHC_WTMK_LVL_WR_WML_SHIFT (16U)

#define	USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

MIX_CTRL - Mixer Control
#define	USDHC_MIX_CTRL_DMAEN_MASK (0x1U)

#define	USDHC_MIX_CTRL_DMAEN_SHIFT (0U)

#define	USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

#define	USDHC_MIX_CTRL_BCEN_MASK (0x2U)

#define	USDHC_MIX_CTRL_BCEN_SHIFT (1U)

#define	USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

#define	USDHC_MIX_CTRL_AC12EN_MASK (0x4U)

#define	USDHC_MIX_CTRL_AC12EN_SHIFT (2U)

#define	USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

#define	USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)

#define	USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)

#define	USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

#define	USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)

#define	USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)

#define	USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

#define	USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)

#define	USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)

#define	USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

#define	USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)

#define	USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)

#define	USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

#define	USDHC_MIX_CTRL_AC23EN_MASK (0x80U)

#define	USDHC_MIX_CTRL_AC23EN_SHIFT (7U)

#define	USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

#define	USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)

#define	USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)

#define	USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)

#define	USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)

#define	USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

#define	USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)

#define	USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)

#define	USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

#define	USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)

#define	USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)

#define	USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

FORCE_EVENT - Force Event
#define	USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)

#define	USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)

#define	USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)

#define	USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)

#define	USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)

#define	USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)

#define	USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)

#define	USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)

#define	USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)

#define	USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)

#define	USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)

#define	USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)

#define	USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)

#define	USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)

#define	USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)

#define	USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)

#define	USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)

#define	USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)

#define	USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)

#define	USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)

#define	USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

#define	USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)

#define	USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)

#define	USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

#define	USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)

#define	USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)

#define	USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

#define	USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)

#define	USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)

#define	USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

#define	USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)

#define	USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)

#define	USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

ADMA_ERR_STATUS - ADMA Error Status
#define	USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)

#define	USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)

#define	USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)

#define	USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMA_SYS_ADDR - ADMA System Address
#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)

#define	USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

DLL_CTRL - DLL (Delay Line) Control
#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)

#define	USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)

#define	USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

#define	USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

#define	USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

#define	USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_STATUS - DLL Status
#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)

#define	USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)

#define	USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status
#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)

#define	USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

STROBE_DLL_CTRL - Strobe DLL control
#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)

#define	USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)

STROBE_DLL_STATUS - Strobe DLL status
#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)

#define	USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)

VEND_SPEC - Vendor Specific Register
#define	USDHC_VEND_SPEC_VSELECT_MASK (0x2U)

#define	USDHC_VEND_SPEC_VSELECT_SHIFT (1U)

#define	USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)

#define	USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)

#define	USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)

#define	USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)

#define	USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)

#define	USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

MMC_BOOT - MMC Boot
#define	USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)

#define	USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)

#define	USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)

#define	USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)

#define	USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

#define	USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)

#define	USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)

#define	USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

#define	USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)

#define	USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)

#define	USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)

#define	USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)

#define	USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)

#define	USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

VEND_SPEC2 - Vendor Specific 2 Register
#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)

#define	USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)

#define	USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)

#define	USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)

#define	USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)

#define	USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)

#define	USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)

#define	USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

TUNING_CTRL - Tuning Control
#define	USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)

#define	USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)

#define	USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)

#define	USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

#define	USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)

#define	USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)

#define	USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)

#define	USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)

#define	USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

Detailed Description

Macro Definition Documentation

◆ USDHC_ADMA_ERR_STATUS_ADMADCE [1/3]

#define USDHC_ADMA_ERR_STATUS_ADMADCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMADCE - ADMA descriptor error 0b1..Error 0b0..No error

◆ USDHC_ADMA_ERR_STATUS_ADMADCE [2/3]

#define USDHC_ADMA_ERR_STATUS_ADMADCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMADCE - ADMA descriptor error 0b1..Error 0b0..No error

◆ USDHC_ADMA_ERR_STATUS_ADMADCE [3/3]

#define USDHC_ADMA_ERR_STATUS_ADMADCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)

ADMADCE - ADMA descriptor error 0b1..Error 0b0..No error

◆ USDHC_ADMA_ERR_STATUS_ADMAES [1/3]

#define USDHC_ADMA_ERR_STATUS_ADMAES ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

ADMAES - ADMA error state (when ADMA error is occurred)

◆ USDHC_ADMA_ERR_STATUS_ADMAES [2/3]

#define USDHC_ADMA_ERR_STATUS_ADMAES ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

ADMAES - ADMA error state (when ADMA error is occurred)

◆ USDHC_ADMA_ERR_STATUS_ADMAES [3/3]

#define USDHC_ADMA_ERR_STATUS_ADMAES ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)

ADMAES - ADMA error state (when ADMA error is occurred)

◆ USDHC_ADMA_ERR_STATUS_ADMALME [1/3]

#define USDHC_ADMA_ERR_STATUS_ADMALME ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

ADMALME - ADMA length mismatch error 0b1..Error 0b0..No error

◆ USDHC_ADMA_ERR_STATUS_ADMALME [2/3]

#define USDHC_ADMA_ERR_STATUS_ADMALME ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

ADMALME - ADMA length mismatch error 0b1..Error 0b0..No error

◆ USDHC_ADMA_ERR_STATUS_ADMALME [3/3]

#define USDHC_ADMA_ERR_STATUS_ADMALME ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)

ADMALME - ADMA length mismatch error 0b1..Error 0b0..No error

◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR [1/3]

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

ADS_ADDR - ADMA system address

◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR [2/3]

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

ADS_ADDR - ADMA system address

◆ USDHC_ADMA_SYS_ADDR_ADS_ADDR [3/3]

#define USDHC_ADMA_SYS_ADDR_ADS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)

ADS_ADDR - ADMA system address

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

AC12CE - Auto CMD12 / 23 CRC error 0b1..CRC error met in Auto CMD12/23 response 0b0..No CRC error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

AC12CE - Auto CMD12 / 23 CRC error 0b1..CRC error met in Auto CMD12/23 response 0b0..No CRC error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12CE [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)

AC12CE - Auto CMD12 / 23 CRC error 0b1..CRC error met in Auto CMD12/23 response 0b0..No CRC error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

AC12EBE - Auto CMD12 / 23 end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

AC12EBE - Auto CMD12 / 23 end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12EBE [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)

AC12EBE - Auto CMD12 / 23 end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

AC12IE - Auto CMD12 / 23 index error 0b1..Error, the CMD index in response is not CMD12/23 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

AC12IE - Auto CMD12 / 23 index error 0b1..Error, the CMD index in response is not CMD12/23 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12IE [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)

AC12IE - Auto CMD12 / 23 index error 0b1..Error, the CMD index in response is not CMD12/23 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

AC12NE - Auto CMD12 not executed 0b1..Not executed 0b0..Executed

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

AC12NE - Auto CMD12 not executed 0b1..Not executed 0b0..Executed

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12NE [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)

AC12NE - Auto CMD12 not executed 0b1..Not executed 0b0..Executed

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

AC12TOE - Auto CMD12 / 23 timeout error 0b1..Time out 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

AC12TOE - Auto CMD12 / 23 timeout error 0b1..Time out 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_AC12TOE [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)

AC12TOE - Auto CMD12 / 23 timeout error 0b1..Time out 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

CNIBAC12E - Command not issued by Auto CMD12 error 0b1..Not issued 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

CNIBAC12E - Command not issued by Auto CMD12 error 0b1..Not issued 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)

CNIBAC12E - Command not issued by Auto CMD12 error 0b1..Not issued 0b0..No error

◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

EXECUTE_TUNING - Execute tuning

◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

EXECUTE_TUNING - Execute tuning 0b1..Start tuning procedure 0b0..Tuning procedure is aborted

◆ USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)

EXECUTE_TUNING - Execute tuning 0b1..Start tuning procedure 0b0..Tuning procedure is aborted

◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL [1/3]

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Sample clock select 0b1..Tuned clock is used to sample data 0b0..Fixed clock is used to sample data

◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL [2/3]

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Sample clock select 0b1..Tuned clock is used to sample data 0b0..Fixed clock is used to sample data

◆ USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL [3/3]

#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Sample clock select 0b1..Tuned clock is used to sample data 0b0..Fixed clock is used to sample data

◆ USDHC_BLK_ATT_BLKCNT [1/3]

#define USDHC_BLK_ATT_BLKCNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

BLKCNT - Blocks count for current transfer 0b1111111111111111..65535 blocks 0b0000000000000010..2 blocks 0b0000000000000001..1 block 0b0000000000000000..Stop count

◆ USDHC_BLK_ATT_BLKCNT [2/3]

#define USDHC_BLK_ATT_BLKCNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

BLKCNT - Blocks count for current transfer 0b1111111111111111..65535 blocks 0b0000000000000010..2 blocks 0b0000000000000001..1 block 0b0000000000000000..Stop count

◆ USDHC_BLK_ATT_BLKCNT [3/3]

#define USDHC_BLK_ATT_BLKCNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)

BLKCNT - Blocks count for current transfer 0b1111111111111111..65535 blocks 0b0000000000000010..2 blocks 0b0000000000000001..1 block 0b0000000000000000..Stop count

◆ USDHC_BLK_ATT_BLKSIZE [1/3]

#define USDHC_BLK_ATT_BLKSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

BLKSIZE - Transfer block size 0b1000000000000..4096 bytes 0b0100000000000..2048 bytes 0b0001000000000..512 bytes 0b0000111111111..511 bytes 0b0000000000100..4 bytes 0b0000000000011..3 bytes 0b0000000000010..2 bytes 0b0000000000001..1 byte 0b0000000000000..No data transfer

◆ USDHC_BLK_ATT_BLKSIZE [2/3]

#define USDHC_BLK_ATT_BLKSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

BLKSIZE - Transfer block size 0b1000000000000..4096 bytes 0b0100000000000..2048 bytes 0b0001000000000..512 bytes 0b0000111111111..511 bytes 0b0000000000100..4 bytes 0b0000000000011..3 bytes 0b0000000000010..2 bytes 0b0000000000001..1 byte 0b0000000000000..No data transfer

◆ USDHC_BLK_ATT_BLKSIZE [3/3]

#define USDHC_BLK_ATT_BLKSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)

BLKSIZE - Transfer block size 0b1000000000000..4096 bytes 0b0100000000000..2048 bytes 0b0001000000000..512 bytes 0b0000111111111..511 bytes 0b0000000000100..4 bytes 0b0000000000011..3 bytes 0b0000000000010..2 bytes 0b0000000000001..1 byte 0b0000000000000..No data transfer

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)

DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)

DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE

◆ USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)

DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE

◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

NXT_ERR - NXT error

◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

NXT_ERR - NXT error

◆ USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)

NXT_ERR - NXT error

◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

PRE_ERR - PRE error

◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

PRE_ERR - PRE error

◆ USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)

PRE_ERR - PRE error

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)

TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)

TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE [1/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

TAP_SEL_PRE - TAP_SEL_PRE

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE [2/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

TAP_SEL_PRE - TAP_SEL_PRE

◆ USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE [3/3]

#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)

TAP_SEL_PRE - TAP_SEL_PRE

◆ USDHC_CMD_ARG_CMDARG [1/3]

#define USDHC_CMD_ARG_CMDARG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMDARG - Command argument

◆ USDHC_CMD_ARG_CMDARG [2/3]

#define USDHC_CMD_ARG_CMDARG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMDARG - Command argument

◆ USDHC_CMD_ARG_CMDARG [3/3]

#define USDHC_CMD_ARG_CMDARG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)

CMDARG - Command argument

◆ USDHC_CMD_RSP0_CMDRSP0 [1/3]

#define USDHC_CMD_RSP0_CMDRSP0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMDRSP0 - Command response 0

◆ USDHC_CMD_RSP0_CMDRSP0 [2/3]

#define USDHC_CMD_RSP0_CMDRSP0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMDRSP0 - Command response 0

◆ USDHC_CMD_RSP0_CMDRSP0 [3/3]

#define USDHC_CMD_RSP0_CMDRSP0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)

CMDRSP0 - Command response 0

◆ USDHC_CMD_RSP1_CMDRSP1 [1/3]

#define USDHC_CMD_RSP1_CMDRSP1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMDRSP1 - Command response 1

◆ USDHC_CMD_RSP1_CMDRSP1 [2/3]

#define USDHC_CMD_RSP1_CMDRSP1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMDRSP1 - Command response 1

◆ USDHC_CMD_RSP1_CMDRSP1 [3/3]

#define USDHC_CMD_RSP1_CMDRSP1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)

CMDRSP1 - Command response 1

◆ USDHC_CMD_RSP2_CMDRSP2 [1/3]

#define USDHC_CMD_RSP2_CMDRSP2 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMDRSP2 - Command response 2

◆ USDHC_CMD_RSP2_CMDRSP2 [2/3]

#define USDHC_CMD_RSP2_CMDRSP2 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMDRSP2 - Command response 2

◆ USDHC_CMD_RSP2_CMDRSP2 [3/3]

#define USDHC_CMD_RSP2_CMDRSP2 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)

CMDRSP2 - Command response 2

◆ USDHC_CMD_RSP3_CMDRSP3 [1/3]

#define USDHC_CMD_RSP3_CMDRSP3 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

CMDRSP3 - Command response 3

◆ USDHC_CMD_RSP3_CMDRSP3 [2/3]

#define USDHC_CMD_RSP3_CMDRSP3 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

CMDRSP3 - Command response 3

◆ USDHC_CMD_RSP3_CMDRSP3 [3/3]

#define USDHC_CMD_RSP3_CMDRSP3 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)

CMDRSP3 - Command response 3

◆ USDHC_CMD_XFR_TYP_CCCEN [1/3]

#define USDHC_CMD_XFR_TYP_CCCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

CCCEN - Command CRC check enable 0b1..Enables command CRC check 0b0..Disables command CRC check

◆ USDHC_CMD_XFR_TYP_CCCEN [2/3]

#define USDHC_CMD_XFR_TYP_CCCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

CCCEN - Command CRC check enable 0b1..Enables command CRC check 0b0..Disables command CRC check

◆ USDHC_CMD_XFR_TYP_CCCEN [3/3]

#define USDHC_CMD_XFR_TYP_CCCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)

CCCEN - Command CRC check enable 0b1..Enables command CRC check 0b0..Disables command CRC check

◆ USDHC_CMD_XFR_TYP_CICEN [1/3]

#define USDHC_CMD_XFR_TYP_CICEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

CICEN - Command index check enable 0b1..Enables command index check 0b0..Disable command index check

◆ USDHC_CMD_XFR_TYP_CICEN [2/3]

#define USDHC_CMD_XFR_TYP_CICEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

CICEN - Command index check enable 0b1..Enables command index check 0b0..Disable command index check

◆ USDHC_CMD_XFR_TYP_CICEN [3/3]

#define USDHC_CMD_XFR_TYP_CICEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)

CICEN - Command index check enable 0b1..Enables command index check 0b0..Disable command index check

◆ USDHC_CMD_XFR_TYP_CMDINX [1/3]

#define USDHC_CMD_XFR_TYP_CMDINX ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMDINX - Command index

◆ USDHC_CMD_XFR_TYP_CMDINX [2/3]

#define USDHC_CMD_XFR_TYP_CMDINX ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMDINX - Command index

◆ USDHC_CMD_XFR_TYP_CMDINX [3/3]

#define USDHC_CMD_XFR_TYP_CMDINX ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)

CMDINX - Command index

◆ USDHC_CMD_XFR_TYP_CMDTYP [1/3]

#define USDHC_CMD_XFR_TYP_CMDTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

CMDTYP - Command type 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR 0b10..Resume CMD52 for writing function select in CCCR 0b01..Suspend CMD52 for writing bus suspend in CCCR 0b00..Normal other commands

◆ USDHC_CMD_XFR_TYP_CMDTYP [2/3]

#define USDHC_CMD_XFR_TYP_CMDTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

CMDTYP - Command type 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR 0b10..Resume CMD52 for writing function select in CCCR 0b01..Suspend CMD52 for writing bus suspend in CCCR 0b00..Normal other commands

◆ USDHC_CMD_XFR_TYP_CMDTYP [3/3]

#define USDHC_CMD_XFR_TYP_CMDTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)

CMDTYP - Command type 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR 0b10..Resume CMD52 for writing function select in CCCR 0b01..Suspend CMD52 for writing bus suspend in CCCR 0b00..Normal other commands

◆ USDHC_CMD_XFR_TYP_DPSEL [1/3]

#define USDHC_CMD_XFR_TYP_DPSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

DPSEL - Data present select 0b1..Data present 0b0..No data present

◆ USDHC_CMD_XFR_TYP_DPSEL [2/3]

#define USDHC_CMD_XFR_TYP_DPSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

DPSEL - Data present select 0b1..Data present 0b0..No data present

◆ USDHC_CMD_XFR_TYP_DPSEL [3/3]

#define USDHC_CMD_XFR_TYP_DPSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)

DPSEL - Data present select 0b1..Data present 0b0..No data present

◆ USDHC_CMD_XFR_TYP_RSPTYP [1/3]

#define USDHC_CMD_XFR_TYP_RSPTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

RSPTYP - Response type select 0b00..No response 0b01..Response length 136 0b10..Response length 48 0b11..Response length 48, check busy after response

◆ USDHC_CMD_XFR_TYP_RSPTYP [2/3]

#define USDHC_CMD_XFR_TYP_RSPTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

RSPTYP - Response type select 0b00..No response 0b01..Response length 136 0b10..Response length 48 0b11..Response length 48, check busy after response

◆ USDHC_CMD_XFR_TYP_RSPTYP [3/3]

#define USDHC_CMD_XFR_TYP_RSPTYP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)

RSPTYP - Response type select 0b00..No response 0b01..Response length 136 0b10..Response length 48 0b11..Response length 48, check busy after response

◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT [1/3]

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

DATCONT - Data content

◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT [2/3]

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

DATCONT - Data content

◆ USDHC_DATA_BUFF_ACC_PORT_DATCONT [3/3]

#define USDHC_DATA_BUFF_ACC_PORT_DATCONT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)

DATCONT - Data content

◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

DLL_CTRL_ENABLE - DLL and delay chain

◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

DLL_CTRL_ENABLE - DLL and delay chain

◆ USDHC_DLL_CTRL_DLL_CTRL_ENABLE [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)

DLL_CTRL_ENABLE - DLL and delay chain

◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

DLL_CTRL_GATE_UPDATE - DLL gate update

◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

DLL_CTRL_GATE_UPDATE - DLL gate update

◆ USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)

DLL_CTRL_GATE_UPDATE - DLL gate update

◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval

◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval

◆ USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)

DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval

◆ USDHC_DLL_CTRL_DLL_CTRL_RESET [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

DLL_CTRL_RESET - DLL reset

◆ USDHC_DLL_CTRL_DLL_CTRL_RESET [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

DLL_CTRL_RESET - DLL reset

◆ USDHC_DLL_CTRL_DLL_CTRL_RESET [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)

DLL_CTRL_RESET - DLL reset

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)

DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)

DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)

DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

DLL_CTRL_SLV_OVERRIDE - DLL slave override

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

DLL_CTRL_SLV_OVERRIDE - DLL slave override

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)

DLL_CTRL_SLV_OVERRIDE - DLL slave override

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT [1/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT [2/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval

◆ USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT [3/3]

#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)

DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval

◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK [1/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

DLL_STS_REF_LOCK - Reference DLL lock status

◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK [2/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

DLL_STS_REF_LOCK - Reference DLL lock status

◆ USDHC_DLL_STATUS_DLL_STS_REF_LOCK [3/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)

DLL_STS_REF_LOCK - Reference DLL lock status

◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL [1/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

DLL_STS_REF_SEL - Reference delay line select taps

◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL [2/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

DLL_STS_REF_SEL - Reference delay line select taps

◆ USDHC_DLL_STATUS_DLL_STS_REF_SEL [3/3]

#define USDHC_DLL_STATUS_DLL_STS_REF_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)

DLL_STS_REF_SEL - Reference delay line select taps

◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK [1/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

DLL_STS_SLV_LOCK - Slave delay-line lock status

◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK [2/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

DLL_STS_SLV_LOCK - Slave delay-line lock status

◆ USDHC_DLL_STATUS_DLL_STS_SLV_LOCK [3/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)

DLL_STS_SLV_LOCK - Slave delay-line lock status

◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL [1/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

DLL_STS_SLV_SEL - Slave delay line select status

◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL [2/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

DLL_STS_SLV_SEL - Slave delay line select status

◆ USDHC_DLL_STATUS_DLL_STS_SLV_SEL [3/3]

#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)

DLL_STS_SLV_SEL - Slave delay line select status

◆ USDHC_DS_ADDR_DS_ADDR [1/3]

#define USDHC_DS_ADDR_DS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

DS_ADDR - System address

◆ USDHC_DS_ADDR_DS_ADDR [2/3]

#define USDHC_DS_ADDR_DS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

DS_ADDR - System address

◆ USDHC_DS_ADDR_DS_ADDR [3/3]

#define USDHC_DS_ADDR_DS_ADDR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)

DS_ADDR - System address

◆ USDHC_FORCE_EVENT_FEVTAC12CE [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

FEVTAC12CE - Force event auto command 12 CRC error

◆ USDHC_FORCE_EVENT_FEVTAC12CE [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

FEVTAC12CE - Force event auto command 12 CRC error

◆ USDHC_FORCE_EVENT_FEVTAC12CE [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12CE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)

FEVTAC12CE - Force event auto command 12 CRC error

◆ USDHC_FORCE_EVENT_FEVTAC12E [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

FEVTAC12E - Force event Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTAC12E [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

FEVTAC12E - Force event Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTAC12E [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)

FEVTAC12E - Force event Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTAC12EBE [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

FEVTAC12EBE - Force event Auto Command 12 end bit error

◆ USDHC_FORCE_EVENT_FEVTAC12EBE [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

FEVTAC12EBE - Force event Auto Command 12 end bit error

◆ USDHC_FORCE_EVENT_FEVTAC12EBE [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12EBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)

FEVTAC12EBE - Force event Auto Command 12 end bit error

◆ USDHC_FORCE_EVENT_FEVTAC12IE [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

FEVTAC12IE - Force event Auto Command 12 index error

◆ USDHC_FORCE_EVENT_FEVTAC12IE [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

FEVTAC12IE - Force event Auto Command 12 index error

◆ USDHC_FORCE_EVENT_FEVTAC12IE [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12IE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)

FEVTAC12IE - Force event Auto Command 12 index error

◆ USDHC_FORCE_EVENT_FEVTAC12NE [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

FEVTAC12NE - Force event auto command 12 not executed

◆ USDHC_FORCE_EVENT_FEVTAC12NE [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

FEVTAC12NE - Force event auto command 12 not executed

◆ USDHC_FORCE_EVENT_FEVTAC12NE [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12NE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)

FEVTAC12NE - Force event auto command 12 not executed

◆ USDHC_FORCE_EVENT_FEVTAC12TOE [1/3]

#define USDHC_FORCE_EVENT_FEVTAC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

FEVTAC12TOE - Force event auto command 12 time out error

◆ USDHC_FORCE_EVENT_FEVTAC12TOE [2/3]

#define USDHC_FORCE_EVENT_FEVTAC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

FEVTAC12TOE - Force event auto command 12 time out error

◆ USDHC_FORCE_EVENT_FEVTAC12TOE [3/3]

#define USDHC_FORCE_EVENT_FEVTAC12TOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)

FEVTAC12TOE - Force event auto command 12 time out error

◆ USDHC_FORCE_EVENT_FEVTCCE [1/3]

#define USDHC_FORCE_EVENT_FEVTCCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

FEVTCCE - Force event command CRC error

◆ USDHC_FORCE_EVENT_FEVTCCE [2/3]

#define USDHC_FORCE_EVENT_FEVTCCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

FEVTCCE - Force event command CRC error

◆ USDHC_FORCE_EVENT_FEVTCCE [3/3]

#define USDHC_FORCE_EVENT_FEVTCCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)

FEVTCCE - Force event command CRC error

◆ USDHC_FORCE_EVENT_FEVTCEBE [1/3]

#define USDHC_FORCE_EVENT_FEVTCEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

FEVTCEBE - Force event command end bit error

◆ USDHC_FORCE_EVENT_FEVTCEBE [2/3]

#define USDHC_FORCE_EVENT_FEVTCEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

FEVTCEBE - Force event command end bit error

◆ USDHC_FORCE_EVENT_FEVTCEBE [3/3]

#define USDHC_FORCE_EVENT_FEVTCEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)

FEVTCEBE - Force event command end bit error

◆ USDHC_FORCE_EVENT_FEVTCIE [1/3]

#define USDHC_FORCE_EVENT_FEVTCIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

FEVTCIE - Force event command index error

◆ USDHC_FORCE_EVENT_FEVTCIE [2/3]

#define USDHC_FORCE_EVENT_FEVTCIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

FEVTCIE - Force event command index error

◆ USDHC_FORCE_EVENT_FEVTCIE [3/3]

#define USDHC_FORCE_EVENT_FEVTCIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)

FEVTCIE - Force event command index error

◆ USDHC_FORCE_EVENT_FEVTCINT [1/3]

#define USDHC_FORCE_EVENT_FEVTCINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

FEVTCINT - Force event card interrupt

◆ USDHC_FORCE_EVENT_FEVTCINT [2/3]

#define USDHC_FORCE_EVENT_FEVTCINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

FEVTCINT - Force event card interrupt

◆ USDHC_FORCE_EVENT_FEVTCINT [3/3]

#define USDHC_FORCE_EVENT_FEVTCINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)

FEVTCINT - Force event card interrupt

◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E [1/3]

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E [2/3]

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTCNIBAC12E [3/3]

#define USDHC_FORCE_EVENT_FEVTCNIBAC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)

FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error

◆ USDHC_FORCE_EVENT_FEVTCTOE [1/3]

#define USDHC_FORCE_EVENT_FEVTCTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

FEVTCTOE - Force event command time out error

◆ USDHC_FORCE_EVENT_FEVTCTOE [2/3]

#define USDHC_FORCE_EVENT_FEVTCTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

FEVTCTOE - Force event command time out error

◆ USDHC_FORCE_EVENT_FEVTCTOE [3/3]

#define USDHC_FORCE_EVENT_FEVTCTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)

FEVTCTOE - Force event command time out error

◆ USDHC_FORCE_EVENT_FEVTDCE [1/3]

#define USDHC_FORCE_EVENT_FEVTDCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

FEVTDCE - Force event data CRC error

◆ USDHC_FORCE_EVENT_FEVTDCE [2/3]

#define USDHC_FORCE_EVENT_FEVTDCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

FEVTDCE - Force event data CRC error

◆ USDHC_FORCE_EVENT_FEVTDCE [3/3]

#define USDHC_FORCE_EVENT_FEVTDCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)

FEVTDCE - Force event data CRC error

◆ USDHC_FORCE_EVENT_FEVTDEBE [1/3]

#define USDHC_FORCE_EVENT_FEVTDEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

FEVTDEBE - Force event data end bit error

◆ USDHC_FORCE_EVENT_FEVTDEBE [2/3]

#define USDHC_FORCE_EVENT_FEVTDEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

FEVTDEBE - Force event data end bit error

◆ USDHC_FORCE_EVENT_FEVTDEBE [3/3]

#define USDHC_FORCE_EVENT_FEVTDEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)

FEVTDEBE - Force event data end bit error

◆ USDHC_FORCE_EVENT_FEVTDMAE [1/3]

#define USDHC_FORCE_EVENT_FEVTDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

FEVTDMAE - Force event DMA error

◆ USDHC_FORCE_EVENT_FEVTDMAE [2/3]

#define USDHC_FORCE_EVENT_FEVTDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

FEVTDMAE - Force event DMA error

◆ USDHC_FORCE_EVENT_FEVTDMAE [3/3]

#define USDHC_FORCE_EVENT_FEVTDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)

FEVTDMAE - Force event DMA error

◆ USDHC_FORCE_EVENT_FEVTDTOE [1/3]

#define USDHC_FORCE_EVENT_FEVTDTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

FEVTDTOE - Force event data time out error

◆ USDHC_FORCE_EVENT_FEVTDTOE [2/3]

#define USDHC_FORCE_EVENT_FEVTDTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

FEVTDTOE - Force event data time out error

◆ USDHC_FORCE_EVENT_FEVTDTOE [3/3]

#define USDHC_FORCE_EVENT_FEVTDTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)

FEVTDTOE - Force event data time out error

◆ USDHC_FORCE_EVENT_FEVTTNE [1/3]

#define USDHC_FORCE_EVENT_FEVTTNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

FEVTTNE - Force tuning error

◆ USDHC_FORCE_EVENT_FEVTTNE [2/3]

#define USDHC_FORCE_EVENT_FEVTTNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

FEVTTNE - Force tuning error

◆ USDHC_FORCE_EVENT_FEVTTNE [3/3]

#define USDHC_FORCE_EVENT_FEVTTNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)

FEVTTNE - Force tuning error

◆ USDHC_HOST_CTRL_CAP_ADMAS [1/3]

#define USDHC_HOST_CTRL_CAP_ADMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

ADMAS - ADMA support 0b1..Advanced DMA supported 0b0..Advanced DMA not supported

◆ USDHC_HOST_CTRL_CAP_ADMAS [2/3]

#define USDHC_HOST_CTRL_CAP_ADMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

ADMAS - ADMA support 0b1..Advanced DMA supported 0b0..Advanced DMA not supported

◆ USDHC_HOST_CTRL_CAP_ADMAS [3/3]

#define USDHC_HOST_CTRL_CAP_ADMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)

ADMAS - ADMA support 0b1..Advanced DMA supported 0b0..Advanced DMA not supported

◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT [1/3]

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

DDR50_SUPPORT - DDR50 support

◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT [2/3]

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

DDR50_SUPPORT - DDR50 support

◆ USDHC_HOST_CTRL_CAP_DDR50_SUPPORT [3/3]

#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)

DDR50_SUPPORT - DDR50 support

◆ USDHC_HOST_CTRL_CAP_DMAS [1/3]

#define USDHC_HOST_CTRL_CAP_DMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

DMAS - DMA support 0b1..DMA supported 0b0..DMA not supported

◆ USDHC_HOST_CTRL_CAP_DMAS [2/3]

#define USDHC_HOST_CTRL_CAP_DMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

DMAS - DMA support 0b1..DMA supported 0b0..DMA not supported

◆ USDHC_HOST_CTRL_CAP_DMAS [3/3]

#define USDHC_HOST_CTRL_CAP_DMAS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)

DMAS - DMA support 0b1..DMA supported 0b0..DMA not supported

◆ USDHC_HOST_CTRL_CAP_HSS [1/3]

#define USDHC_HOST_CTRL_CAP_HSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

HSS - High speed support 0b1..High speed supported 0b0..High speed not supported

◆ USDHC_HOST_CTRL_CAP_HSS [2/3]

#define USDHC_HOST_CTRL_CAP_HSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

HSS - High speed support 0b1..High speed supported 0b0..High speed not supported

◆ USDHC_HOST_CTRL_CAP_HSS [3/3]

#define USDHC_HOST_CTRL_CAP_HSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)

HSS - High speed support 0b1..High speed supported 0b0..High speed not supported

◆ USDHC_HOST_CTRL_CAP_MBL [1/3]

#define USDHC_HOST_CTRL_CAP_MBL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

MBL - Max block length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ USDHC_HOST_CTRL_CAP_MBL [2/3]

#define USDHC_HOST_CTRL_CAP_MBL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

MBL - Max block length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ USDHC_HOST_CTRL_CAP_MBL [3/3]

#define USDHC_HOST_CTRL_CAP_MBL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)

MBL - Max block length 0b000..512 bytes 0b001..1024 bytes 0b010..2048 bytes 0b011..4096 bytes

◆ USDHC_HOST_CTRL_CAP_RETUNING_MODE

#define USDHC_HOST_CTRL_CAP_RETUNING_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)

RETUNING_MODE - Retuning Mode 0b00..Mode 1 0b01..Mode 2 0b10..Mode 3 0b11..Reserved

◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT [1/3]

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

SDR104_SUPPORT - SDR104 support

◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT [2/3]

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

SDR104_SUPPORT - SDR104 support

◆ USDHC_HOST_CTRL_CAP_SDR104_SUPPORT [3/3]

#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)

SDR104_SUPPORT - SDR104 support

◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT [1/3]

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

SDR50_SUPPORT - SDR50 support

◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT [2/3]

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

SDR50_SUPPORT - SDR50 support

◆ USDHC_HOST_CTRL_CAP_SDR50_SUPPORT [3/3]

#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)

SDR50_SUPPORT - SDR50 support

◆ USDHC_HOST_CTRL_CAP_SRS [1/3]

#define USDHC_HOST_CTRL_CAP_SRS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

SRS - Suspend / resume support 0b1..Supported 0b0..Not supported

◆ USDHC_HOST_CTRL_CAP_SRS [2/3]

#define USDHC_HOST_CTRL_CAP_SRS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

SRS - Suspend / resume support 0b1..Supported 0b0..Not supported

◆ USDHC_HOST_CTRL_CAP_SRS [3/3]

#define USDHC_HOST_CTRL_CAP_SRS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)

SRS - Suspend / resume support 0b1..Supported 0b0..Not supported

◆ USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING

#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)

TIME_COUNT_RETUNING - Time counter for retuning

◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 [1/3]

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

USE_TUNING_SDR50 - Use Tuning for SDR50 0b1..SDR50 requires tuning. 0b0..SDR does not require tuning.

◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 [2/3]

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

USE_TUNING_SDR50 - Use Tuning for SDR50 0b1..SDR50 supports tuning 0b0..SDR50 does not support tuning

◆ USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 [3/3]

#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)

USE_TUNING_SDR50 - Use Tuning for SDR50 0b1..SDR50 supports tuning 0b0..SDR50 does not support tuning

◆ USDHC_HOST_CTRL_CAP_VS18 [1/3]

#define USDHC_HOST_CTRL_CAP_VS18 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

VS18 - Voltage support 1.8 V 0b1..1.8 V supported 0b0..1.8 V not supported

◆ USDHC_HOST_CTRL_CAP_VS18 [2/3]

#define USDHC_HOST_CTRL_CAP_VS18 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

VS18 - Voltage support 1.8 V 0b1..1.8 V supported 0b0..1.8 V not supported

◆ USDHC_HOST_CTRL_CAP_VS18 [3/3]

#define USDHC_HOST_CTRL_CAP_VS18 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)

VS18 - Voltage support 1.8 V 0b1..1.8 V supported 0b0..1.8 V not supported

◆ USDHC_HOST_CTRL_CAP_VS30 [1/3]

#define USDHC_HOST_CTRL_CAP_VS30 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

VS30 - Voltage support 3.0 V 0b1..3.0 V supported 0b0..3.0 V not supported

◆ USDHC_HOST_CTRL_CAP_VS30 [2/3]

#define USDHC_HOST_CTRL_CAP_VS30 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

VS30 - Voltage support 3.0 V 0b1..3.0 V supported 0b0..3.0 V not supported

◆ USDHC_HOST_CTRL_CAP_VS30 [3/3]

#define USDHC_HOST_CTRL_CAP_VS30 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)

VS30 - Voltage support 3.0 V 0b1..3.0 V supported 0b0..3.0 V not supported

◆ USDHC_HOST_CTRL_CAP_VS33 [1/3]

#define USDHC_HOST_CTRL_CAP_VS33 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

VS33 - Voltage support 3.3 V 0b1..3.3 V supported 0b0..3.3 V not supported

◆ USDHC_HOST_CTRL_CAP_VS33 [2/3]

#define USDHC_HOST_CTRL_CAP_VS33 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

VS33 - Voltage support 3.3 V 0b1..3.3 V supported 0b0..3.3 V not supported

◆ USDHC_HOST_CTRL_CAP_VS33 [3/3]

#define USDHC_HOST_CTRL_CAP_VS33 ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)

VS33 - Voltage support 3.3 V 0b1..3.3 V supported 0b0..3.3 V not supported

◆ USDHC_INT_SIGNAL_EN_AC12EIEN [1/3]

#define USDHC_INT_SIGNAL_EN_AC12EIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_AC12EIEN [2/3]

#define USDHC_INT_SIGNAL_EN_AC12EIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_AC12EIEN [3/3]

#define USDHC_INT_SIGNAL_EN_AC12EIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)

AC12EIEN - Auto CMD12 error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BGEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_BGEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

BGEIEN - Block gap event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BGEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_BGEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

BGEIEN - Block gap event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BGEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_BGEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)

BGEIEN - Block gap event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BRRIEN [1/3]

#define USDHC_INT_SIGNAL_EN_BRRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

BRRIEN - Buffer read ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BRRIEN [2/3]

#define USDHC_INT_SIGNAL_EN_BRRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

BRRIEN - Buffer read ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BRRIEN [3/3]

#define USDHC_INT_SIGNAL_EN_BRRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)

BRRIEN - Buffer read ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BWRIEN [1/3]

#define USDHC_INT_SIGNAL_EN_BWRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

BWRIEN - Buffer write ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BWRIEN [2/3]

#define USDHC_INT_SIGNAL_EN_BWRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

BWRIEN - Buffer write ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_BWRIEN [3/3]

#define USDHC_INT_SIGNAL_EN_BWRIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)

BWRIEN - Buffer write ready interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

CCEIEN - Command CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

CCEIEN - Command CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)

CCEIEN - Command CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

CCIEN - Command complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

CCIEN - Command complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CCIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)

CCIEN - Command complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CEBEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

CEBEIEN - Command end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CEBEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

CEBEIEN - Command end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CEBEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)

CEBEIEN - Command end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CIEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CIEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

CIEIEN - Command index error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CIEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CIEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

CIEIEN - Command index error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CIEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CIEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)

CIEIEN - Command index error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINSIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CINSIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

CINSIEN - Card insertion interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINSIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CINSIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

CINSIEN - Card insertion interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINSIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CINSIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)

CINSIEN - Card insertion interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINTIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

CINTIEN - Card interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINTIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

CINTIEN - Card interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CINTIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)

CINTIEN - Card interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CRMIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CRMIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

CRMIEN - Card removal interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CRMIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CRMIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

CRMIEN - Card removal interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CRMIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CRMIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)

CRMIEN - Card removal interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CTOEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_CTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

CTOEIEN - Command timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CTOEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_CTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

CTOEIEN - Command timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_CTOEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_CTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)

CTOEIEN - Command timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DCEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_DCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

DCEIEN - Data CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DCEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_DCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

DCEIEN - Data CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DCEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_DCEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)

DCEIEN - Data CRC error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DEBEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_DEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

DEBEIEN - Data end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DEBEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_DEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

DEBEIEN - Data end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DEBEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_DEBEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)

DEBEIEN - Data end bit error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DINTIEN [1/3]

#define USDHC_INT_SIGNAL_EN_DINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

DINTIEN - DMA interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DINTIEN [2/3]

#define USDHC_INT_SIGNAL_EN_DINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

DINTIEN - DMA interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DINTIEN [3/3]

#define USDHC_INT_SIGNAL_EN_DINTIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)

DINTIEN - DMA interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DMAEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_DMAEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

DMAEIEN - DMA error interrupt enable 0b1..Enable 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DMAEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_DMAEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

DMAEIEN - DMA error interrupt enable 0b1..Enable 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DMAEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_DMAEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)

DMAEIEN - DMA error interrupt enable 0b1..Enable 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DTOEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_DTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

DTOEIEN - Data timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DTOEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_DTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

DTOEIEN - Data timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_DTOEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_DTOEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)

DTOEIEN - Data timeout error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_RTEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_RTEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

RTEIEN - Re-tuning event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_RTEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_RTEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

RTEIEN - Re-tuning event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_RTEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_RTEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)

RTEIEN - Re-tuning event interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TCIEN [1/3]

#define USDHC_INT_SIGNAL_EN_TCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

TCIEN - Transfer complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TCIEN [2/3]

#define USDHC_INT_SIGNAL_EN_TCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

TCIEN - Transfer complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TCIEN [3/3]

#define USDHC_INT_SIGNAL_EN_TCIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)

TCIEN - Transfer complete interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TNEIEN [1/3]

#define USDHC_INT_SIGNAL_EN_TNEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

TNEIEN - Tuning error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TNEIEN [2/3]

#define USDHC_INT_SIGNAL_EN_TNEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

TNEIEN - Tuning error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TNEIEN [3/3]

#define USDHC_INT_SIGNAL_EN_TNEIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)

TNEIEN - Tuning error interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TPIEN [1/3]

#define USDHC_INT_SIGNAL_EN_TPIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

TPIEN - Tuning Pass interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TPIEN [2/3]

#define USDHC_INT_SIGNAL_EN_TPIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

TPIEN - Tuning Pass interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_SIGNAL_EN_TPIEN [3/3]

#define USDHC_INT_SIGNAL_EN_TPIEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)

TPIEN - Tuning Pass interrupt enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_AC12E [1/3]

#define USDHC_INT_STATUS_AC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

AC12E - Auto CMD12 error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_AC12E [2/3]

#define USDHC_INT_STATUS_AC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

AC12E - Auto CMD12 error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_AC12E [3/3]

#define USDHC_INT_STATUS_AC12E ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)

AC12E - Auto CMD12 error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_BGE [1/3]

#define USDHC_INT_STATUS_BGE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

BGE - Block gap event 0b1..Transaction stopped at block gap 0b0..No block gap event

◆ USDHC_INT_STATUS_BGE [2/3]

#define USDHC_INT_STATUS_BGE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

BGE - Block gap event 0b1..Transaction stopped at block gap 0b0..No block gap event

◆ USDHC_INT_STATUS_BGE [3/3]

#define USDHC_INT_STATUS_BGE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)

BGE - Block gap event 0b1..Transaction stopped at block gap 0b0..No block gap event

◆ USDHC_INT_STATUS_BRR [1/3]

#define USDHC_INT_STATUS_BRR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

BRR - Buffer read ready 0b1..Ready to read buffer 0b0..Not ready to read buffer

◆ USDHC_INT_STATUS_BRR [2/3]

#define USDHC_INT_STATUS_BRR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

BRR - Buffer read ready 0b1..Ready to read buffer 0b0..Not ready to read buffer

◆ USDHC_INT_STATUS_BRR [3/3]

#define USDHC_INT_STATUS_BRR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)

BRR - Buffer read ready 0b1..Ready to read buffer 0b0..Not ready to read buffer

◆ USDHC_INT_STATUS_BWR [1/3]

#define USDHC_INT_STATUS_BWR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

BWR - Buffer write ready 0b1..Ready to write buffer 0b0..Not ready to write buffer

◆ USDHC_INT_STATUS_BWR [2/3]

#define USDHC_INT_STATUS_BWR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

BWR - Buffer write ready 0b1..Ready to write buffer 0b0..Not ready to write buffer

◆ USDHC_INT_STATUS_BWR [3/3]

#define USDHC_INT_STATUS_BWR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)

BWR - Buffer write ready 0b1..Ready to write buffer 0b0..Not ready to write buffer

◆ USDHC_INT_STATUS_CC [1/3]

#define USDHC_INT_STATUS_CC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

CC - Command complete 0b1..Command complete 0b0..Command not complete

◆ USDHC_INT_STATUS_CC [2/3]

#define USDHC_INT_STATUS_CC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

CC - Command complete 0b1..Command complete 0b0..Command not complete

◆ USDHC_INT_STATUS_CC [3/3]

#define USDHC_INT_STATUS_CC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)

CC - Command complete 0b1..Command complete 0b0..Command not complete

◆ USDHC_INT_STATUS_CCE [1/3]

#define USDHC_INT_STATUS_CCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

CCE - Command CRC error 0b1..CRC error generated 0b0..No error

◆ USDHC_INT_STATUS_CCE [2/3]

#define USDHC_INT_STATUS_CCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

CCE - Command CRC error 0b1..CRC error generated 0b0..No error

◆ USDHC_INT_STATUS_CCE [3/3]

#define USDHC_INT_STATUS_CCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)

CCE - Command CRC error 0b1..CRC error generated 0b0..No error

◆ USDHC_INT_STATUS_CEBE [1/3]

#define USDHC_INT_STATUS_CEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

CEBE - Command end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_INT_STATUS_CEBE [2/3]

#define USDHC_INT_STATUS_CEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

CEBE - Command end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_INT_STATUS_CEBE [3/3]

#define USDHC_INT_STATUS_CEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)

CEBE - Command end bit error 0b1..End bit error generated 0b0..No error

◆ USDHC_INT_STATUS_CIE [1/3]

#define USDHC_INT_STATUS_CIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

CIE - Command index error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_CIE [2/3]

#define USDHC_INT_STATUS_CIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

CIE - Command index error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_CIE [3/3]

#define USDHC_INT_STATUS_CIE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)

CIE - Command index error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_CINS [1/3]

#define USDHC_INT_STATUS_CINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

CINS - Card insertion 0b1..Card inserted 0b0..Card state unstable or removed

◆ USDHC_INT_STATUS_CINS [2/3]

#define USDHC_INT_STATUS_CINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

CINS - Card insertion 0b1..Card inserted 0b0..Card state unstable or removed

◆ USDHC_INT_STATUS_CINS [3/3]

#define USDHC_INT_STATUS_CINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)

CINS - Card insertion 0b1..Card inserted 0b0..Card state unstable or removed

◆ USDHC_INT_STATUS_CINT [1/3]

#define USDHC_INT_STATUS_CINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

CINT - Card interrupt 0b1..Generate card interrupt 0b0..No card interrupt

◆ USDHC_INT_STATUS_CINT [2/3]

#define USDHC_INT_STATUS_CINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

CINT - Card interrupt 0b1..Generate card interrupt 0b0..No card interrupt

◆ USDHC_INT_STATUS_CINT [3/3]

#define USDHC_INT_STATUS_CINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)

CINT - Card interrupt 0b1..Generate card interrupt 0b0..No card interrupt

◆ USDHC_INT_STATUS_CRM [1/3]

#define USDHC_INT_STATUS_CRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

CRM - Card removal 0b1..Card removed 0b0..Card state unstable or inserted

◆ USDHC_INT_STATUS_CRM [2/3]

#define USDHC_INT_STATUS_CRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

CRM - Card removal 0b1..Card removed 0b0..Card state unstable or inserted

◆ USDHC_INT_STATUS_CRM [3/3]

#define USDHC_INT_STATUS_CRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)

CRM - Card removal 0b1..Card removed 0b0..Card state unstable or inserted

◆ USDHC_INT_STATUS_CTOE [1/3]

#define USDHC_INT_STATUS_CTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

CTOE - Command timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_CTOE [2/3]

#define USDHC_INT_STATUS_CTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

CTOE - Command timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_CTOE [3/3]

#define USDHC_INT_STATUS_CTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)

CTOE - Command timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_DCE [1/3]

#define USDHC_INT_STATUS_DCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

DCE - Data CRC error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DCE [2/3]

#define USDHC_INT_STATUS_DCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

DCE - Data CRC error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DCE [3/3]

#define USDHC_INT_STATUS_DCE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)

DCE - Data CRC error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DEBE [1/3]

#define USDHC_INT_STATUS_DEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

DEBE - Data end bit error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DEBE [2/3]

#define USDHC_INT_STATUS_DEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

DEBE - Data end bit error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DEBE [3/3]

#define USDHC_INT_STATUS_DEBE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)

DEBE - Data end bit error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DINT [1/3]

#define USDHC_INT_STATUS_DINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

DINT - DMA interrupt 0b1..DMA interrupt is generated. 0b0..No DMA interrupt

◆ USDHC_INT_STATUS_DINT [2/3]

#define USDHC_INT_STATUS_DINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

DINT - DMA interrupt 0b1..DMA interrupt is generated. 0b0..No DMA interrupt

◆ USDHC_INT_STATUS_DINT [3/3]

#define USDHC_INT_STATUS_DINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)

DINT - DMA interrupt 0b1..DMA interrupt is generated. 0b0..No DMA interrupt

◆ USDHC_INT_STATUS_DMAE [1/3]

#define USDHC_INT_STATUS_DMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

DMAE - DMA error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DMAE [2/3]

#define USDHC_INT_STATUS_DMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

DMAE - DMA error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DMAE [3/3]

#define USDHC_INT_STATUS_DMAE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)

DMAE - DMA error 0b1..Error 0b0..No error

◆ USDHC_INT_STATUS_DTOE [1/3]

#define USDHC_INT_STATUS_DTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

DTOE - Data timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_DTOE [2/3]

#define USDHC_INT_STATUS_DTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

DTOE - Data timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_DTOE [3/3]

#define USDHC_INT_STATUS_DTOE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)

DTOE - Data timeout error 0b1..Time out 0b0..No error

◆ USDHC_INT_STATUS_EN_AC12ESEN [1/3]

#define USDHC_INT_STATUS_EN_AC12ESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_AC12ESEN [2/3]

#define USDHC_INT_STATUS_EN_AC12ESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_AC12ESEN [3/3]

#define USDHC_INT_STATUS_EN_AC12ESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)

AC12ESEN - Auto CMD12 error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BGESEN [1/3]

#define USDHC_INT_STATUS_EN_BGESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

BGESEN - Block gap event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BGESEN [2/3]

#define USDHC_INT_STATUS_EN_BGESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

BGESEN - Block gap event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BGESEN [3/3]

#define USDHC_INT_STATUS_EN_BGESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)

BGESEN - Block gap event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BRRSEN [1/3]

#define USDHC_INT_STATUS_EN_BRRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

BRRSEN - Buffer read ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BRRSEN [2/3]

#define USDHC_INT_STATUS_EN_BRRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

BRRSEN - Buffer read ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BRRSEN [3/3]

#define USDHC_INT_STATUS_EN_BRRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)

BRRSEN - Buffer read ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BWRSEN [1/3]

#define USDHC_INT_STATUS_EN_BWRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

BWRSEN - Buffer write ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BWRSEN [2/3]

#define USDHC_INT_STATUS_EN_BWRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

BWRSEN - Buffer write ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_BWRSEN [3/3]

#define USDHC_INT_STATUS_EN_BWRSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)

BWRSEN - Buffer write ready status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCESEN [1/3]

#define USDHC_INT_STATUS_EN_CCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

CCESEN - Command CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCESEN [2/3]

#define USDHC_INT_STATUS_EN_CCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

CCESEN - Command CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCESEN [3/3]

#define USDHC_INT_STATUS_EN_CCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)

CCESEN - Command CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCSEN [1/3]

#define USDHC_INT_STATUS_EN_CCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

CCSEN - Command complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCSEN [2/3]

#define USDHC_INT_STATUS_EN_CCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

CCSEN - Command complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CCSEN [3/3]

#define USDHC_INT_STATUS_EN_CCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)

CCSEN - Command complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CEBESEN [1/3]

#define USDHC_INT_STATUS_EN_CEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

CEBESEN - Command end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CEBESEN [2/3]

#define USDHC_INT_STATUS_EN_CEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

CEBESEN - Command end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CEBESEN [3/3]

#define USDHC_INT_STATUS_EN_CEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)

CEBESEN - Command end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CIESEN [1/3]

#define USDHC_INT_STATUS_EN_CIESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

CIESEN - Command index error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CIESEN [2/3]

#define USDHC_INT_STATUS_EN_CIESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

CIESEN - Command index error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CIESEN [3/3]

#define USDHC_INT_STATUS_EN_CIESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)

CIESEN - Command index error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINSSEN [1/3]

#define USDHC_INT_STATUS_EN_CINSSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

CINSSEN - Card insertion status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINSSEN [2/3]

#define USDHC_INT_STATUS_EN_CINSSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

CINSSEN - Card insertion status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINSSEN [3/3]

#define USDHC_INT_STATUS_EN_CINSSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)

CINSSEN - Card insertion status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINTSEN [1/3]

#define USDHC_INT_STATUS_EN_CINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

CINTSEN - Card interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINTSEN [2/3]

#define USDHC_INT_STATUS_EN_CINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

CINTSEN - Card interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CINTSEN [3/3]

#define USDHC_INT_STATUS_EN_CINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)

CINTSEN - Card interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CRMSEN [1/3]

#define USDHC_INT_STATUS_EN_CRMSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

CRMSEN - Card removal status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CRMSEN [2/3]

#define USDHC_INT_STATUS_EN_CRMSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

CRMSEN - Card removal status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CRMSEN [3/3]

#define USDHC_INT_STATUS_EN_CRMSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)

CRMSEN - Card removal status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CTOESEN [1/3]

#define USDHC_INT_STATUS_EN_CTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

CTOESEN - Command timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CTOESEN [2/3]

#define USDHC_INT_STATUS_EN_CTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

CTOESEN - Command timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_CTOESEN [3/3]

#define USDHC_INT_STATUS_EN_CTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)

CTOESEN - Command timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DCESEN [1/3]

#define USDHC_INT_STATUS_EN_DCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

DCESEN - Data CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DCESEN [2/3]

#define USDHC_INT_STATUS_EN_DCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

DCESEN - Data CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DCESEN [3/3]

#define USDHC_INT_STATUS_EN_DCESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)

DCESEN - Data CRC error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DEBESEN [1/3]

#define USDHC_INT_STATUS_EN_DEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

DEBESEN - Data end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DEBESEN [2/3]

#define USDHC_INT_STATUS_EN_DEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

DEBESEN - Data end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DEBESEN [3/3]

#define USDHC_INT_STATUS_EN_DEBESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)

DEBESEN - Data end bit error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DINTSEN [1/3]

#define USDHC_INT_STATUS_EN_DINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

DINTSEN - DMA interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DINTSEN [2/3]

#define USDHC_INT_STATUS_EN_DINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

DINTSEN - DMA interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DINTSEN [3/3]

#define USDHC_INT_STATUS_EN_DINTSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)

DINTSEN - DMA interrupt status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DMAESEN [1/3]

#define USDHC_INT_STATUS_EN_DMAESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

DMAESEN - DMA error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DMAESEN [2/3]

#define USDHC_INT_STATUS_EN_DMAESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

DMAESEN - DMA error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DMAESEN [3/3]

#define USDHC_INT_STATUS_EN_DMAESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)

DMAESEN - DMA error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DTOESEN [1/3]

#define USDHC_INT_STATUS_EN_DTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

DTOESEN - Data timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DTOESEN [2/3]

#define USDHC_INT_STATUS_EN_DTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

DTOESEN - Data timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_DTOESEN [3/3]

#define USDHC_INT_STATUS_EN_DTOESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)

DTOESEN - Data timeout error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_RTESEN [1/3]

#define USDHC_INT_STATUS_EN_RTESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

RTESEN - Re-tuning event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_RTESEN [2/3]

#define USDHC_INT_STATUS_EN_RTESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

RTESEN - Re-tuning event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_RTESEN [3/3]

#define USDHC_INT_STATUS_EN_RTESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)

RTESEN - Re-tuning event status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TCSEN [1/3]

#define USDHC_INT_STATUS_EN_TCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

TCSEN - Transfer complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TCSEN [2/3]

#define USDHC_INT_STATUS_EN_TCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

TCSEN - Transfer complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TCSEN [3/3]

#define USDHC_INT_STATUS_EN_TCSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)

TCSEN - Transfer complete status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TNESEN [1/3]

#define USDHC_INT_STATUS_EN_TNESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

TNESEN - Tuning error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TNESEN [2/3]

#define USDHC_INT_STATUS_EN_TNESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

TNESEN - Tuning error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TNESEN [3/3]

#define USDHC_INT_STATUS_EN_TNESEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)

TNESEN - Tuning error status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TPSEN [1/3]

#define USDHC_INT_STATUS_EN_TPSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

TPSEN - Tuning pass status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TPSEN [2/3]

#define USDHC_INT_STATUS_EN_TPSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

TPSEN - Tuning pass status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_EN_TPSEN [3/3]

#define USDHC_INT_STATUS_EN_TPSEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)

TPSEN - Tuning pass status enable 0b1..Enabled 0b0..Masked

◆ USDHC_INT_STATUS_RTE [1/3]

#define USDHC_INT_STATUS_RTE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Re-tuning should be performed. 0b0..Re-tuning is not required.

◆ USDHC_INT_STATUS_RTE [2/3]

#define USDHC_INT_STATUS_RTE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Re-tuning should be performed. 0b0..Re-tuning is not required.

◆ USDHC_INT_STATUS_RTE [3/3]

#define USDHC_INT_STATUS_RTE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)

RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Re-tuning should be performed. 0b0..Re-tuning is not required.

◆ USDHC_INT_STATUS_TC [1/3]

#define USDHC_INT_STATUS_TC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

TC - Transfer complete 0b1..Transfer complete 0b0..Transfer does not complete

◆ USDHC_INT_STATUS_TC [2/3]

#define USDHC_INT_STATUS_TC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

TC - Transfer complete 0b1..Transfer complete 0b0..Transfer does not complete

◆ USDHC_INT_STATUS_TC [3/3]

#define USDHC_INT_STATUS_TC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)

TC - Transfer complete 0b1..Transfer complete 0b0..Transfer does not complete

◆ USDHC_INT_STATUS_TNE [1/3]

#define USDHC_INT_STATUS_TNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_INT_STATUS_TNE [2/3]

#define USDHC_INT_STATUS_TNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_INT_STATUS_TNE [3/3]

#define USDHC_INT_STATUS_TNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)

TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_INT_STATUS_TP [1/3]

#define USDHC_INT_STATUS_TP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_INT_STATUS_TP [2/3]

#define USDHC_INT_STATUS_TP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_INT_STATUS_TP [3/3]

#define USDHC_INT_STATUS_TP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)

TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)

◆ USDHC_MIX_CTRL_AC12EN [1/3]

#define USDHC_MIX_CTRL_AC12EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

AC12EN - Auto CMD12 enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_AC12EN [2/3]

#define USDHC_MIX_CTRL_AC12EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

AC12EN - Auto CMD12 enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_AC12EN [3/3]

#define USDHC_MIX_CTRL_AC12EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)

AC12EN - Auto CMD12 enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_AC23EN [1/3]

#define USDHC_MIX_CTRL_AC23EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

AC23EN - Auto CMD23 enable

◆ USDHC_MIX_CTRL_AC23EN [2/3]

#define USDHC_MIX_CTRL_AC23EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

AC23EN - Auto CMD23 enable

◆ USDHC_MIX_CTRL_AC23EN [3/3]

#define USDHC_MIX_CTRL_AC23EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)

AC23EN - Auto CMD23 enable

◆ USDHC_MIX_CTRL_AUTO_TUNE_EN [1/3]

#define USDHC_MIX_CTRL_AUTO_TUNE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) 0b1..Enable auto tuning 0b0..Disable auto tuning

◆ USDHC_MIX_CTRL_AUTO_TUNE_EN [2/3]

#define USDHC_MIX_CTRL_AUTO_TUNE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) 0b1..Enable auto tuning 0b0..Disable auto tuning

◆ USDHC_MIX_CTRL_AUTO_TUNE_EN [3/3]

#define USDHC_MIX_CTRL_AUTO_TUNE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)

AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) 0b1..Enable auto tuning 0b0..Disable auto tuning

◆ USDHC_MIX_CTRL_BCEN [1/3]

#define USDHC_MIX_CTRL_BCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

BCEN - Block count enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_BCEN [2/3]

#define USDHC_MIX_CTRL_BCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

BCEN - Block count enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_BCEN [3/3]

#define USDHC_MIX_CTRL_BCEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)

BCEN - Block count enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_DDR_EN [1/3]

#define USDHC_MIX_CTRL_DDR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

DDR_EN - Dual data rate mode selection

◆ USDHC_MIX_CTRL_DDR_EN [2/3]

#define USDHC_MIX_CTRL_DDR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

DDR_EN - Dual data rate mode selection

◆ USDHC_MIX_CTRL_DDR_EN [3/3]

#define USDHC_MIX_CTRL_DDR_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)

DDR_EN - Dual data rate mode selection

◆ USDHC_MIX_CTRL_DMAEN [1/3]

#define USDHC_MIX_CTRL_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

DMAEN - DMA enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_DMAEN [2/3]

#define USDHC_MIX_CTRL_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

DMAEN - DMA enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_DMAEN [3/3]

#define USDHC_MIX_CTRL_DMAEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)

DMAEN - DMA enable 0b1..Enable 0b0..Disable

◆ USDHC_MIX_CTRL_DTDSEL [1/3]

#define USDHC_MIX_CTRL_DTDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

DTDSEL - Data transfer direction select 0b1..Read (Card to host) 0b0..Write (Host to card)

◆ USDHC_MIX_CTRL_DTDSEL [2/3]

#define USDHC_MIX_CTRL_DTDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

DTDSEL - Data transfer direction select 0b1..Read (Card to host) 0b0..Write (Host to card)

◆ USDHC_MIX_CTRL_DTDSEL [3/3]

#define USDHC_MIX_CTRL_DTDSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)

DTDSEL - Data transfer direction select 0b1..Read (Card to host) 0b0..Write (Host to card)

◆ USDHC_MIX_CTRL_EXE_TUNE [1/3]

#define USDHC_MIX_CTRL_EXE_TUNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Execute tuning 0b0..Not tuned or tuning completed

◆ USDHC_MIX_CTRL_EXE_TUNE [2/3]

#define USDHC_MIX_CTRL_EXE_TUNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Execute tuning 0b0..Not tuned or tuning completed

◆ USDHC_MIX_CTRL_EXE_TUNE [3/3]

#define USDHC_MIX_CTRL_EXE_TUNE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)

EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Execute tuning 0b0..Not tuned or tuning completed

◆ USDHC_MIX_CTRL_FBCLK_SEL [1/3]

#define USDHC_MIX_CTRL_FBCLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Feedback clock comes from the ipp_card_clk_out 0b0..Feedback clock comes from the loopback CLK

◆ USDHC_MIX_CTRL_FBCLK_SEL [2/3]

#define USDHC_MIX_CTRL_FBCLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Feedback clock comes from the ipp_card_clk_out 0b0..Feedback clock comes from the loopback CLK

◆ USDHC_MIX_CTRL_FBCLK_SEL [3/3]

#define USDHC_MIX_CTRL_FBCLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)

FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) 0b1..Feedback clock comes from the ipp_card_clk_out 0b0..Feedback clock comes from the loopback CLK

◆ USDHC_MIX_CTRL_HS400_MODE [1/2]

#define USDHC_MIX_CTRL_HS400_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

HS400_MODE - Enable HS400 mode

◆ USDHC_MIX_CTRL_HS400_MODE [2/2]

#define USDHC_MIX_CTRL_HS400_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)

HS400_MODE - Enable HS400 mode

◆ USDHC_MIX_CTRL_MSBSEL [1/3]

#define USDHC_MIX_CTRL_MSBSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

MSBSEL - Multi / Single block select 0b1..Multiple blocks 0b0..Single block

◆ USDHC_MIX_CTRL_MSBSEL [2/3]

#define USDHC_MIX_CTRL_MSBSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

MSBSEL - Multi / Single block select 0b1..Multiple blocks 0b0..Single block

◆ USDHC_MIX_CTRL_MSBSEL [3/3]

#define USDHC_MIX_CTRL_MSBSEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)

MSBSEL - Multi / Single block select 0b1..Multiple blocks 0b0..Single block

◆ USDHC_MIX_CTRL_NIBBLE_POS [1/3]

#define USDHC_MIX_CTRL_NIBBLE_POS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

NIBBLE_POS - Nibble position indication

◆ USDHC_MIX_CTRL_NIBBLE_POS [2/3]

#define USDHC_MIX_CTRL_NIBBLE_POS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

NIBBLE_POS - Nibble position indication

◆ USDHC_MIX_CTRL_NIBBLE_POS [3/3]

#define USDHC_MIX_CTRL_NIBBLE_POS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)

NIBBLE_POS - Nibble position indication

◆ USDHC_MIX_CTRL_SMP_CLK_SEL [1/3]

#define USDHC_MIX_CTRL_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Clock selection 0b1..Tuned clock is used to sample data / cmd 0b0..Fixed clock is used to sample data / cmd

◆ USDHC_MIX_CTRL_SMP_CLK_SEL [2/3]

#define USDHC_MIX_CTRL_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Clock selection 0b1..Tuned clock is used to sample data / cmd 0b0..Fixed clock is used to sample data / cmd

◆ USDHC_MIX_CTRL_SMP_CLK_SEL [3/3]

#define USDHC_MIX_CTRL_SMP_CLK_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)

SMP_CLK_SEL - Clock selection 0b1..Tuned clock is used to sample data / cmd 0b0..Fixed clock is used to sample data / cmd

◆ USDHC_MMC_BOOT_AUTO_SABG_EN [1/3]

#define USDHC_MMC_BOOT_AUTO_SABG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

AUTO_SABG_EN - Auto stop at block gap

◆ USDHC_MMC_BOOT_AUTO_SABG_EN [2/3]

#define USDHC_MMC_BOOT_AUTO_SABG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

AUTO_SABG_EN - Auto stop at block gap

◆ USDHC_MMC_BOOT_AUTO_SABG_EN [3/3]

#define USDHC_MMC_BOOT_AUTO_SABG_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)

AUTO_SABG_EN - Auto stop at block gap

◆ USDHC_MMC_BOOT_BOOT_ACK [1/3]

#define USDHC_MMC_BOOT_BOOT_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

BOOT_ACK - BOOT ACK 0b0..No ack 0b1..Ack

◆ USDHC_MMC_BOOT_BOOT_ACK [2/3]

#define USDHC_MMC_BOOT_BOOT_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

BOOT_ACK - BOOT ACK 0b0..No ack 0b1..Ack

◆ USDHC_MMC_BOOT_BOOT_ACK [3/3]

#define USDHC_MMC_BOOT_BOOT_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)

BOOT_ACK - BOOT ACK 0b0..No ack 0b1..Ack

◆ USDHC_MMC_BOOT_BOOT_BLK_CNT [1/3]

#define USDHC_MMC_BOOT_BOOT_BLK_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

BOOT_BLK_CNT - Stop At Block Gap value of automatic mode

◆ USDHC_MMC_BOOT_BOOT_BLK_CNT [2/3]

#define USDHC_MMC_BOOT_BOOT_BLK_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

BOOT_BLK_CNT - Stop At Block Gap value of automatic mode

◆ USDHC_MMC_BOOT_BOOT_BLK_CNT [3/3]

#define USDHC_MMC_BOOT_BOOT_BLK_CNT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)

BOOT_BLK_CNT - Stop At Block Gap value of automatic mode

◆ USDHC_MMC_BOOT_BOOT_EN [1/3]

#define USDHC_MMC_BOOT_BOOT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

BOOT_EN - Boot enable 0b0..Fast boot disable 0b1..Fast boot enable

◆ USDHC_MMC_BOOT_BOOT_EN [2/3]

#define USDHC_MMC_BOOT_BOOT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

BOOT_EN - Boot enable 0b0..Fast boot disable 0b1..Fast boot enable

◆ USDHC_MMC_BOOT_BOOT_EN [3/3]

#define USDHC_MMC_BOOT_BOOT_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)

BOOT_EN - Boot enable 0b0..Fast boot disable 0b1..Fast boot enable

◆ USDHC_MMC_BOOT_BOOT_MODE [1/3]

#define USDHC_MMC_BOOT_BOOT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

BOOT_MODE - Boot mode 0b0..Normal boot 0b1..Alternative boot

◆ USDHC_MMC_BOOT_BOOT_MODE [2/3]

#define USDHC_MMC_BOOT_BOOT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

BOOT_MODE - Boot mode 0b0..Normal boot 0b1..Alternative boot

◆ USDHC_MMC_BOOT_BOOT_MODE [3/3]

#define USDHC_MMC_BOOT_BOOT_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)

BOOT_MODE - Boot mode 0b0..Normal boot 0b1..Alternative boot

◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT [1/3]

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

DISABLE_TIME_OUT - Time out 0b0..Enable time out 0b1..Disable time out

◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT [2/3]

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

DISABLE_TIME_OUT - Time out 0b0..Enable time out 0b1..Disable time out

◆ USDHC_MMC_BOOT_DISABLE_TIME_OUT [3/3]

#define USDHC_MMC_BOOT_DISABLE_TIME_OUT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)

DISABLE_TIME_OUT - Time out 0b0..Enable time out 0b1..Disable time out

◆ USDHC_MMC_BOOT_DTOCV_ACK [1/3]

#define USDHC_MMC_BOOT_DTOCV_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

DTOCV_ACK - Boot ACK time out 0b0000..SDCLK x 2^14 0b0001..SDCLK x 2^15 0b0010..SDCLK x 2^16 0b0011..SDCLK x 2^17 0b0100..SDCLK x 2^18 0b0101..SDCLK x 2^19 0b0110..SDCLK x 2^20 0b0111..SDCLK x 2^21 0b1110..SDCLK x 2^28 0b1111..SDCLK x 2^29

◆ USDHC_MMC_BOOT_DTOCV_ACK [2/3]

#define USDHC_MMC_BOOT_DTOCV_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

DTOCV_ACK - Boot ACK time out 0b0000..SDCLK x 2^14 0b0001..SDCLK x 2^15 0b0010..SDCLK x 2^16 0b0011..SDCLK x 2^17 0b0100..SDCLK x 2^18 0b0101..SDCLK x 2^19 0b0110..SDCLK x 2^20 0b0111..SDCLK x 2^21 0b1110..SDCLK x 2^28 0b1111..SDCLK x 2^29

◆ USDHC_MMC_BOOT_DTOCV_ACK [3/3]

#define USDHC_MMC_BOOT_DTOCV_ACK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)

DTOCV_ACK - Boot ACK time out 0b0000..SDCLK x 2^14 0b0001..SDCLK x 2^15 0b0010..SDCLK x 2^16 0b0011..SDCLK x 2^17 0b0100..SDCLK x 2^18 0b0101..SDCLK x 2^19 0b0110..SDCLK x 2^20 0b0111..SDCLK x 2^21 0b1110..SDCLK x 2^28 0b1111..SDCLK x 2^29

◆ USDHC_PRES_STATE_BREN [1/3]

#define USDHC_PRES_STATE_BREN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

BREN - Buffer read enable 0b1..Read enable 0b0..Read disable

◆ USDHC_PRES_STATE_BREN [2/3]

#define USDHC_PRES_STATE_BREN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

BREN - Buffer read enable 0b1..Read enable 0b0..Read disable

◆ USDHC_PRES_STATE_BREN [3/3]

#define USDHC_PRES_STATE_BREN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)

BREN - Buffer read enable 0b1..Read enable 0b0..Read disable

◆ USDHC_PRES_STATE_BWEN [1/3]

#define USDHC_PRES_STATE_BWEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

BWEN - Buffer write enable 0b1..Write enable 0b0..Write disable

◆ USDHC_PRES_STATE_BWEN [2/3]

#define USDHC_PRES_STATE_BWEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

BWEN - Buffer write enable 0b1..Write enable 0b0..Write disable

◆ USDHC_PRES_STATE_BWEN [3/3]

#define USDHC_PRES_STATE_BWEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)

BWEN - Buffer write enable 0b1..Write enable 0b0..Write disable

◆ USDHC_PRES_STATE_CDIHB [1/3]

#define USDHC_PRES_STATE_CDIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

CDIHB - Command inhibit (DATA) 0b1..Cannot issue command that uses the DATA line 0b0..Can issue command that uses the DATA line

◆ USDHC_PRES_STATE_CDIHB [2/3]

#define USDHC_PRES_STATE_CDIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

CDIHB - Command Inhibit Data (DATA) 0b1..Cannot issue command that uses the DATA line 0b0..Can issue command that uses the DATA line

◆ USDHC_PRES_STATE_CDIHB [3/3]

#define USDHC_PRES_STATE_CDIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)

CDIHB - Command Inhibit Data (DATA) 0b1..Cannot issue command that uses the DATA line 0b0..Can issue command that uses the DATA line

◆ USDHC_PRES_STATE_CDPL [1/3]

#define USDHC_PRES_STATE_CDPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

CDPL - Card detect pin level 0b1..Card present (CD_B = 0) 0b0..No card present (CD_B = 1)

◆ USDHC_PRES_STATE_CDPL [2/3]

#define USDHC_PRES_STATE_CDPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

CDPL - Card detect pin level 0b1..Card present (CD_B = 0) 0b0..No card present (CD_B = 1)

◆ USDHC_PRES_STATE_CDPL [3/3]

#define USDHC_PRES_STATE_CDPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)

CDPL - Card detect pin level 0b1..Card present (CD_B = 0) 0b0..No card present (CD_B = 1)

◆ USDHC_PRES_STATE_CIHB [1/3]

#define USDHC_PRES_STATE_CIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

CIHB - Command inhibit (CMD) 0b1..Cannot issue command 0b0..Can issue command using only CMD line

◆ USDHC_PRES_STATE_CIHB [2/3]

#define USDHC_PRES_STATE_CIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

CIHB - Command inhibit (CMD) 0b1..Cannot issue command 0b0..Can issue command using only CMD line

◆ USDHC_PRES_STATE_CIHB [3/3]

#define USDHC_PRES_STATE_CIHB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)

CIHB - Command inhibit (CMD) 0b1..Cannot issue command 0b0..Can issue command using only CMD line

◆ USDHC_PRES_STATE_CINST [1/3]

#define USDHC_PRES_STATE_CINST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

CINST - Card inserted 0b1..Card inserted 0b0..Power on reset or no card

◆ USDHC_PRES_STATE_CINST [2/3]

#define USDHC_PRES_STATE_CINST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

CINST - Card inserted 0b1..Card inserted 0b0..Power on reset or no card

◆ USDHC_PRES_STATE_CINST [3/3]

#define USDHC_PRES_STATE_CINST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)

CINST - Card inserted 0b1..Card inserted 0b0..Power on reset or no card

◆ USDHC_PRES_STATE_CLSL [1/3]

#define USDHC_PRES_STATE_CLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

CLSL - CMD line signal level

◆ USDHC_PRES_STATE_CLSL [2/3]

#define USDHC_PRES_STATE_CLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

CLSL - CMD line signal level

◆ USDHC_PRES_STATE_CLSL [3/3]

#define USDHC_PRES_STATE_CLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)

CLSL - CMD line signal level

◆ USDHC_PRES_STATE_DLA [1/3]

#define USDHC_PRES_STATE_DLA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

DLA - Data line active 0b1..DATA line active 0b0..DATA line inactive

◆ USDHC_PRES_STATE_DLA [2/3]

#define USDHC_PRES_STATE_DLA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

DLA - Data line active 0b1..DATA line active 0b0..DATA line inactive

◆ USDHC_PRES_STATE_DLA [3/3]

#define USDHC_PRES_STATE_DLA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)

DLA - Data line active 0b1..DATA line active 0b0..DATA line inactive

◆ USDHC_PRES_STATE_DLSL [1/3]

#define USDHC_PRES_STATE_DLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

DLSL - DATA[7:0] line signal level 0b00000111..Data 7 line signal level 0b00000110..Data 6 line signal level 0b00000101..Data 5 line signal level 0b00000100..Data 4 line signal level 0b00000011..Data 3 line signal level 0b00000010..Data 2 line signal level 0b00000001..Data 1 line signal level 0b00000000..Data 0 line signal level

◆ USDHC_PRES_STATE_DLSL [2/3]

#define USDHC_PRES_STATE_DLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

DLSL - DATA[7:0] line signal level 0b00000111..Data 7 line signal level 0b00000110..Data 6 line signal level 0b00000101..Data 5 line signal level 0b00000100..Data 4 line signal level 0b00000011..Data 3 line signal level 0b00000010..Data 2 line signal level 0b00000001..Data 1 line signal level 0b00000000..Data 0 line signal level

◆ USDHC_PRES_STATE_DLSL [3/3]

#define USDHC_PRES_STATE_DLSL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)

DLSL - DATA[7:0] line signal level 0b00000111..Data 7 line signal level 0b00000110..Data 6 line signal level 0b00000101..Data 5 line signal level 0b00000100..Data 4 line signal level 0b00000011..Data 3 line signal level 0b00000010..Data 2 line signal level 0b00000001..Data 1 line signal level 0b00000000..Data 0 line signal level

◆ USDHC_PRES_STATE_HCKOFF [1/3]

#define USDHC_PRES_STATE_HCKOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

HCKOFF - HCLK gated off internally 0b1..HCLK is gated off. 0b0..HCLK is active.

◆ USDHC_PRES_STATE_HCKOFF [2/3]

#define USDHC_PRES_STATE_HCKOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

HCKOFF - HCLK gated off internally 0b1..HCLK is gated off. 0b0..HCLK is active.

◆ USDHC_PRES_STATE_HCKOFF [3/3]

#define USDHC_PRES_STATE_HCKOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)

HCKOFF - HCLK gated off internally 0b1..HCLK is gated off. 0b0..HCLK is active.

◆ USDHC_PRES_STATE_IPGOFF [1/3]

#define USDHC_PRES_STATE_IPGOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

IPGOFF - Peripheral clock gated off internally 0b1..Peripheral clock is gated off. 0b0..Peripheral clock is active.

◆ USDHC_PRES_STATE_IPGOFF [2/3]

#define USDHC_PRES_STATE_IPGOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

IPGOFF - Peripheral clock gated off internally 0b1..Peripheral clock is gated off. 0b0..Peripheral clock is active.

◆ USDHC_PRES_STATE_IPGOFF [3/3]

#define USDHC_PRES_STATE_IPGOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)

IPGOFF - Peripheral clock gated off internally 0b1..Peripheral clock is gated off. 0b0..Peripheral clock is active.

◆ USDHC_PRES_STATE_PEROFF [1/3]

#define USDHC_PRES_STATE_PEROFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

PEROFF - IPG_PERCLK gated off internally 0b1..IPG_PERCLK is gated off. 0b0..IPG_PERCLK is active.

◆ USDHC_PRES_STATE_PEROFF [2/3]

#define USDHC_PRES_STATE_PEROFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

PEROFF - IPG_PERCLK gated off internally 0b1..IPG_PERCLK is gated off. 0b0..IPG_PERCLK is active.

◆ USDHC_PRES_STATE_PEROFF [3/3]

#define USDHC_PRES_STATE_PEROFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)

PEROFF - IPG_PERCLK gated off internally 0b1..IPG_PERCLK is gated off. 0b0..IPG_PERCLK is active.

◆ USDHC_PRES_STATE_RTA [1/3]

#define USDHC_PRES_STATE_RTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

RTA - Read transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PRES_STATE_RTA [2/3]

#define USDHC_PRES_STATE_RTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

RTA - Read transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PRES_STATE_RTA [3/3]

#define USDHC_PRES_STATE_RTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)

RTA - Read transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PRES_STATE_RTR [1/3]

#define USDHC_PRES_STATE_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) 0b1..Sampling clock needs re-tuning 0b0..Fixed or well tuned sampling clock

◆ USDHC_PRES_STATE_RTR [2/3]

#define USDHC_PRES_STATE_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode) 0b1..Sampling clock needs re-tuning 0b0..Fixed or well tuned sampling clock

◆ USDHC_PRES_STATE_RTR [3/3]

#define USDHC_PRES_STATE_RTR ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)

RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode) 0b1..Sampling clock needs re-tuning 0b0..Fixed or well tuned sampling clock

◆ USDHC_PRES_STATE_SDOFF [1/3]

#define USDHC_PRES_STATE_SDOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

SDOFF - SD clock gated off internally 0b1..SD clock is gated off. 0b0..SD clock is active.

◆ USDHC_PRES_STATE_SDOFF [2/3]

#define USDHC_PRES_STATE_SDOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

SDOFF - SD clock gated off internally 0b1..SD clock is gated off. 0b0..SD clock is active.

◆ USDHC_PRES_STATE_SDOFF [3/3]

#define USDHC_PRES_STATE_SDOFF ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)

SDOFF - SD clock gated off internally 0b1..SD clock is gated off. 0b0..SD clock is active.

◆ USDHC_PRES_STATE_SDSTB [1/3]

#define USDHC_PRES_STATE_SDSTB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

SDSTB - SD clock stable 0b1..Clock is stable. 0b0..Clock is changing frequency and not stable.

◆ USDHC_PRES_STATE_SDSTB [2/3]

#define USDHC_PRES_STATE_SDSTB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

SDSTB - SD clock stable 0b1..Clock is stable. 0b0..Clock is changing frequency and not stable.

◆ USDHC_PRES_STATE_SDSTB [3/3]

#define USDHC_PRES_STATE_SDSTB ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)

SDSTB - SD clock stable 0b1..Clock is stable. 0b0..Clock is changing frequency and not stable.

◆ USDHC_PRES_STATE_TSCD [1/3]

#define USDHC_PRES_STATE_TSCD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

TSCD - Tape select change done 0b1..Delay cell select change is finished. 0b0..Delay cell select change is not finished.

◆ USDHC_PRES_STATE_TSCD [2/3]

#define USDHC_PRES_STATE_TSCD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

TSCD - Tap select change done 0b1..Delay cell select change is finished. 0b0..Delay cell select change is not finished.

◆ USDHC_PRES_STATE_TSCD [3/3]

#define USDHC_PRES_STATE_TSCD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)

TSCD - Tap select change done 0b1..Delay cell select change is finished. 0b0..Delay cell select change is not finished.

◆ USDHC_PRES_STATE_WPSPL [1/3]

#define USDHC_PRES_STATE_WPSPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

WPSPL - Write protect switch pin level 0b1..Write enabled (WP = 0) 0b0..Write protected (WP = 1)

◆ USDHC_PRES_STATE_WPSPL [2/3]

#define USDHC_PRES_STATE_WPSPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

WPSPL - Write protect switch pin level 0b1..Write enabled (WP = 0) 0b0..Write protected (WP = 1)

◆ USDHC_PRES_STATE_WPSPL [3/3]

#define USDHC_PRES_STATE_WPSPL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)

WPSPL - Write protect switch pin level 0b1..Write enabled (WP = 0) 0b0..Write protected (WP = 1)

◆ USDHC_PRES_STATE_WTA [1/3]

#define USDHC_PRES_STATE_WTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

WTA - Write transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PRES_STATE_WTA [2/3]

#define USDHC_PRES_STATE_WTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

WTA - Write transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PRES_STATE_WTA [3/3]

#define USDHC_PRES_STATE_WTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)

WTA - Write transfer active 0b1..Transferring data 0b0..No valid data

◆ USDHC_PROT_CTRL_BURST_LEN_EN

#define USDHC_PROT_CTRL_BURST_LEN_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)

BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP 0bxx1..Burst length is enabled for INCR. 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16. 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP.

◆ USDHC_PROT_CTRL_CDSS [1/3]

#define USDHC_PROT_CTRL_CDSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

CDSS - Card detect signal selection 0b1..Card detection test level is selected (for test purpose). 0b0..Card detection level is selected (for normal purpose).

◆ USDHC_PROT_CTRL_CDSS [2/3]

#define USDHC_PROT_CTRL_CDSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

CDSS - Card detect signal selection 0b1..Card detection test level is selected (for test purpose). 0b0..Card detection level is selected (for normal purpose).

◆ USDHC_PROT_CTRL_CDSS [3/3]

#define USDHC_PROT_CTRL_CDSS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)

CDSS - Card detect signal selection 0b1..Card detection test level is selected (for test purpose). 0b0..Card detection level is selected (for normal purpose).

◆ USDHC_PROT_CTRL_CDTL [1/3]

#define USDHC_PROT_CTRL_CDTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

CDTL - Card detect test level 0b1..Card detect test level is 1, card inserted 0b0..Card detect test level is 0, no card inserted

◆ USDHC_PROT_CTRL_CDTL [2/3]

#define USDHC_PROT_CTRL_CDTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

CDTL - Card detect test level 0b1..Card detect test level is 1, card inserted 0b0..Card detect test level is 0, no card inserted

◆ USDHC_PROT_CTRL_CDTL [3/3]

#define USDHC_PROT_CTRL_CDTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)

CDTL - Card detect test level 0b1..Card detect test level is 1, card inserted 0b0..Card detect test level is 0, no card inserted

◆ USDHC_PROT_CTRL_CREQ [1/3]

#define USDHC_PROT_CTRL_CREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

CREQ - Continue request 0b1..Restart 0b0..No effect

◆ USDHC_PROT_CTRL_CREQ [2/3]

#define USDHC_PROT_CTRL_CREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

CREQ - Continue request 0b1..Restart 0b0..No effect

◆ USDHC_PROT_CTRL_CREQ [3/3]

#define USDHC_PROT_CTRL_CREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)

CREQ - Continue request 0b1..Restart 0b0..No effect

◆ USDHC_PROT_CTRL_D3CD [1/3]

#define USDHC_PROT_CTRL_D3CD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

D3CD - DATA3 as card detection pin 0b1..DATA3 as card detection pin 0b0..DATA3 does not monitor card insertion

◆ USDHC_PROT_CTRL_D3CD [2/3]

#define USDHC_PROT_CTRL_D3CD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

D3CD - DATA3 as card detection pin 0b1..DATA3 as card detection pin 0b0..DATA3 does not monitor card insertion

◆ USDHC_PROT_CTRL_D3CD [3/3]

#define USDHC_PROT_CTRL_D3CD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)

D3CD - DATA3 as card detection pin 0b1..DATA3 as card detection pin 0b0..DATA3 does not monitor card insertion

◆ USDHC_PROT_CTRL_DMASEL [1/3]

#define USDHC_PROT_CTRL_DMASEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

DMASEL - DMA select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ USDHC_PROT_CTRL_DMASEL [2/3]

#define USDHC_PROT_CTRL_DMASEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

DMASEL - DMA select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ USDHC_PROT_CTRL_DMASEL [3/3]

#define USDHC_PROT_CTRL_DMASEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)

DMASEL - DMA select 0b00..No DMA or simple DMA is selected. 0b01..ADMA1 is selected. 0b10..ADMA2 is selected. 0b11..Reserved

◆ USDHC_PROT_CTRL_DTW [1/3]

#define USDHC_PROT_CTRL_DTW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

DTW - Data transfer width 0b10..8-bit mode 0b01..4-bit mode 0b00..1-bit mode 0b11..Reserved

◆ USDHC_PROT_CTRL_DTW [2/3]

#define USDHC_PROT_CTRL_DTW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

DTW - Data transfer width 0b10..8-bit mode 0b01..4-bit mode 0b00..1-bit mode 0b11..Reserved

◆ USDHC_PROT_CTRL_DTW [3/3]

#define USDHC_PROT_CTRL_DTW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)

DTW - Data transfer width 0b10..8-bit mode 0b01..4-bit mode 0b00..1-bit mode 0b11..Reserved

◆ USDHC_PROT_CTRL_EMODE [1/3]

#define USDHC_PROT_CTRL_EMODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

EMODE - Endian mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ USDHC_PROT_CTRL_EMODE [2/3]

#define USDHC_PROT_CTRL_EMODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

EMODE - Endian mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ USDHC_PROT_CTRL_EMODE [3/3]

#define USDHC_PROT_CTRL_EMODE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)

EMODE - Endian mode 0b00..Big endian mode 0b01..Half word big endian mode 0b10..Little endian mode 0b11..Reserved

◆ USDHC_PROT_CTRL_IABG [1/3]

#define USDHC_PROT_CTRL_IABG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

IABG - Interrupt at block gap 0b1..Enables interrupt at block gap 0b0..Disables interrupt at block gap

◆ USDHC_PROT_CTRL_IABG [2/3]

#define USDHC_PROT_CTRL_IABG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

IABG - Interrupt at block gap 0b1..Enables interrupt at block gap 0b0..Disables interrupt at block gap

◆ USDHC_PROT_CTRL_IABG [3/3]

#define USDHC_PROT_CTRL_IABG ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)

IABG - Interrupt at block gap 0b1..Enables interrupt at block gap 0b0..Disables interrupt at block gap

◆ USDHC_PROT_CTRL_LCTL

#define USDHC_PROT_CTRL_LCTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)

LCTL - LED control 0b1..LED on 0b0..LED off

◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD [1/3]

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

NON_EXACT_BLK_RD - Non-exact block read 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.

◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD [2/3]

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

NON_EXACT_BLK_RD - Non-exact block read 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.

◆ USDHC_PROT_CTRL_NON_EXACT_BLK_RD [3/3]

#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)

NON_EXACT_BLK_RD - Non-exact block read 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.

◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK [1/3]

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

RD_DONE_NO_8CLK - Read performed number 8 clock

◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK [2/3]

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

RD_DONE_NO_8CLK - Read performed number 8 clock

◆ USDHC_PROT_CTRL_RD_DONE_NO_8CLK [3/3]

#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)

RD_DONE_NO_8CLK - Read performed number 8 clock

◆ USDHC_PROT_CTRL_RWCTL [1/3]

#define USDHC_PROT_CTRL_RWCTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

RWCTL - Read wait control 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set

◆ USDHC_PROT_CTRL_RWCTL [2/3]

#define USDHC_PROT_CTRL_RWCTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

RWCTL - Read wait control 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set

◆ USDHC_PROT_CTRL_RWCTL [3/3]

#define USDHC_PROT_CTRL_RWCTL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)

RWCTL - Read wait control 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set

◆ USDHC_PROT_CTRL_SABGREQ [1/3]

#define USDHC_PROT_CTRL_SABGREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

SABGREQ - Stop at block gap request 0b1..Stop 0b0..Transfer

◆ USDHC_PROT_CTRL_SABGREQ [2/3]

#define USDHC_PROT_CTRL_SABGREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

SABGREQ - Stop at block gap request 0b1..Stop 0b0..Transfer

◆ USDHC_PROT_CTRL_SABGREQ [3/3]

#define USDHC_PROT_CTRL_SABGREQ ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)

SABGREQ - Stop at block gap request 0b1..Stop 0b0..Transfer

◆ USDHC_PROT_CTRL_WECINS [1/3]

#define USDHC_PROT_CTRL_WECINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

WECINS - Wakeup event enable on SD card insertion 0b1..Enable wakeup event enable on SD card insertion 0b0..Disable wakeup event enable on SD card insertion

◆ USDHC_PROT_CTRL_WECINS [2/3]

#define USDHC_PROT_CTRL_WECINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

WECINS - Wakeup event enable on SD card insertion 0b1..Enable wakeup event enable on SD card insertion 0b0..Disable wakeup event enable on SD card insertion

◆ USDHC_PROT_CTRL_WECINS [3/3]

#define USDHC_PROT_CTRL_WECINS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)

WECINS - Wakeup event enable on SD card insertion 0b1..Enable wakeup event enable on SD card insertion 0b0..Disable wakeup event enable on SD card insertion

◆ USDHC_PROT_CTRL_WECINT [1/3]

#define USDHC_PROT_CTRL_WECINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

WECINT - Wakeup event enable on card interrupt 0b1..Enables wakeup event enable on card interrupt 0b0..Disables wakeup event enable on card interrupt

◆ USDHC_PROT_CTRL_WECINT [2/3]

#define USDHC_PROT_CTRL_WECINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

WECINT - Wakeup event enable on card interrupt 0b1..Enables wakeup event enable on card interrupt 0b0..Disables wakeup event enable on card interrupt

◆ USDHC_PROT_CTRL_WECINT [3/3]

#define USDHC_PROT_CTRL_WECINT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)

WECINT - Wakeup event enable on card interrupt 0b1..Enables wakeup event enable on card interrupt 0b0..Disables wakeup event enable on card interrupt

◆ USDHC_PROT_CTRL_WECRM [1/3]

#define USDHC_PROT_CTRL_WECRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

WECRM - Wakeup event enable on SD card removal 0b1..Enables wakeup event enable on SD card removal 0b0..Disables wakeup event enable on SD card removal

◆ USDHC_PROT_CTRL_WECRM [2/3]

#define USDHC_PROT_CTRL_WECRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

WECRM - Wakeup event enable on SD card removal 0b1..Enables wakeup event enable on SD card removal 0b0..Disables wakeup event enable on SD card removal

◆ USDHC_PROT_CTRL_WECRM [3/3]

#define USDHC_PROT_CTRL_WECRM ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)

WECRM - Wakeup event enable on SD card removal 0b1..Enables wakeup event enable on SD card removal 0b0..Disables wakeup event enable on SD card removal

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)

STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)

STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)

STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)

STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

STROBE_DLL_CTRL_RESET - Strobe DLL control reset

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)

STROBE_DLL_CTRL_RESET - Strobe DLL control reset

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)

STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)

STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)

STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)

STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT [1/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval

◆ USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT [2/2]

#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)

STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK [1/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK [2/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)

STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL [1/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)

STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL [2/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)

STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK [1/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK [2/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)

STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL [1/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select

◆ USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL [2/2]

#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)

STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select

◆ USDHC_SYS_CTRL_DTOCV [1/3]

#define USDHC_SYS_CTRL_DTOCV ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

DTOCV - Data timeout counter value 0b1111..SDCLK x 2 31 recommend to use for HS400 mode 0b1110..SDCLK x 2 30 recommend to use for HS200/SDR104 mode 0b1101..SDCLK x 2 29 recommend to use for other speed mode except HS400/HS200/SDR104 mode 0b0011..SDCLK x 2 19 0b0010..SDCLK x 2 18 0b0001..SDCLK x 2 33 0b0000..SDCLK x 2 32

◆ USDHC_SYS_CTRL_DTOCV [2/3]

#define USDHC_SYS_CTRL_DTOCV ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

DTOCV - Data timeout counter value 0b1111..SDCLK x 2 29 0b1110..SDCLK x 2 28 0b1101..SDCLK x 2 27 0b1100..SDCLK x 2 26 0b1011..SDCLK x 2 25 0b1010..SDCLK x 2 24 0b1001..SDCLK x 2 23 0b1000..SDCLK x 2 22 0b0111..SDCLK x 2 21 0b0110..SDCLK x 2 20 0b0101..SDCLK x 2 19 0b0100..SDCLK x 2 18 0b0011..SDCLK x 2 17 0b0010..SDCLK x 2 16 0b0001..SDCLK x 2 15 0b0000..SDCLK x 2 14

◆ USDHC_SYS_CTRL_DTOCV [3/3]

#define USDHC_SYS_CTRL_DTOCV ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)

DTOCV - Data timeout counter value 0b1111..SDCLK x 2 29 0b1110..SDCLK x 2 28 0b1101..SDCLK x 2 27 0b1100..SDCLK x 2 26 0b1011..SDCLK x 2 25 0b1010..SDCLK x 2 24 0b1001..SDCLK x 2 23 0b1000..SDCLK x 2 22 0b0111..SDCLK x 2 21 0b0110..SDCLK x 2 20 0b0101..SDCLK x 2 19 0b0100..SDCLK x 2 18 0b0011..SDCLK x 2 17 0b0010..SDCLK x 2 16 0b0001..SDCLK x 2 15 0b0000..SDCLK x 2 14

◆ USDHC_SYS_CTRL_DVS [1/3]

#define USDHC_SYS_CTRL_DVS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

DVS - Divisor 0b0000..Divide-by-1 0b0001..Divide-by-2 0b1110..Divide-by-15 0b1111..Divide-by-16

◆ USDHC_SYS_CTRL_DVS [2/3]

#define USDHC_SYS_CTRL_DVS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

DVS - Divisor 0b0000..Divide-by-1 0b0001..Divide-by-2 0b1110..Divide-by-15 0b1111..Divide-by-16

◆ USDHC_SYS_CTRL_DVS [3/3]

#define USDHC_SYS_CTRL_DVS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)

DVS - Divisor 0b0000..Divide-by-1 0b0001..Divide-by-2 0b1110..Divide-by-15 0b1111..Divide-by-16

◆ USDHC_SYS_CTRL_INITA [1/3]

#define USDHC_SYS_CTRL_INITA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

INITA - Initialization active

◆ USDHC_SYS_CTRL_INITA [2/3]

#define USDHC_SYS_CTRL_INITA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

INITA - Initialization active

◆ USDHC_SYS_CTRL_INITA [3/3]

#define USDHC_SYS_CTRL_INITA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)

INITA - Initialization active

◆ USDHC_SYS_CTRL_IPP_RST_N [1/3]

#define USDHC_SYS_CTRL_IPP_RST_N ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

IPP_RST_N - Hardware reset

◆ USDHC_SYS_CTRL_IPP_RST_N [2/3]

#define USDHC_SYS_CTRL_IPP_RST_N ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

IPP_RST_N - Hardware reset

◆ USDHC_SYS_CTRL_IPP_RST_N [3/3]

#define USDHC_SYS_CTRL_IPP_RST_N ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)

IPP_RST_N - Hardware reset

◆ USDHC_SYS_CTRL_RSTA [1/3]

#define USDHC_SYS_CTRL_RSTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

RSTA - Software reset for all 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTA [2/3]

#define USDHC_SYS_CTRL_RSTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

RSTA - Software reset for all 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTA [3/3]

#define USDHC_SYS_CTRL_RSTA ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)

RSTA - Software reset for all 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTC [1/3]

#define USDHC_SYS_CTRL_RSTC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

RSTC - Software reset for CMD line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTC [2/3]

#define USDHC_SYS_CTRL_RSTC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

RSTC - Software reset for CMD line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTC [3/3]

#define USDHC_SYS_CTRL_RSTC ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)

RSTC - Software reset for CMD line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTD [1/3]

#define USDHC_SYS_CTRL_RSTD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

RSTD - Software reset for data line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTD [2/3]

#define USDHC_SYS_CTRL_RSTD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

RSTD - Software reset for data line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTD [3/3]

#define USDHC_SYS_CTRL_RSTD ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)

RSTD - Software reset for data line 0b1..Reset 0b0..No reset

◆ USDHC_SYS_CTRL_RSTT [1/3]

#define USDHC_SYS_CTRL_RSTT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

RSTT - Reset tuning

◆ USDHC_SYS_CTRL_RSTT [2/3]

#define USDHC_SYS_CTRL_RSTT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

RSTT - Reset tuning

◆ USDHC_SYS_CTRL_RSTT [3/3]

#define USDHC_SYS_CTRL_RSTT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)

RSTT - Reset tuning

◆ USDHC_SYS_CTRL_SDCLKFS [1/3]

#define USDHC_SYS_CTRL_SDCLKFS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

SDCLKFS - SDCLK frequency select

◆ USDHC_SYS_CTRL_SDCLKFS [2/3]

#define USDHC_SYS_CTRL_SDCLKFS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

SDCLKFS - SDCLK frequency select

◆ USDHC_SYS_CTRL_SDCLKFS [3/3]

#define USDHC_SYS_CTRL_SDCLKFS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)

SDCLKFS - SDCLK frequency select

◆ USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING [1/2]

#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning

◆ USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING [2/2]

#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)

DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning

◆ USDHC_TUNING_CTRL_STD_TUNING_EN [1/3]

#define USDHC_TUNING_CTRL_STD_TUNING_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

STD_TUNING_EN - Standard tuning circuit and procedure enable

◆ USDHC_TUNING_CTRL_STD_TUNING_EN [2/3]

#define USDHC_TUNING_CTRL_STD_TUNING_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

STD_TUNING_EN - Standard tuning circuit and procedure enable

◆ USDHC_TUNING_CTRL_STD_TUNING_EN [3/3]

#define USDHC_TUNING_CTRL_STD_TUNING_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)

STD_TUNING_EN - Standard tuning circuit and procedure enable

◆ USDHC_TUNING_CTRL_TUNING_COUNTER [1/3]

#define USDHC_TUNING_CTRL_TUNING_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

TUNING_COUNTER - Tuning counter

◆ USDHC_TUNING_CTRL_TUNING_COUNTER [2/3]

#define USDHC_TUNING_CTRL_TUNING_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

TUNING_COUNTER - Tuning counter

◆ USDHC_TUNING_CTRL_TUNING_COUNTER [3/3]

#define USDHC_TUNING_CTRL_TUNING_COUNTER ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)

TUNING_COUNTER - Tuning counter

◆ USDHC_TUNING_CTRL_TUNING_START_TAP [1/3]

#define USDHC_TUNING_CTRL_TUNING_START_TAP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

TUNING_START_TAP - Tuning start

◆ USDHC_TUNING_CTRL_TUNING_START_TAP [2/3]

#define USDHC_TUNING_CTRL_TUNING_START_TAP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

TUNING_START_TAP - Tuning start

◆ USDHC_TUNING_CTRL_TUNING_START_TAP [3/3]

#define USDHC_TUNING_CTRL_TUNING_START_TAP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)

TUNING_START_TAP - Tuning start

◆ USDHC_TUNING_CTRL_TUNING_STEP [1/3]

#define USDHC_TUNING_CTRL_TUNING_STEP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

TUNING_STEP - TUNING_STEP

◆ USDHC_TUNING_CTRL_TUNING_STEP [2/3]

#define USDHC_TUNING_CTRL_TUNING_STEP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

TUNING_STEP - TUNING_STEP

◆ USDHC_TUNING_CTRL_TUNING_STEP [3/3]

#define USDHC_TUNING_CTRL_TUNING_STEP ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)

TUNING_STEP - TUNING_STEP

◆ USDHC_TUNING_CTRL_TUNING_WINDOW [1/3]

#define USDHC_TUNING_CTRL_TUNING_WINDOW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

TUNING_WINDOW - Data window

◆ USDHC_TUNING_CTRL_TUNING_WINDOW [2/3]

#define USDHC_TUNING_CTRL_TUNING_WINDOW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

TUNING_WINDOW - Data window

◆ USDHC_TUNING_CTRL_TUNING_WINDOW [3/3]

#define USDHC_TUNING_CTRL_TUNING_WINDOW ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)

TUNING_WINDOW - Data window

◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN [1/3]

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. 0b0..Disable

◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN [2/3]

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. 0b0..Disable

◆ USDHC_VEND_SPEC2_ACMD23_ARGU2_EN [3/3]

#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)

ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled. 0b0..Disable

◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST [1/3]

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

CARD_INT_D3_TEST - Card interrupt detection test 0b0..Check the card interrupt only when DATA3 is high. 0b1..Check the card interrupt by ignoring the status of DATA3.

◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST [2/3]

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

CARD_INT_D3_TEST - Card interrupt detection test 0b0..Check the card interrupt only when DATA3 is high. 0b1..Check the card interrupt by ignoring the status of DATA3.

◆ USDHC_VEND_SPEC2_CARD_INT_D3_TEST [3/3]

#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)

CARD_INT_D3_TEST - Card interrupt detection test 0b0..Check the card interrupt only when DATA3 is high. 0b1..Check the card interrupt by ignoring the status of DATA3.

◆ USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN [1/2]

#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

HS400_RD_CLK_STOP_EN - HS400 read clock stop enable

◆ USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN [2/2]

#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)

HS400_RD_CLK_STOP_EN - HS400 read clock stop enable

◆ USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN [1/2]

#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

HS400_WR_CLK_STOP_EN - HS400 write clock stop enable

◆ USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN [2/2]

#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)

HS400_WR_CLK_STOP_EN - HS400 write clock stop enable

◆ USDHC_VEND_SPEC2_TUNING_1bit_EN [1/3]

#define USDHC_VEND_SPEC2_TUNING_1bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

TUNING_1bit_EN - Tuning 1bit enable

◆ USDHC_VEND_SPEC2_TUNING_1bit_EN [2/3]

#define USDHC_VEND_SPEC2_TUNING_1bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

TUNING_1bit_EN - Tuning 1bit enable

◆ USDHC_VEND_SPEC2_TUNING_1bit_EN [3/3]

#define USDHC_VEND_SPEC2_TUNING_1bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)

TUNING_1bit_EN - Tuning 1bit enable

◆ USDHC_VEND_SPEC2_TUNING_8bit_EN [1/3]

#define USDHC_VEND_SPEC2_TUNING_8bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

TUNING_8bit_EN - Tuning 8bit enable

◆ USDHC_VEND_SPEC2_TUNING_8bit_EN [2/3]

#define USDHC_VEND_SPEC2_TUNING_8bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

TUNING_8bit_EN - Tuning 8bit enable

◆ USDHC_VEND_SPEC2_TUNING_8bit_EN [3/3]

#define USDHC_VEND_SPEC2_TUNING_8bit_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)

TUNING_8bit_EN - Tuning 8bit enable

◆ USDHC_VEND_SPEC2_TUNING_CMD_EN [1/3]

#define USDHC_VEND_SPEC2_TUNING_CMD_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

TUNING_CMD_EN - Tuning command enable 0b0..Auto tuning circuit does not check the CMD line. 0b1..Auto tuning circuit checks the CMD line.

◆ USDHC_VEND_SPEC2_TUNING_CMD_EN [2/3]

#define USDHC_VEND_SPEC2_TUNING_CMD_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

TUNING_CMD_EN - Tuning command enable 0b0..Auto tuning circuit does not check the CMD line. 0b1..Auto tuning circuit checks the CMD line.

◆ USDHC_VEND_SPEC2_TUNING_CMD_EN [3/3]

#define USDHC_VEND_SPEC2_TUNING_CMD_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)

TUNING_CMD_EN - Tuning command enable 0b0..Auto tuning circuit does not check the CMD line. 0b1..Auto tuning circuit checks the CMD line.

◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN [1/3]

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

AC12_WR_CHKBUSY_EN - Check busy enable 0b0..Do not check busy after auto CMD12 for write data packet 0b1..Check busy after auto CMD12 for write data packet

◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN [2/3]

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

AC12_WR_CHKBUSY_EN - Check busy enable 0b0..Do not check busy after auto CMD12 for write data packet 0b1..Check busy after auto CMD12 for write data packet

◆ USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN [3/3]

#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)

AC12_WR_CHKBUSY_EN - Check busy enable 0b0..Do not check busy after auto CMD12 for write data packet 0b1..Check busy after auto CMD12 for write data packet

◆ USDHC_VEND_SPEC_CMD_BYTE_EN [1/3]

#define USDHC_VEND_SPEC_CMD_BYTE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

CMD_BYTE_EN - Byte access 0b0..Disable 0b1..Enable

◆ USDHC_VEND_SPEC_CMD_BYTE_EN [2/3]

#define USDHC_VEND_SPEC_CMD_BYTE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

CMD_BYTE_EN - Byte access 0b0..Disable 0b1..Enable

◆ USDHC_VEND_SPEC_CMD_BYTE_EN [3/3]

#define USDHC_VEND_SPEC_CMD_BYTE_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)

CMD_BYTE_EN - Byte access 0b0..Disable 0b1..Enable

◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN [1/3]

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

CONFLICT_CHK_EN - Conflict check enable 0b0..Conflict check disable 0b1..Conflict check enable

◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN [2/3]

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

CONFLICT_CHK_EN - Conflict check enable 0b0..Conflict check disable 0b1..Conflict check enable

◆ USDHC_VEND_SPEC_CONFLICT_CHK_EN [3/3]

#define USDHC_VEND_SPEC_CONFLICT_CHK_EN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)

CONFLICT_CHK_EN - Conflict check enable 0b0..Conflict check disable 0b1..Conflict check enable

◆ USDHC_VEND_SPEC_CRC_CHK_DIS [1/3]

#define USDHC_VEND_SPEC_CRC_CHK_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

CRC_CHK_DIS - CRC Check Disable 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet

◆ USDHC_VEND_SPEC_CRC_CHK_DIS [2/3]

#define USDHC_VEND_SPEC_CRC_CHK_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

CRC_CHK_DIS - CRC Check Disable 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet

◆ USDHC_VEND_SPEC_CRC_CHK_DIS [3/3]

#define USDHC_VEND_SPEC_CRC_CHK_DIS ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)

CRC_CHK_DIS - CRC Check Disable 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet

◆ USDHC_VEND_SPEC_FRC_SDCLK_ON [1/3]

#define USDHC_VEND_SPEC_FRC_SDCLK_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

FRC_SDCLK_ON - Force CLK 0b0..CLK active or inactive is fully controlled by the hardware. 0b1..Force CLK active

◆ USDHC_VEND_SPEC_FRC_SDCLK_ON [2/3]

#define USDHC_VEND_SPEC_FRC_SDCLK_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

FRC_SDCLK_ON - Force CLK 0b0..CLK active or inactive is fully controlled by the hardware. 0b1..Force CLK active

◆ USDHC_VEND_SPEC_FRC_SDCLK_ON [3/3]

#define USDHC_VEND_SPEC_FRC_SDCLK_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)

FRC_SDCLK_ON - Force CLK 0b0..CLK active or inactive is fully controlled by the hardware. 0b1..Force CLK active

◆ USDHC_VEND_SPEC_VSELECT [1/3]

#define USDHC_VEND_SPEC_VSELECT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

VSELECT - Voltage selection 0b1..Change the voltage to low voltage range, around 1.8 V 0b0..Change the voltage to high voltage range, around 3.0 V

◆ USDHC_VEND_SPEC_VSELECT [2/3]

#define USDHC_VEND_SPEC_VSELECT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

VSELECT - Voltage selection 0b1..Change the voltage to low voltage range, around 1.8 V 0b0..Change the voltage to high voltage range, around 3.0 V

◆ USDHC_VEND_SPEC_VSELECT [3/3]

#define USDHC_VEND_SPEC_VSELECT ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)

VSELECT - Voltage selection 0b1..Change the voltage to low voltage range, around 1.8 V 0b0..Change the voltage to high voltage range, around 3.0 V

◆ USDHC_WTMK_LVL_RD_BRST_LEN

#define USDHC_WTMK_LVL_RD_BRST_LEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)

RD_BRST_LEN - Read burst length due to system restriction, the actual burst length might not exceed 16

◆ USDHC_WTMK_LVL_RD_WML [1/3]

#define USDHC_WTMK_LVL_RD_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

RD_WML - Read watermark level

◆ USDHC_WTMK_LVL_RD_WML [2/3]

#define USDHC_WTMK_LVL_RD_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

RD_WML - Read watermark level

◆ USDHC_WTMK_LVL_RD_WML [3/3]

#define USDHC_WTMK_LVL_RD_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)

RD_WML - Read watermark level

◆ USDHC_WTMK_LVL_WR_BRST_LEN

#define USDHC_WTMK_LVL_WR_BRST_LEN ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)

WR_BRST_LEN - Write burst length due to system restriction, the actual burst length might not exceed 16

◆ USDHC_WTMK_LVL_WR_WML [1/3]

#define USDHC_WTMK_LVL_WR_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

WR_WML - Write watermark level

◆ USDHC_WTMK_LVL_WR_WML [2/3]

#define USDHC_WTMK_LVL_WR_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

WR_WML - Write watermark level

◆ USDHC_WTMK_LVL_WR_WML [3/3]

#define USDHC_WTMK_LVL_WR_WML ( x ) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)

WR_WML - Write watermark level

DS_ADDR - DMA System Address

BLK_ATT - Block Attributes

CMD_ARG - Command Argument

CMD_XFR_TYP - Command Transfer Type

CMD_RSP0 - Command Response0

CMD_RSP1 - Command Response1

CMD_RSP2 - Command Response2

CMD_RSP3 - Command Response3

DATA_BUFF_ACC_PORT - Data Buffer Access Port

PRES_STATE - Present State

PROT_CTRL - Protocol Control

SYS_CTRL - System Control

INT_STATUS - Interrupt Status

INT_STATUS_EN - Interrupt Status Enable

INT_SIGNAL_EN - Interrupt Signal Enable

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status

HOST_CTRL_CAP - Host Controller Capabilities

WTMK_LVL - Watermark Level

MIX_CTRL - Mixer Control

FORCE_EVENT - Force Event

ADMA_ERR_STATUS - ADMA Error Status

ADMA_SYS_ADDR - ADMA System Address

DLL_CTRL - DLL (Delay Line) Control

DLL_STATUS - DLL Status

CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status

VEND_SPEC - Vendor Specific Register

MMC_BOOT - MMC Boot

VEND_SPEC2 - Vendor Specific 2 Register

TUNING_CTRL - Tuning Control

DS_ADDR - DMA System Address

BLK_ATT - Block Attributes

CMD_ARG - Command Argument

CMD_XFR_TYP - Command Transfer Type

CMD_RSP0 - Command Response0

CMD_RSP1 - Command Response1

CMD_RSP2 - Command Response2

CMD_RSP3 - Command Response3

DATA_BUFF_ACC_PORT - Data Buffer Access Port

PRES_STATE - Present State

PROT_CTRL - Protocol Control

SYS_CTRL - System Control

INT_STATUS - Interrupt Status

INT_STATUS_EN - Interrupt Status Enable

INT_SIGNAL_EN - Interrupt Signal Enable

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status

HOST_CTRL_CAP - Host Controller Capabilities

WTMK_LVL - Watermark Level

MIX_CTRL - Mixer Control

FORCE_EVENT - Force Event

ADMA_ERR_STATUS - ADMA Error Status

ADMA_SYS_ADDR - ADMA System Address

DLL_CTRL - DLL (Delay Line) Control

DLL_STATUS - DLL Status

CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status

STROBE_DLL_CTRL - Strobe DLL control

STROBE_DLL_STATUS - Strobe DLL status

VEND_SPEC - Vendor Specific Register

MMC_BOOT - MMC Boot

VEND_SPEC2 - Vendor Specific 2 Register

TUNING_CTRL - Tuning Control

DS_ADDR - DMA System Address

BLK_ATT - Block Attributes

CMD_ARG - Command Argument

CMD_XFR_TYP - Command Transfer Type

CMD_RSP0 - Command Response0

CMD_RSP1 - Command Response1

CMD_RSP2 - Command Response2

CMD_RSP3 - Command Response3

DATA_BUFF_ACC_PORT - Data Buffer Access Port

PRES_STATE - Present State

PROT_CTRL - Protocol Control

SYS_CTRL - System Control

INT_STATUS - Interrupt Status

INT_STATUS_EN - Interrupt Status Enable

INT_SIGNAL_EN - Interrupt Signal Enable

AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status

HOST_CTRL_CAP - Host Controller Capabilities

WTMK_LVL - Watermark Level

MIX_CTRL - Mixer Control

FORCE_EVENT - Force Event