Macros
#define	TMR_COMP1_COUNT (4U)

#define	TMR_COMP2_COUNT (4U)

#define	TMR_CAPT_COUNT (4U)

#define	TMR_LOAD_COUNT (4U)

#define	TMR_HOLD_COUNT (4U)

#define	TMR_CNTR_COUNT (4U)

#define	TMR_CTRL_COUNT (4U)

#define	TMR_SCTRL_COUNT (4U)

#define	TMR_CMPLD1_COUNT (4U)

#define	TMR_CMPLD2_COUNT (4U)

#define	TMR_CSCTRL_COUNT (4U)

#define	TMR_FILT_COUNT (4U)

#define	TMR_DMA_COUNT (4U)

#define	TMR_ENBL_COUNT (4U)

#define	TMR_COMP1_COUNT (4U)

#define	TMR_COMP2_COUNT (4U)

#define	TMR_CAPT_COUNT (4U)

#define	TMR_LOAD_COUNT (4U)

#define	TMR_HOLD_COUNT (4U)

#define	TMR_CNTR_COUNT (4U)

#define	TMR_CTRL_COUNT (4U)

#define	TMR_SCTRL_COUNT (4U)

#define	TMR_CMPLD1_COUNT (4U)

#define	TMR_CMPLD2_COUNT (4U)

#define	TMR_CSCTRL_COUNT (4U)

#define	TMR_FILT_COUNT (4U)

#define	TMR_DMA_COUNT (4U)

#define	TMR_ENBL_COUNT (4U)

#define	TMR_COMP1_COUNT (4U)

#define	TMR_COMP2_COUNT (4U)

#define	TMR_CAPT_COUNT (4U)

#define	TMR_LOAD_COUNT (4U)

#define	TMR_HOLD_COUNT (4U)

#define	TMR_CNTR_COUNT (4U)

#define	TMR_CTRL_COUNT (4U)

#define	TMR_SCTRL_COUNT (4U)

#define	TMR_CMPLD1_COUNT (4U)

#define	TMR_CMPLD2_COUNT (4U)

#define	TMR_CSCTRL_COUNT (4U)

#define	TMR_FILT_COUNT (4U)

#define	TMR_DMA_COUNT (4U)

#define	TMR_ENBL_COUNT (4U)

COMP1 - Timer Channel Compare Register 1
#define	TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)

#define	TMR_COMP1_COMPARISON_1_SHIFT (0U)

#define	TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMP2 - Timer Channel Compare Register 2
#define	TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)

#define	TMR_COMP2_COMPARISON_2_SHIFT (0U)

#define	TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

CAPT - Timer Channel Capture Register
#define	TMR_CAPT_CAPTURE_MASK (0xFFFFU)

#define	TMR_CAPT_CAPTURE_SHIFT (0U)

#define	TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

LOAD - Timer Channel Load Register
#define	TMR_LOAD_LOAD_MASK (0xFFFFU)

#define	TMR_LOAD_LOAD_SHIFT (0U)

#define	TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

HOLD - Timer Channel Hold Register
#define	TMR_HOLD_HOLD_MASK (0xFFFFU)

#define	TMR_HOLD_HOLD_SHIFT (0U)

#define	TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

CNTR - Timer Channel Counter Register
#define	TMR_CNTR_COUNTER_MASK (0xFFFFU)

#define	TMR_CNTR_COUNTER_SHIFT (0U)

#define	TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

CTRL - Timer Channel Control Register
#define	TMR_CTRL_OUTMODE_MASK (0x7U)

#define	TMR_CTRL_OUTMODE_SHIFT (0U)

#define	TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

#define	TMR_CTRL_COINIT_MASK (0x8U)

#define	TMR_CTRL_COINIT_SHIFT (3U)

#define	TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

#define	TMR_CTRL_DIR_MASK (0x10U)

#define	TMR_CTRL_DIR_SHIFT (4U)

#define	TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

#define	TMR_CTRL_LENGTH_MASK (0x20U)

#define	TMR_CTRL_LENGTH_SHIFT (5U)

#define	TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

#define	TMR_CTRL_ONCE_MASK (0x40U)

#define	TMR_CTRL_ONCE_SHIFT (6U)

#define	TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

#define	TMR_CTRL_SCS_MASK (0x180U)

#define	TMR_CTRL_SCS_SHIFT (7U)

#define	TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

#define	TMR_CTRL_PCS_MASK (0x1E00U)

#define	TMR_CTRL_PCS_SHIFT (9U)

#define	TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

#define	TMR_CTRL_CM_MASK (0xE000U)

#define	TMR_CTRL_CM_SHIFT (13U)

#define	TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

SCTRL - Timer Channel Status and Control Register
#define	TMR_SCTRL_OEN_MASK (0x1U)

#define	TMR_SCTRL_OEN_SHIFT (0U)

#define	TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

#define	TMR_SCTRL_OPS_MASK (0x2U)

#define	TMR_SCTRL_OPS_SHIFT (1U)

#define	TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

#define	TMR_SCTRL_FORCE_MASK (0x4U)

#define	TMR_SCTRL_FORCE_SHIFT (2U)

#define	TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

#define	TMR_SCTRL_VAL_MASK (0x8U)

#define	TMR_SCTRL_VAL_SHIFT (3U)

#define	TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

#define	TMR_SCTRL_EEOF_MASK (0x10U)

#define	TMR_SCTRL_EEOF_SHIFT (4U)

#define	TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

#define	TMR_SCTRL_MSTR_MASK (0x20U)

#define	TMR_SCTRL_MSTR_SHIFT (5U)

#define	TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

#define	TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)

#define	TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)

#define	TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

#define	TMR_SCTRL_INPUT_MASK (0x100U)

#define	TMR_SCTRL_INPUT_SHIFT (8U)

#define	TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

#define	TMR_SCTRL_IPS_MASK (0x200U)

#define	TMR_SCTRL_IPS_SHIFT (9U)

#define	TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

#define	TMR_SCTRL_IEFIE_MASK (0x400U)

#define	TMR_SCTRL_IEFIE_SHIFT (10U)

#define	TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

#define	TMR_SCTRL_IEF_MASK (0x800U)

#define	TMR_SCTRL_IEF_SHIFT (11U)

#define	TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

#define	TMR_SCTRL_TOFIE_MASK (0x1000U)

#define	TMR_SCTRL_TOFIE_SHIFT (12U)

#define	TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

#define	TMR_SCTRL_TOF_MASK (0x2000U)

#define	TMR_SCTRL_TOF_SHIFT (13U)

#define	TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

#define	TMR_SCTRL_TCFIE_MASK (0x4000U)

#define	TMR_SCTRL_TCFIE_SHIFT (14U)

#define	TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

#define	TMR_SCTRL_TCF_MASK (0x8000U)

#define	TMR_SCTRL_TCF_SHIFT (15U)

#define	TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

CMPLD1 - Timer Channel Comparator Load Register 1
#define	TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

CMPLD2 - Timer Channel Comparator Load Register 2
#define	TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

CSCTRL - Timer Channel Comparator Status and Control Register
#define	TMR_CSCTRL_CL1_MASK (0x3U)

#define	TMR_CSCTRL_CL1_SHIFT (0U)

#define	TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

#define	TMR_CSCTRL_CL2_MASK (0xCU)

#define	TMR_CSCTRL_CL2_SHIFT (2U)

#define	TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

#define	TMR_CSCTRL_TCF1_MASK (0x10U)

#define	TMR_CSCTRL_TCF1_SHIFT (4U)

#define	TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

#define	TMR_CSCTRL_TCF2_MASK (0x20U)

#define	TMR_CSCTRL_TCF2_SHIFT (5U)

#define	TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

#define	TMR_CSCTRL_TCF1EN_MASK (0x40U)

#define	TMR_CSCTRL_TCF1EN_SHIFT (6U)

#define	TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

#define	TMR_CSCTRL_TCF2EN_MASK (0x80U)

#define	TMR_CSCTRL_TCF2EN_SHIFT (7U)

#define	TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

#define	TMR_CSCTRL_UP_MASK (0x200U)

#define	TMR_CSCTRL_UP_SHIFT (9U)

#define	TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

#define	TMR_CSCTRL_TCI_MASK (0x400U)

#define	TMR_CSCTRL_TCI_SHIFT (10U)

#define	TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

#define	TMR_CSCTRL_ROC_MASK (0x800U)

#define	TMR_CSCTRL_ROC_SHIFT (11U)

#define	TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

#define	TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)

#define	TMR_CSCTRL_ALT_LOAD_SHIFT (12U)

#define	TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

#define	TMR_CSCTRL_FAULT_MASK (0x2000U)

#define	TMR_CSCTRL_FAULT_SHIFT (13U)

#define	TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

#define	TMR_CSCTRL_DBG_EN_MASK (0xC000U)

#define	TMR_CSCTRL_DBG_EN_SHIFT (14U)

#define	TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

FILT - Timer Channel Input Filter Register
#define	TMR_FILT_FILT_PER_MASK (0xFFU)

#define	TMR_FILT_FILT_PER_SHIFT (0U)

#define	TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

#define	TMR_FILT_FILT_CNT_MASK (0x700U)

#define	TMR_FILT_FILT_CNT_SHIFT (8U)

#define	TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

DMA - Timer Channel DMA Enable Register
#define	TMR_DMA_IEFDE_MASK (0x1U)

#define	TMR_DMA_IEFDE_SHIFT (0U)

#define	TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

#define	TMR_DMA_CMPLD1DE_MASK (0x2U)

#define	TMR_DMA_CMPLD1DE_SHIFT (1U)

#define	TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

#define	TMR_DMA_CMPLD2DE_MASK (0x4U)

#define	TMR_DMA_CMPLD2DE_SHIFT (2U)

#define	TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

ENBL - Timer Channel Enable Register
#define	TMR_ENBL_ENBL_MASK (0xFU)

#define	TMR_ENBL_ENBL_SHIFT (0U)

#define	TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

COMP1 - Timer Channel Compare Register 1
#define	TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)

#define	TMR_COMP1_COMPARISON_1_SHIFT (0U)

#define	TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMP2 - Timer Channel Compare Register 2
#define	TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)

#define	TMR_COMP2_COMPARISON_2_SHIFT (0U)

#define	TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

CAPT - Timer Channel Capture Register
#define	TMR_CAPT_CAPTURE_MASK (0xFFFFU)

#define	TMR_CAPT_CAPTURE_SHIFT (0U)

#define	TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

LOAD - Timer Channel Load Register
#define	TMR_LOAD_LOAD_MASK (0xFFFFU)

#define	TMR_LOAD_LOAD_SHIFT (0U)

#define	TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

HOLD - Timer Channel Hold Register
#define	TMR_HOLD_HOLD_MASK (0xFFFFU)

#define	TMR_HOLD_HOLD_SHIFT (0U)

#define	TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

CNTR - Timer Channel Counter Register
#define	TMR_CNTR_COUNTER_MASK (0xFFFFU)

#define	TMR_CNTR_COUNTER_SHIFT (0U)

#define	TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

CTRL - Timer Channel Control Register
#define	TMR_CTRL_OUTMODE_MASK (0x7U)

#define	TMR_CTRL_OUTMODE_SHIFT (0U)

#define	TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

#define	TMR_CTRL_COINIT_MASK (0x8U)

#define	TMR_CTRL_COINIT_SHIFT (3U)

#define	TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

#define	TMR_CTRL_DIR_MASK (0x10U)

#define	TMR_CTRL_DIR_SHIFT (4U)

#define	TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

#define	TMR_CTRL_LENGTH_MASK (0x20U)

#define	TMR_CTRL_LENGTH_SHIFT (5U)

#define	TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

#define	TMR_CTRL_ONCE_MASK (0x40U)

#define	TMR_CTRL_ONCE_SHIFT (6U)

#define	TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

#define	TMR_CTRL_SCS_MASK (0x180U)

#define	TMR_CTRL_SCS_SHIFT (7U)

#define	TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

#define	TMR_CTRL_PCS_MASK (0x1E00U)

#define	TMR_CTRL_PCS_SHIFT (9U)

#define	TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

#define	TMR_CTRL_CM_MASK (0xE000U)

#define	TMR_CTRL_CM_SHIFT (13U)

#define	TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

SCTRL - Timer Channel Status and Control Register
#define	TMR_SCTRL_OEN_MASK (0x1U)

#define	TMR_SCTRL_OEN_SHIFT (0U)

#define	TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

#define	TMR_SCTRL_OPS_MASK (0x2U)

#define	TMR_SCTRL_OPS_SHIFT (1U)

#define	TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

#define	TMR_SCTRL_FORCE_MASK (0x4U)

#define	TMR_SCTRL_FORCE_SHIFT (2U)

#define	TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

#define	TMR_SCTRL_VAL_MASK (0x8U)

#define	TMR_SCTRL_VAL_SHIFT (3U)

#define	TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

#define	TMR_SCTRL_EEOF_MASK (0x10U)

#define	TMR_SCTRL_EEOF_SHIFT (4U)

#define	TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

#define	TMR_SCTRL_MSTR_MASK (0x20U)

#define	TMR_SCTRL_MSTR_SHIFT (5U)

#define	TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

#define	TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)

#define	TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)

#define	TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

#define	TMR_SCTRL_INPUT_MASK (0x100U)

#define	TMR_SCTRL_INPUT_SHIFT (8U)

#define	TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

#define	TMR_SCTRL_IPS_MASK (0x200U)

#define	TMR_SCTRL_IPS_SHIFT (9U)

#define	TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

#define	TMR_SCTRL_IEFIE_MASK (0x400U)

#define	TMR_SCTRL_IEFIE_SHIFT (10U)

#define	TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

#define	TMR_SCTRL_IEF_MASK (0x800U)

#define	TMR_SCTRL_IEF_SHIFT (11U)

#define	TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

#define	TMR_SCTRL_TOFIE_MASK (0x1000U)

#define	TMR_SCTRL_TOFIE_SHIFT (12U)

#define	TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

#define	TMR_SCTRL_TOF_MASK (0x2000U)

#define	TMR_SCTRL_TOF_SHIFT (13U)

#define	TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

#define	TMR_SCTRL_TCFIE_MASK (0x4000U)

#define	TMR_SCTRL_TCFIE_SHIFT (14U)

#define	TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

#define	TMR_SCTRL_TCF_MASK (0x8000U)

#define	TMR_SCTRL_TCF_SHIFT (15U)

#define	TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

CMPLD1 - Timer Channel Comparator Load Register 1
#define	TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

CMPLD2 - Timer Channel Comparator Load Register 2
#define	TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

CSCTRL - Timer Channel Comparator Status and Control Register
#define	TMR_CSCTRL_CL1_MASK (0x3U)

#define	TMR_CSCTRL_CL1_SHIFT (0U)

#define	TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

#define	TMR_CSCTRL_CL2_MASK (0xCU)

#define	TMR_CSCTRL_CL2_SHIFT (2U)

#define	TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

#define	TMR_CSCTRL_TCF1_MASK (0x10U)

#define	TMR_CSCTRL_TCF1_SHIFT (4U)

#define	TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

#define	TMR_CSCTRL_TCF2_MASK (0x20U)

#define	TMR_CSCTRL_TCF2_SHIFT (5U)

#define	TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

#define	TMR_CSCTRL_TCF1EN_MASK (0x40U)

#define	TMR_CSCTRL_TCF1EN_SHIFT (6U)

#define	TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

#define	TMR_CSCTRL_TCF2EN_MASK (0x80U)

#define	TMR_CSCTRL_TCF2EN_SHIFT (7U)

#define	TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

#define	TMR_CSCTRL_UP_MASK (0x200U)

#define	TMR_CSCTRL_UP_SHIFT (9U)

#define	TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

#define	TMR_CSCTRL_TCI_MASK (0x400U)

#define	TMR_CSCTRL_TCI_SHIFT (10U)

#define	TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

#define	TMR_CSCTRL_ROC_MASK (0x800U)

#define	TMR_CSCTRL_ROC_SHIFT (11U)

#define	TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

#define	TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)

#define	TMR_CSCTRL_ALT_LOAD_SHIFT (12U)

#define	TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

#define	TMR_CSCTRL_FAULT_MASK (0x2000U)

#define	TMR_CSCTRL_FAULT_SHIFT (13U)

#define	TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

#define	TMR_CSCTRL_DBG_EN_MASK (0xC000U)

#define	TMR_CSCTRL_DBG_EN_SHIFT (14U)

#define	TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

FILT - Timer Channel Input Filter Register
#define	TMR_FILT_FILT_PER_MASK (0xFFU)

#define	TMR_FILT_FILT_PER_SHIFT (0U)

#define	TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

#define	TMR_FILT_FILT_CNT_MASK (0x700U)

#define	TMR_FILT_FILT_CNT_SHIFT (8U)

#define	TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

DMA - Timer Channel DMA Enable Register
#define	TMR_DMA_IEFDE_MASK (0x1U)

#define	TMR_DMA_IEFDE_SHIFT (0U)

#define	TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

#define	TMR_DMA_CMPLD1DE_MASK (0x2U)

#define	TMR_DMA_CMPLD1DE_SHIFT (1U)

#define	TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

#define	TMR_DMA_CMPLD2DE_MASK (0x4U)

#define	TMR_DMA_CMPLD2DE_SHIFT (2U)

#define	TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

ENBL - Timer Channel Enable Register
#define	TMR_ENBL_ENBL_MASK (0xFU)

#define	TMR_ENBL_ENBL_SHIFT (0U)

#define	TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

COMP1 - Timer Channel Compare Register 1
#define	TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)

#define	TMR_COMP1_COMPARISON_1_SHIFT (0U)

#define	TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMP2 - Timer Channel Compare Register 2
#define	TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)

#define	TMR_COMP2_COMPARISON_2_SHIFT (0U)

#define	TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

CAPT - Timer Channel Capture Register
#define	TMR_CAPT_CAPTURE_MASK (0xFFFFU)

#define	TMR_CAPT_CAPTURE_SHIFT (0U)

#define	TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

LOAD - Timer Channel Load Register
#define	TMR_LOAD_LOAD_MASK (0xFFFFU)

#define	TMR_LOAD_LOAD_SHIFT (0U)

#define	TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

HOLD - Timer Channel Hold Register
#define	TMR_HOLD_HOLD_MASK (0xFFFFU)

#define	TMR_HOLD_HOLD_SHIFT (0U)

#define	TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

CNTR - Timer Channel Counter Register
#define	TMR_CNTR_COUNTER_MASK (0xFFFFU)

#define	TMR_CNTR_COUNTER_SHIFT (0U)

#define	TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

CTRL - Timer Channel Control Register
#define	TMR_CTRL_OUTMODE_MASK (0x7U)

#define	TMR_CTRL_OUTMODE_SHIFT (0U)

#define	TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

#define	TMR_CTRL_COINIT_MASK (0x8U)

#define	TMR_CTRL_COINIT_SHIFT (3U)

#define	TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

#define	TMR_CTRL_DIR_MASK (0x10U)

#define	TMR_CTRL_DIR_SHIFT (4U)

#define	TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

#define	TMR_CTRL_LENGTH_MASK (0x20U)

#define	TMR_CTRL_LENGTH_SHIFT (5U)

#define	TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

#define	TMR_CTRL_ONCE_MASK (0x40U)

#define	TMR_CTRL_ONCE_SHIFT (6U)

#define	TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

#define	TMR_CTRL_SCS_MASK (0x180U)

#define	TMR_CTRL_SCS_SHIFT (7U)

#define	TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

#define	TMR_CTRL_PCS_MASK (0x1E00U)

#define	TMR_CTRL_PCS_SHIFT (9U)

#define	TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

#define	TMR_CTRL_CM_MASK (0xE000U)

#define	TMR_CTRL_CM_SHIFT (13U)

#define	TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

SCTRL - Timer Channel Status and Control Register
#define	TMR_SCTRL_OEN_MASK (0x1U)

#define	TMR_SCTRL_OEN_SHIFT (0U)

#define	TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

#define	TMR_SCTRL_OPS_MASK (0x2U)

#define	TMR_SCTRL_OPS_SHIFT (1U)

#define	TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

#define	TMR_SCTRL_FORCE_MASK (0x4U)

#define	TMR_SCTRL_FORCE_SHIFT (2U)

#define	TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

#define	TMR_SCTRL_VAL_MASK (0x8U)

#define	TMR_SCTRL_VAL_SHIFT (3U)

#define	TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

#define	TMR_SCTRL_EEOF_MASK (0x10U)

#define	TMR_SCTRL_EEOF_SHIFT (4U)

#define	TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

#define	TMR_SCTRL_MSTR_MASK (0x20U)

#define	TMR_SCTRL_MSTR_SHIFT (5U)

#define	TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

#define	TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)

#define	TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)

#define	TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

#define	TMR_SCTRL_INPUT_MASK (0x100U)

#define	TMR_SCTRL_INPUT_SHIFT (8U)

#define	TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

#define	TMR_SCTRL_IPS_MASK (0x200U)

#define	TMR_SCTRL_IPS_SHIFT (9U)

#define	TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

#define	TMR_SCTRL_IEFIE_MASK (0x400U)

#define	TMR_SCTRL_IEFIE_SHIFT (10U)

#define	TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

#define	TMR_SCTRL_IEF_MASK (0x800U)

#define	TMR_SCTRL_IEF_SHIFT (11U)

#define	TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

#define	TMR_SCTRL_TOFIE_MASK (0x1000U)

#define	TMR_SCTRL_TOFIE_SHIFT (12U)

#define	TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

#define	TMR_SCTRL_TOF_MASK (0x2000U)

#define	TMR_SCTRL_TOF_SHIFT (13U)

#define	TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

#define	TMR_SCTRL_TCFIE_MASK (0x4000U)

#define	TMR_SCTRL_TCFIE_SHIFT (14U)

#define	TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

#define	TMR_SCTRL_TCF_MASK (0x8000U)

#define	TMR_SCTRL_TCF_SHIFT (15U)

#define	TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

CMPLD1 - Timer Channel Comparator Load Register 1
#define	TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)

#define	TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

CMPLD2 - Timer Channel Comparator Load Register 2
#define	TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)

#define	TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

CSCTRL - Timer Channel Comparator Status and Control Register
#define	TMR_CSCTRL_CL1_MASK (0x3U)

#define	TMR_CSCTRL_CL1_SHIFT (0U)

#define	TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

#define	TMR_CSCTRL_CL2_MASK (0xCU)

#define	TMR_CSCTRL_CL2_SHIFT (2U)

#define	TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

#define	TMR_CSCTRL_TCF1_MASK (0x10U)

#define	TMR_CSCTRL_TCF1_SHIFT (4U)

#define	TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

#define	TMR_CSCTRL_TCF2_MASK (0x20U)

#define	TMR_CSCTRL_TCF2_SHIFT (5U)

#define	TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

#define	TMR_CSCTRL_TCF1EN_MASK (0x40U)

#define	TMR_CSCTRL_TCF1EN_SHIFT (6U)

#define	TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

#define	TMR_CSCTRL_TCF2EN_MASK (0x80U)

#define	TMR_CSCTRL_TCF2EN_SHIFT (7U)

#define	TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

#define	TMR_CSCTRL_UP_MASK (0x200U)

#define	TMR_CSCTRL_UP_SHIFT (9U)

#define	TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

#define	TMR_CSCTRL_TCI_MASK (0x400U)

#define	TMR_CSCTRL_TCI_SHIFT (10U)

#define	TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

#define	TMR_CSCTRL_ROC_MASK (0x800U)

#define	TMR_CSCTRL_ROC_SHIFT (11U)

#define	TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

#define	TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)

#define	TMR_CSCTRL_ALT_LOAD_SHIFT (12U)

#define	TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

#define	TMR_CSCTRL_FAULT_MASK (0x2000U)

#define	TMR_CSCTRL_FAULT_SHIFT (13U)

#define	TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

#define	TMR_CSCTRL_DBG_EN_MASK (0xC000U)

#define	TMR_CSCTRL_DBG_EN_SHIFT (14U)

#define	TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

FILT - Timer Channel Input Filter Register
#define	TMR_FILT_FILT_PER_MASK (0xFFU)

#define	TMR_FILT_FILT_PER_SHIFT (0U)

#define	TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

#define	TMR_FILT_FILT_CNT_MASK (0x700U)

#define	TMR_FILT_FILT_CNT_SHIFT (8U)

#define	TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

DMA - Timer Channel DMA Enable Register
#define	TMR_DMA_IEFDE_MASK (0x1U)

#define	TMR_DMA_IEFDE_SHIFT (0U)

#define	TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

#define	TMR_DMA_CMPLD1DE_MASK (0x2U)

#define	TMR_DMA_CMPLD1DE_SHIFT (1U)

#define	TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

#define	TMR_DMA_CMPLD2DE_MASK (0x4U)

#define	TMR_DMA_CMPLD2DE_SHIFT (2U)

#define	TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

ENBL - Timer Channel Enable Register
#define	TMR_ENBL_ENBL_MASK (0xFU)

#define	TMR_ENBL_ENBL_SHIFT (0U)

#define	TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

Detailed Description

Macro Definition Documentation

◆ TMR_CAPT_CAPTURE [1/3]

#define TMR_CAPT_CAPTURE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

CAPTURE - Capture Value

◆ TMR_CAPT_CAPTURE [2/3]

#define TMR_CAPT_CAPTURE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

CAPTURE - Capture Value

◆ TMR_CAPT_CAPTURE [3/3]

#define TMR_CAPT_CAPTURE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)

CAPTURE - Capture Value

◆ TMR_CMPLD1_COMPARATOR_LOAD_1 [1/2]

#define TMR_CMPLD1_COMPARATOR_LOAD_1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1

◆ TMR_CMPLD1_COMPARATOR_LOAD_1 [2/2]

#define TMR_CMPLD1_COMPARATOR_LOAD_1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)

COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1

◆ TMR_CMPLD2_COMPARATOR_LOAD_2 [1/2]

#define TMR_CMPLD2_COMPARATOR_LOAD_2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2

◆ TMR_CMPLD2_COMPARATOR_LOAD_2 [2/2]

#define TMR_CMPLD2_COMPARATOR_LOAD_2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)

COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2

◆ TMR_CNTR_COUNTER [1/2]

#define TMR_CNTR_COUNTER ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

COUNTER - COUNTER

◆ TMR_CNTR_COUNTER [2/2]

#define TMR_CNTR_COUNTER ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)

COUNTER - COUNTER

◆ TMR_COMP1_COMPARISON_1 [1/3]

#define TMR_COMP1_COMPARISON_1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMPARISON_1 - Comparison Value 1

◆ TMR_COMP1_COMPARISON_1 [2/3]

#define TMR_COMP1_COMPARISON_1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMPARISON_1 - Comparison Value 1

◆ TMR_COMP1_COMPARISON_1 [3/3]

#define TMR_COMP1_COMPARISON_1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)

COMPARISON_1 - Comparison Value 1

◆ TMR_COMP2_COMPARISON_2 [1/3]

#define TMR_COMP2_COMPARISON_2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

COMPARISON_2 - Comparison Value 2

◆ TMR_COMP2_COMPARISON_2 [2/3]

#define TMR_COMP2_COMPARISON_2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

COMPARISON_2 - Comparison Value 2

◆ TMR_COMP2_COMPARISON_2 [3/3]

#define TMR_COMP2_COMPARISON_2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)

COMPARISON_2 - Comparison Value 2

◆ TMR_CSCTRL_ALT_LOAD [1/3]

#define TMR_CSCTRL_ALT_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

ALT_LOAD - Alternative Load Enable 0b0..Counter can be re-initialized only with the LOAD register. 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.

◆ TMR_CSCTRL_ALT_LOAD [2/3]

#define TMR_CSCTRL_ALT_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

ALT_LOAD - Alternative Load Enable 0b0..Counter can be re-initialized only with the LOAD register. 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.

◆ TMR_CSCTRL_ALT_LOAD [3/3]

#define TMR_CSCTRL_ALT_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)

ALT_LOAD - Alternative Load Enable 0b0..Counter can be re-initialized only with the LOAD register. 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.

◆ TMR_CSCTRL_CL1 [1/3]

#define TMR_CSCTRL_CL1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

CL1 - Compare Load Control 1 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_CL1 [2/3]

#define TMR_CSCTRL_CL1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

CL1 - Compare Load Control 1 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_CL1 [3/3]

#define TMR_CSCTRL_CL1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)

CL1 - Compare Load Control 1 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_CL2 [1/3]

#define TMR_CSCTRL_CL2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

CL2 - Compare Load Control 2 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_CL2 [2/3]

#define TMR_CSCTRL_CL2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

CL2 - Compare Load Control 2 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_CL2 [3/3]

#define TMR_CSCTRL_CL2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)

CL2 - Compare Load Control 2 0b00..Never preload 0b01..Load upon successful compare with the value in COMP1 0b10..Load upon successful compare with the value in COMP2 0b11..Reserved

◆ TMR_CSCTRL_DBG_EN [1/3]

#define TMR_CSCTRL_DBG_EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

DBG_EN - Debug Actions Enable 0b00..Continue with normal operation during debug mode. (default) 0b01..Halt TMR counter during debug mode. 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0b11..Both halt counter and force output to 0 during debug mode.

◆ TMR_CSCTRL_DBG_EN [2/3]

#define TMR_CSCTRL_DBG_EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

DBG_EN - Debug Actions Enable 0b00..Continue with normal operation during debug mode. (default) 0b01..Halt TMR counter during debug mode. 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0b11..Both halt counter and force output to 0 during debug mode.

◆ TMR_CSCTRL_DBG_EN [3/3]

#define TMR_CSCTRL_DBG_EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)

DBG_EN - Debug Actions Enable 0b00..Continue with normal operation during debug mode. (default) 0b01..Halt TMR counter during debug mode. 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 0b11..Both halt counter and force output to 0 during debug mode.

◆ TMR_CSCTRL_FAULT [1/3]

#define TMR_CSCTRL_FAULT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

FAULT - Fault Enable 0b0..Fault function disabled. 0b1..Fault function enabled.

◆ TMR_CSCTRL_FAULT [2/3]

#define TMR_CSCTRL_FAULT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

FAULT - Fault Enable 0b0..Fault function disabled. 0b1..Fault function enabled.

◆ TMR_CSCTRL_FAULT [3/3]

#define TMR_CSCTRL_FAULT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)

FAULT - Fault Enable 0b0..Fault function disabled. 0b1..Fault function enabled.

◆ TMR_CSCTRL_ROC [1/3]

#define TMR_CSCTRL_ROC ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

ROC - Reload on Capture 0b0..Do not reload the counter on a capture event. 0b1..Reload the counter on a capture event.

◆ TMR_CSCTRL_ROC [2/3]

#define TMR_CSCTRL_ROC ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

ROC - Reload on Capture 0b0..Do not reload the counter on a capture event. 0b1..Reload the counter on a capture event.

◆ TMR_CSCTRL_ROC [3/3]

#define TMR_CSCTRL_ROC ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)

ROC - Reload on Capture 0b0..Do not reload the counter on a capture event. 0b1..Reload the counter on a capture event.

◆ TMR_CSCTRL_TCF1 [1/3]

#define TMR_CSCTRL_TCF1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

TCF1 - Timer Compare 1 Interrupt Flag

◆ TMR_CSCTRL_TCF1 [2/3]

#define TMR_CSCTRL_TCF1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

TCF1 - Timer Compare 1 Interrupt Flag

◆ TMR_CSCTRL_TCF1 [3/3]

#define TMR_CSCTRL_TCF1 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)

TCF1 - Timer Compare 1 Interrupt Flag

◆ TMR_CSCTRL_TCF1EN [1/3]

#define TMR_CSCTRL_TCF1EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

TCF1EN - Timer Compare 1 Interrupt Enable

◆ TMR_CSCTRL_TCF1EN [2/3]

#define TMR_CSCTRL_TCF1EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

TCF1EN - Timer Compare 1 Interrupt Enable

◆ TMR_CSCTRL_TCF1EN [3/3]

#define TMR_CSCTRL_TCF1EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)

TCF1EN - Timer Compare 1 Interrupt Enable

◆ TMR_CSCTRL_TCF2 [1/3]

#define TMR_CSCTRL_TCF2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

TCF2 - Timer Compare 2 Interrupt Flag

◆ TMR_CSCTRL_TCF2 [2/3]

#define TMR_CSCTRL_TCF2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

TCF2 - Timer Compare 2 Interrupt Flag

◆ TMR_CSCTRL_TCF2 [3/3]

#define TMR_CSCTRL_TCF2 ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)

TCF2 - Timer Compare 2 Interrupt Flag

◆ TMR_CSCTRL_TCF2EN [1/3]

#define TMR_CSCTRL_TCF2EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

TCF2EN - Timer Compare 2 Interrupt Enable

◆ TMR_CSCTRL_TCF2EN [2/3]

#define TMR_CSCTRL_TCF2EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

TCF2EN - Timer Compare 2 Interrupt Enable

◆ TMR_CSCTRL_TCF2EN [3/3]

#define TMR_CSCTRL_TCF2EN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)

TCF2EN - Timer Compare 2 Interrupt Enable

◆ TMR_CSCTRL_TCI [1/3]

#define TMR_CSCTRL_TCI ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

TCI - Triggered Count Initialization Control 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.

◆ TMR_CSCTRL_TCI [2/3]

#define TMR_CSCTRL_TCI ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

TCI - Triggered Count Initialization Control 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.

◆ TMR_CSCTRL_TCI [3/3]

#define TMR_CSCTRL_TCI ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)

TCI - Triggered Count Initialization Control 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.

◆ TMR_CSCTRL_UP [1/3]

#define TMR_CSCTRL_UP ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

UP - Counting Direction Indicator 0b0..The last count was in the DOWN direction. 0b1..The last count was in the UP direction.

◆ TMR_CSCTRL_UP [2/3]

#define TMR_CSCTRL_UP ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

UP - Counting Direction Indicator 0b0..The last count was in the DOWN direction. 0b1..The last count was in the UP direction.

◆ TMR_CSCTRL_UP [3/3]

#define TMR_CSCTRL_UP ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)

UP - Counting Direction Indicator 0b0..The last count was in the DOWN direction. 0b1..The last count was in the UP direction.

◆ TMR_CTRL_CM [1/3]

#define TMR_CTRL_CM ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

CM - Count Mode 0b000..No operation 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0b011..Count rising edges of primary source while secondary input high active 0b100..Quadrature count mode, uses primary and secondary sources 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0b110..Edge of secondary source triggers primary count until compare 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.

◆ TMR_CTRL_CM [2/3]

#define TMR_CTRL_CM ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

CM - Count Mode 0b000..No operation 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0b011..Count rising edges of primary source while secondary input high active 0b100..Quadrature count mode, uses primary and secondary sources 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0b110..Edge of secondary source triggers primary count until compare 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.

◆ TMR_CTRL_CM [3/3]

#define TMR_CTRL_CM ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)

CM - Count Mode 0b000..No operation 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 0b011..Count rising edges of primary source while secondary input high active 0b100..Quadrature count mode, uses primary and secondary sources 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 0b110..Edge of secondary source triggers primary count until compare 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.

◆ TMR_CTRL_COINIT [1/3]

#define TMR_CTRL_COINIT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

COINIT - Co-Channel Initialization 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer

◆ TMR_CTRL_COINIT [2/3]

#define TMR_CTRL_COINIT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

COINIT - Co-Channel Initialization 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer

◆ TMR_CTRL_COINIT [3/3]

#define TMR_CTRL_COINIT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)

COINIT - Co-Channel Initialization 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer

◆ TMR_CTRL_DIR [1/3]

#define TMR_CTRL_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

DIR - Count Direction 0b0..Count up. 0b1..Count down.

◆ TMR_CTRL_DIR [2/3]

#define TMR_CTRL_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

DIR - Count Direction 0b0..Count up. 0b1..Count down.

◆ TMR_CTRL_DIR [3/3]

#define TMR_CTRL_DIR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)

DIR - Count Direction 0b0..Count up. 0b1..Count down.

◆ TMR_CTRL_LENGTH [1/3]

#define TMR_CTRL_LENGTH ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

LENGTH - Count Length 0b0..Count until roll over at $FFFF and continue from $0000. 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.

◆ TMR_CTRL_LENGTH [2/3]

#define TMR_CTRL_LENGTH ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

LENGTH - Count Length 0b0..Count until roll over at $FFFF and continue from $0000. 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.

◆ TMR_CTRL_LENGTH [3/3]

#define TMR_CTRL_LENGTH ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)

LENGTH - Count Length 0b0..Count until roll over at $FFFF and continue from $0000. 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.

◆ TMR_CTRL_ONCE [1/3]

#define TMR_CTRL_ONCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

ONCE - Count Once 0b0..Count repeatedly. 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.

◆ TMR_CTRL_ONCE [2/3]

#define TMR_CTRL_ONCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

ONCE - Count Once 0b0..Count repeatedly. 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.

◆ TMR_CTRL_ONCE [3/3]

#define TMR_CTRL_ONCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)

ONCE - Count Once 0b0..Count repeatedly. 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.

◆ TMR_CTRL_OUTMODE [1/3]

#define TMR_CTRL_OUTMODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

OUTMODE - Output Mode 0b000..Asserted while counter is active 0b001..Clear OFLAG output on successful compare 0b010..Set OFLAG output on successful compare 0b011..Toggle OFLAG output on successful compare 0b100..Toggle OFLAG output using alternating compare registers 0b101..Set on compare, cleared on secondary source input edge 0b110..Set on compare, cleared on counter rollover 0b111..Enable gated clock output while counter is active

◆ TMR_CTRL_OUTMODE [2/3]

#define TMR_CTRL_OUTMODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

OUTMODE - Output Mode 0b000..Asserted while counter is active 0b001..Clear OFLAG output on successful compare 0b010..Set OFLAG output on successful compare 0b011..Toggle OFLAG output on successful compare 0b100..Toggle OFLAG output using alternating compare registers 0b101..Set on compare, cleared on secondary source input edge 0b110..Set on compare, cleared on counter rollover 0b111..Enable gated clock output while counter is active

◆ TMR_CTRL_OUTMODE [3/3]

#define TMR_CTRL_OUTMODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)

OUTMODE - Output Mode 0b000..Asserted while counter is active 0b001..Clear OFLAG output on successful compare 0b010..Set OFLAG output on successful compare 0b011..Toggle OFLAG output on successful compare 0b100..Toggle OFLAG output using alternating compare registers 0b101..Set on compare, cleared on secondary source input edge 0b110..Set on compare, cleared on counter rollover 0b111..Enable gated clock output while counter is active

◆ TMR_CTRL_PCS [1/3]

#define TMR_CTRL_PCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

PCS - Primary Count Source 0b0000..Counter 0 input pin 0b0001..Counter 1 input pin 0b0010..Counter 2 input pin 0b0011..Counter 3 input pin 0b0100..Counter 0 output 0b0101..Counter 1 output 0b0110..Counter 2 output 0b0111..Counter 3 output 0b1000..IP bus clock divide by 1 prescaler 0b1001..IP bus clock divide by 2 prescaler 0b1010..IP bus clock divide by 4 prescaler 0b1011..IP bus clock divide by 8 prescaler 0b1100..IP bus clock divide by 16 prescaler 0b1101..IP bus clock divide by 32 prescaler 0b1110..IP bus clock divide by 64 prescaler 0b1111..IP bus clock divide by 128 prescaler

◆ TMR_CTRL_PCS [2/3]

#define TMR_CTRL_PCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

PCS - Primary Count Source 0b0000..Counter 0 input pin 0b0001..Counter 1 input pin 0b0010..Counter 2 input pin 0b0011..Counter 3 input pin 0b0100..Counter 0 output 0b0101..Counter 1 output 0b0110..Counter 2 output 0b0111..Counter 3 output 0b1000..IP bus clock divide by 1 prescaler 0b1001..IP bus clock divide by 2 prescaler 0b1010..IP bus clock divide by 4 prescaler 0b1011..IP bus clock divide by 8 prescaler 0b1100..IP bus clock divide by 16 prescaler 0b1101..IP bus clock divide by 32 prescaler 0b1110..IP bus clock divide by 64 prescaler 0b1111..IP bus clock divide by 128 prescaler

◆ TMR_CTRL_PCS [3/3]

#define TMR_CTRL_PCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)

PCS - Primary Count Source 0b0000..Counter 0 input pin 0b0001..Counter 1 input pin 0b0010..Counter 2 input pin 0b0011..Counter 3 input pin 0b0100..Counter 0 output 0b0101..Counter 1 output 0b0110..Counter 2 output 0b0111..Counter 3 output 0b1000..IP bus clock divide by 1 prescaler 0b1001..IP bus clock divide by 2 prescaler 0b1010..IP bus clock divide by 4 prescaler 0b1011..IP bus clock divide by 8 prescaler 0b1100..IP bus clock divide by 16 prescaler 0b1101..IP bus clock divide by 32 prescaler 0b1110..IP bus clock divide by 64 prescaler 0b1111..IP bus clock divide by 128 prescaler

◆ TMR_CTRL_SCS [1/3]

#define TMR_CTRL_SCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

SCS - Secondary Count Source 0b00..Counter 0 input pin 0b01..Counter 1 input pin 0b10..Counter 2 input pin 0b11..Counter 3 input pin

◆ TMR_CTRL_SCS [2/3]

#define TMR_CTRL_SCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

SCS - Secondary Count Source 0b00..Counter 0 input pin 0b01..Counter 1 input pin 0b10..Counter 2 input pin 0b11..Counter 3 input pin

◆ TMR_CTRL_SCS [3/3]

#define TMR_CTRL_SCS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)

SCS - Secondary Count Source 0b00..Counter 0 input pin 0b01..Counter 1 input pin 0b10..Counter 2 input pin 0b11..Counter 3 input pin

◆ TMR_DMA_CMPLD1DE [1/3]

#define TMR_DMA_CMPLD1DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

CMPLD1DE - Comparator Preload Register 1 DMA Enable

◆ TMR_DMA_CMPLD1DE [2/3]

#define TMR_DMA_CMPLD1DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

CMPLD1DE - Comparator Preload Register 1 DMA Enable

◆ TMR_DMA_CMPLD1DE [3/3]

#define TMR_DMA_CMPLD1DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)

CMPLD1DE - Comparator Preload Register 1 DMA Enable

◆ TMR_DMA_CMPLD2DE [1/3]

#define TMR_DMA_CMPLD2DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

CMPLD2DE - Comparator Preload Register 2 DMA Enable

◆ TMR_DMA_CMPLD2DE [2/3]

#define TMR_DMA_CMPLD2DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

CMPLD2DE - Comparator Preload Register 2 DMA Enable

◆ TMR_DMA_CMPLD2DE [3/3]

#define TMR_DMA_CMPLD2DE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)

CMPLD2DE - Comparator Preload Register 2 DMA Enable

◆ TMR_DMA_IEFDE [1/3]

#define TMR_DMA_IEFDE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

IEFDE - Input Edge Flag DMA Enable

◆ TMR_DMA_IEFDE [2/3]

#define TMR_DMA_IEFDE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

IEFDE - Input Edge Flag DMA Enable

◆ TMR_DMA_IEFDE [3/3]

#define TMR_DMA_IEFDE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)

IEFDE - Input Edge Flag DMA Enable

◆ TMR_ENBL_ENBL [1/3]

#define TMR_ENBL_ENBL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

ENBL - Timer Channel Enable 0b0000..Timer channel is disabled. 0b0001..Timer channel is enabled. (default)

◆ TMR_ENBL_ENBL [2/3]

#define TMR_ENBL_ENBL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

ENBL - Timer Channel Enable 0b0000..Timer channel is disabled. 0b0001..Timer channel is enabled. (default)

◆ TMR_ENBL_ENBL [3/3]

#define TMR_ENBL_ENBL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)

ENBL - Timer Channel Enable 0b0000..Timer channel is disabled. 0b0001..Timer channel is enabled. (default)

◆ TMR_FILT_FILT_CNT [1/3]

#define TMR_FILT_FILT_CNT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

◆ TMR_FILT_FILT_CNT [2/3]

#define TMR_FILT_FILT_CNT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

◆ TMR_FILT_FILT_CNT [3/3]

#define TMR_FILT_FILT_CNT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)

FILT_CNT - Input Filter Sample Count

◆ TMR_FILT_FILT_PER [1/3]

#define TMR_FILT_FILT_PER ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

◆ TMR_FILT_FILT_PER [2/3]

#define TMR_FILT_FILT_PER ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

◆ TMR_FILT_FILT_PER [3/3]

#define TMR_FILT_FILT_PER ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)

FILT_PER - Input Filter Sample Period

◆ TMR_HOLD_HOLD [1/2]

#define TMR_HOLD_HOLD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

HOLD - HOLD

◆ TMR_HOLD_HOLD [2/2]

#define TMR_HOLD_HOLD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)

HOLD - HOLD

◆ TMR_LOAD_LOAD [1/3]

#define TMR_LOAD_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

LOAD - Timer Load Register

◆ TMR_LOAD_LOAD [2/3]

#define TMR_LOAD_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

LOAD - Timer Load Register

◆ TMR_LOAD_LOAD [3/3]

#define TMR_LOAD_LOAD ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)

LOAD - Timer Load Register

◆ TMR_SCTRL_CAPTURE_MODE [1/3]

#define TMR_SCTRL_CAPTURE_MODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

CAPTURE_MODE - Input Capture Mode 0b00..Capture function is disabled 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0b11..Load capture register on both edges of input

◆ TMR_SCTRL_CAPTURE_MODE [2/3]

#define TMR_SCTRL_CAPTURE_MODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

CAPTURE_MODE - Input Capture Mode 0b00..Capture function is disabled 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0b11..Load capture register on both edges of input

◆ TMR_SCTRL_CAPTURE_MODE [3/3]

#define TMR_SCTRL_CAPTURE_MODE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)

CAPTURE_MODE - Input Capture Mode 0b00..Capture function is disabled 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 0b11..Load capture register on both edges of input

◆ TMR_SCTRL_EEOF [1/3]

#define TMR_SCTRL_EEOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

EEOF - Enable External OFLAG Force

◆ TMR_SCTRL_EEOF [2/3]

#define TMR_SCTRL_EEOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

EEOF - Enable External OFLAG Force

◆ TMR_SCTRL_EEOF [3/3]

#define TMR_SCTRL_EEOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)

EEOF - Enable External OFLAG Force

◆ TMR_SCTRL_FORCE [1/3]

#define TMR_SCTRL_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

FORCE - Force OFLAG Output

◆ TMR_SCTRL_FORCE [2/3]

#define TMR_SCTRL_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

FORCE - Force OFLAG Output

◆ TMR_SCTRL_FORCE [3/3]

#define TMR_SCTRL_FORCE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)

FORCE - Force OFLAG Output

◆ TMR_SCTRL_IEF [1/3]

#define TMR_SCTRL_IEF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

IEF - Input Edge Flag

◆ TMR_SCTRL_IEF [2/3]

#define TMR_SCTRL_IEF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

IEF - Input Edge Flag

◆ TMR_SCTRL_IEF [3/3]

#define TMR_SCTRL_IEF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)

IEF - Input Edge Flag

◆ TMR_SCTRL_IEFIE [1/3]

#define TMR_SCTRL_IEFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

IEFIE - Input Edge Flag Interrupt Enable

◆ TMR_SCTRL_IEFIE [2/3]

#define TMR_SCTRL_IEFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

IEFIE - Input Edge Flag Interrupt Enable

◆ TMR_SCTRL_IEFIE [3/3]

#define TMR_SCTRL_IEFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)

IEFIE - Input Edge Flag Interrupt Enable

◆ TMR_SCTRL_INPUT [1/3]

#define TMR_SCTRL_INPUT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

INPUT - External Input Signal

◆ TMR_SCTRL_INPUT [2/3]

#define TMR_SCTRL_INPUT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

INPUT - External Input Signal

◆ TMR_SCTRL_INPUT [3/3]

#define TMR_SCTRL_INPUT ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)

INPUT - External Input Signal

◆ TMR_SCTRL_IPS [1/3]

#define TMR_SCTRL_IPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

IPS - Input Polarity Select

◆ TMR_SCTRL_IPS [2/3]

#define TMR_SCTRL_IPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

IPS - Input Polarity Select

◆ TMR_SCTRL_IPS [3/3]

#define TMR_SCTRL_IPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)

IPS - Input Polarity Select

◆ TMR_SCTRL_MSTR [1/3]

#define TMR_SCTRL_MSTR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

MSTR - Master Mode

◆ TMR_SCTRL_MSTR [2/3]

#define TMR_SCTRL_MSTR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

MSTR - Master Mode

◆ TMR_SCTRL_MSTR [3/3]

#define TMR_SCTRL_MSTR ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)

MSTR - Master Mode

◆ TMR_SCTRL_OEN [1/3]

#define TMR_SCTRL_OEN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

OEN - Output Enable 0b0..The external pin is configured as an input. 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.

◆ TMR_SCTRL_OEN [2/3]

#define TMR_SCTRL_OEN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

OEN - Output Enable 0b0..The external pin is configured as an input. 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.

◆ TMR_SCTRL_OEN [3/3]

#define TMR_SCTRL_OEN ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)

OEN - Output Enable 0b0..The external pin is configured as an input. 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.

◆ TMR_SCTRL_OPS [1/3]

#define TMR_SCTRL_OPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

OPS - Output Polarity Select 0b0..True polarity. 0b1..Inverted polarity.

◆ TMR_SCTRL_OPS [2/3]

#define TMR_SCTRL_OPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

OPS - Output Polarity Select 0b0..True polarity. 0b1..Inverted polarity.

◆ TMR_SCTRL_OPS [3/3]

#define TMR_SCTRL_OPS ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)

OPS - Output Polarity Select 0b0..True polarity. 0b1..Inverted polarity.

◆ TMR_SCTRL_TCF [1/3]

#define TMR_SCTRL_TCF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

TCF - Timer Compare Flag

◆ TMR_SCTRL_TCF [2/3]

#define TMR_SCTRL_TCF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

TCF - Timer Compare Flag

◆ TMR_SCTRL_TCF [3/3]

#define TMR_SCTRL_TCF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)

TCF - Timer Compare Flag

◆ TMR_SCTRL_TCFIE [1/3]

#define TMR_SCTRL_TCFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

TCFIE - Timer Compare Flag Interrupt Enable

◆ TMR_SCTRL_TCFIE [2/3]

#define TMR_SCTRL_TCFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

TCFIE - Timer Compare Flag Interrupt Enable

◆ TMR_SCTRL_TCFIE [3/3]

#define TMR_SCTRL_TCFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)

TCFIE - Timer Compare Flag Interrupt Enable

◆ TMR_SCTRL_TOF [1/3]

#define TMR_SCTRL_TOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

TOF - Timer Overflow Flag

◆ TMR_SCTRL_TOF [2/3]

#define TMR_SCTRL_TOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

TOF - Timer Overflow Flag

◆ TMR_SCTRL_TOF [3/3]

#define TMR_SCTRL_TOF ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)

TOF - Timer Overflow Flag

◆ TMR_SCTRL_TOFIE [1/3]

#define TMR_SCTRL_TOFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

TOFIE - Timer Overflow Flag Interrupt Enable

◆ TMR_SCTRL_TOFIE [2/3]

#define TMR_SCTRL_TOFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

TOFIE - Timer Overflow Flag Interrupt Enable

◆ TMR_SCTRL_TOFIE [3/3]

#define TMR_SCTRL_TOFIE ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)

TOFIE - Timer Overflow Flag Interrupt Enable

◆ TMR_SCTRL_VAL [1/3]

#define TMR_SCTRL_VAL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

VAL - Forced OFLAG Value

◆ TMR_SCTRL_VAL [2/3]

#define TMR_SCTRL_VAL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

VAL - Forced OFLAG Value

◆ TMR_SCTRL_VAL [3/3]

#define TMR_SCTRL_VAL ( x ) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)

VAL - Forced OFLAG Value

Macros

COMP1 - Timer Channel Compare Register 1

COMP2 - Timer Channel Compare Register 2

CAPT - Timer Channel Capture Register

LOAD - Timer Channel Load Register

HOLD - Timer Channel Hold Register

CNTR - Timer Channel Counter Register

CTRL - Timer Channel Control Register

SCTRL - Timer Channel Status and Control Register

CMPLD1 - Timer Channel Comparator Load Register 1

CMPLD2 - Timer Channel Comparator Load Register 2

CSCTRL - Timer Channel Comparator Status and Control Register

FILT - Timer Channel Input Filter Register

DMA - Timer Channel DMA Enable Register

ENBL - Timer Channel Enable Register

COMP1 - Timer Channel Compare Register 1

COMP2 - Timer Channel Compare Register 2

CAPT - Timer Channel Capture Register

LOAD - Timer Channel Load Register

HOLD - Timer Channel Hold Register

CNTR - Timer Channel Counter Register

CTRL - Timer Channel Control Register

SCTRL - Timer Channel Status and Control Register

CMPLD1 - Timer Channel Comparator Load Register 1

CMPLD2 - Timer Channel Comparator Load Register 2

CSCTRL - Timer Channel Comparator Status and Control Register

FILT - Timer Channel Input Filter Register

DMA - Timer Channel DMA Enable Register

ENBL - Timer Channel Enable Register

COMP1 - Timer Channel Compare Register 1

COMP2 - Timer Channel Compare Register 2

CAPT - Timer Channel Capture Register

LOAD - Timer Channel Load Register

HOLD - Timer Channel Hold Register

CNTR - Timer Channel Counter Register

CTRL - Timer Channel Control Register

SCTRL - Timer Channel Status and Control Register

CMPLD1 - Timer Channel Comparator Load Register 1

CMPLD2 - Timer Channel Comparator Load Register 2

CSCTRL - Timer Channel Comparator Status and Control Register

FILT - Timer Channel Input Filter Register

DMA - Timer Channel DMA Enable Register

ENBL - Timer Channel Enable Register

Detailed Description

Macro Definition Documentation

◆ TMR_CAPT_CAPTURE [1/3]

◆ TMR_CAPT_CAPTURE [2/3]

◆ TMR_CAPT_CAPTURE [3/3]

◆ TMR_CMPLD1_COMPARATOR_LOAD_1 [1/2]

◆ TMR_CMPLD1_COMPARATOR_LOAD_1 [2/2]

◆ TMR_CMPLD2_COMPARATOR_LOAD_2 [1/2]

◆ TMR_CMPLD2_COMPARATOR_LOAD_2 [2/2]

◆ TMR_CNTR_COUNTER [1/2]

◆ TMR_CNTR_COUNTER [2/2]

◆ TMR_COMP1_COMPARISON_1 [1/3]

◆ TMR_COMP1_COMPARISON_1 [2/3]

◆ TMR_COMP1_COMPARISON_1 [3/3]

◆ TMR_COMP2_COMPARISON_2 [1/3]

◆ TMR_COMP2_COMPARISON_2 [2/3]

◆ TMR_COMP2_COMPARISON_2 [3/3]

◆ TMR_CSCTRL_ALT_LOAD [1/3]

◆ TMR_CSCTRL_ALT_LOAD [2/3]

◆ TMR_CSCTRL_ALT_LOAD [3/3]

◆ TMR_CSCTRL_CL1 [1/3]

◆ TMR_CSCTRL_CL1 [2/3]

◆ TMR_CSCTRL_CL1 [3/3]

◆ TMR_CSCTRL_CL2 [1/3]

◆ TMR_CSCTRL_CL2 [2/3]

◆ TMR_CSCTRL_CL2 [3/3]

◆ TMR_CSCTRL_DBG_EN [1/3]

◆ TMR_CSCTRL_DBG_EN [2/3]

◆ TMR_CSCTRL_DBG_EN [3/3]

◆ TMR_CSCTRL_FAULT [1/3]

◆ TMR_CSCTRL_FAULT [2/3]

◆ TMR_CSCTRL_FAULT [3/3]

◆ TMR_CSCTRL_ROC [1/3]

◆ TMR_CSCTRL_ROC [2/3]

◆ TMR_CSCTRL_ROC [3/3]

◆ TMR_CSCTRL_TCF1 [1/3]

◆ TMR_CSCTRL_TCF1 [2/3]