Macros
#define	SEMA4_GATE_COUNT (16U)

#define	SEMA4_CPINE_COUNT (2U)

#define	SEMA4_CPNTF_COUNT (2U)

#define	SEMA4_GATE_COUNT (16U)

#define	SEMA4_CPINE_COUNT (2U)

#define	SEMA4_CPNTF_COUNT (2U)

GATE - Semaphores Gate n Register
#define	SEMA4_GATE_GTFSM_MASK (0x3U)

#define	SEMA4_GATE_GTFSM_SHIFT (0U)

#define	SEMA4_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)

CPINE - Semaphores Processor n IRQ Notification Enable
#define	SEMA4_CPINE_INE7_MASK (0x1U)

#define	SEMA4_CPINE_INE7_SHIFT (0U)

#define	SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)

#define	SEMA4_CPINE_INE6_MASK (0x2U)

#define	SEMA4_CPINE_INE6_SHIFT (1U)

#define	SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)

#define	SEMA4_CPINE_INE5_MASK (0x4U)

#define	SEMA4_CPINE_INE5_SHIFT (2U)

#define	SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)

#define	SEMA4_CPINE_INE4_MASK (0x8U)

#define	SEMA4_CPINE_INE4_SHIFT (3U)

#define	SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)

#define	SEMA4_CPINE_INE3_MASK (0x10U)

#define	SEMA4_CPINE_INE3_SHIFT (4U)

#define	SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)

#define	SEMA4_CPINE_INE2_MASK (0x20U)

#define	SEMA4_CPINE_INE2_SHIFT (5U)

#define	SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)

#define	SEMA4_CPINE_INE1_MASK (0x40U)

#define	SEMA4_CPINE_INE1_SHIFT (6U)

#define	SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)

#define	SEMA4_CPINE_INE0_MASK (0x80U)

#define	SEMA4_CPINE_INE0_SHIFT (7U)

#define	SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)

#define	SEMA4_CPINE_INE15_MASK (0x100U)

#define	SEMA4_CPINE_INE15_SHIFT (8U)

#define	SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)

#define	SEMA4_CPINE_INE14_MASK (0x200U)

#define	SEMA4_CPINE_INE14_SHIFT (9U)

#define	SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)

#define	SEMA4_CPINE_INE13_MASK (0x400U)

#define	SEMA4_CPINE_INE13_SHIFT (10U)

#define	SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)

#define	SEMA4_CPINE_INE12_MASK (0x800U)

#define	SEMA4_CPINE_INE12_SHIFT (11U)

#define	SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)

#define	SEMA4_CPINE_INE11_MASK (0x1000U)

#define	SEMA4_CPINE_INE11_SHIFT (12U)

#define	SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)

#define	SEMA4_CPINE_INE10_MASK (0x2000U)

#define	SEMA4_CPINE_INE10_SHIFT (13U)

#define	SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)

#define	SEMA4_CPINE_INE9_MASK (0x4000U)

#define	SEMA4_CPINE_INE9_SHIFT (14U)

#define	SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)

#define	SEMA4_CPINE_INE8_MASK (0x8000U)

#define	SEMA4_CPINE_INE8_SHIFT (15U)

#define	SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)

CPNTF - Semaphores Processor n IRQ Notification
#define	SEMA4_CPNTF_GN7_MASK (0x1U)

#define	SEMA4_CPNTF_GN7_SHIFT (0U)

#define	SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)

#define	SEMA4_CPNTF_GN6_MASK (0x2U)

#define	SEMA4_CPNTF_GN6_SHIFT (1U)

#define	SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)

#define	SEMA4_CPNTF_GN5_MASK (0x4U)

#define	SEMA4_CPNTF_GN5_SHIFT (2U)

#define	SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)

#define	SEMA4_CPNTF_GN4_MASK (0x8U)

#define	SEMA4_CPNTF_GN4_SHIFT (3U)

#define	SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)

#define	SEMA4_CPNTF_GN3_MASK (0x10U)

#define	SEMA4_CPNTF_GN3_SHIFT (4U)

#define	SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)

#define	SEMA4_CPNTF_GN2_MASK (0x20U)

#define	SEMA4_CPNTF_GN2_SHIFT (5U)

#define	SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)

#define	SEMA4_CPNTF_GN1_MASK (0x40U)

#define	SEMA4_CPNTF_GN1_SHIFT (6U)

#define	SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)

#define	SEMA4_CPNTF_GN0_MASK (0x80U)

#define	SEMA4_CPNTF_GN0_SHIFT (7U)

#define	SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)

#define	SEMA4_CPNTF_GN15_MASK (0x100U)

#define	SEMA4_CPNTF_GN15_SHIFT (8U)

#define	SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)

#define	SEMA4_CPNTF_GN14_MASK (0x200U)

#define	SEMA4_CPNTF_GN14_SHIFT (9U)

#define	SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)

#define	SEMA4_CPNTF_GN13_MASK (0x400U)

#define	SEMA4_CPNTF_GN13_SHIFT (10U)

#define	SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)

#define	SEMA4_CPNTF_GN12_MASK (0x800U)

#define	SEMA4_CPNTF_GN12_SHIFT (11U)

#define	SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)

#define	SEMA4_CPNTF_GN11_MASK (0x1000U)

#define	SEMA4_CPNTF_GN11_SHIFT (12U)

#define	SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)

#define	SEMA4_CPNTF_GN10_MASK (0x2000U)

#define	SEMA4_CPNTF_GN10_SHIFT (13U)

#define	SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)

#define	SEMA4_CPNTF_GN9_MASK (0x4000U)

#define	SEMA4_CPNTF_GN9_SHIFT (14U)

#define	SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)

#define	SEMA4_CPNTF_GN8_MASK (0x8000U)

#define	SEMA4_CPNTF_GN8_SHIFT (15U)

#define	SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)

RSTGT - Semaphores (Secure) Reset Gate n
#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)

#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)

#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)

#define	SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)

#define	SEMA4_RSTGT_RSTGTN_SHIFT (8U)

#define	SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)

RSTNTF - Semaphores (Secure) Reset IRQ Notification
#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)

#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)

#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)

#define	SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)

#define	SEMA4_RSTNTF_RSTNTN_SHIFT (8U)

#define	SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)

GATE - Semaphores Gate n Register
#define	SEMA4_GATE_GTFSM_MASK (0x3U)

#define	SEMA4_GATE_GTFSM_SHIFT (0U)

#define	SEMA4_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)

CPINE - Semaphores Processor n IRQ Notification Enable
#define	SEMA4_CPINE_INE7_MASK (0x1U)

#define	SEMA4_CPINE_INE7_SHIFT (0U)

#define	SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)

#define	SEMA4_CPINE_INE6_MASK (0x2U)

#define	SEMA4_CPINE_INE6_SHIFT (1U)

#define	SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)

#define	SEMA4_CPINE_INE5_MASK (0x4U)

#define	SEMA4_CPINE_INE5_SHIFT (2U)

#define	SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)

#define	SEMA4_CPINE_INE4_MASK (0x8U)

#define	SEMA4_CPINE_INE4_SHIFT (3U)

#define	SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)

#define	SEMA4_CPINE_INE3_MASK (0x10U)

#define	SEMA4_CPINE_INE3_SHIFT (4U)

#define	SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)

#define	SEMA4_CPINE_INE2_MASK (0x20U)

#define	SEMA4_CPINE_INE2_SHIFT (5U)

#define	SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)

#define	SEMA4_CPINE_INE1_MASK (0x40U)

#define	SEMA4_CPINE_INE1_SHIFT (6U)

#define	SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)

#define	SEMA4_CPINE_INE0_MASK (0x80U)

#define	SEMA4_CPINE_INE0_SHIFT (7U)

#define	SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)

#define	SEMA4_CPINE_INE15_MASK (0x100U)

#define	SEMA4_CPINE_INE15_SHIFT (8U)

#define	SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)

#define	SEMA4_CPINE_INE14_MASK (0x200U)

#define	SEMA4_CPINE_INE14_SHIFT (9U)

#define	SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)

#define	SEMA4_CPINE_INE13_MASK (0x400U)

#define	SEMA4_CPINE_INE13_SHIFT (10U)

#define	SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)

#define	SEMA4_CPINE_INE12_MASK (0x800U)

#define	SEMA4_CPINE_INE12_SHIFT (11U)

#define	SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)

#define	SEMA4_CPINE_INE11_MASK (0x1000U)

#define	SEMA4_CPINE_INE11_SHIFT (12U)

#define	SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)

#define	SEMA4_CPINE_INE10_MASK (0x2000U)

#define	SEMA4_CPINE_INE10_SHIFT (13U)

#define	SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)

#define	SEMA4_CPINE_INE9_MASK (0x4000U)

#define	SEMA4_CPINE_INE9_SHIFT (14U)

#define	SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)

#define	SEMA4_CPINE_INE8_MASK (0x8000U)

#define	SEMA4_CPINE_INE8_SHIFT (15U)

#define	SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)

CPNTF - Semaphores Processor n IRQ Notification
#define	SEMA4_CPNTF_GN7_MASK (0x1U)

#define	SEMA4_CPNTF_GN7_SHIFT (0U)

#define	SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)

#define	SEMA4_CPNTF_GN6_MASK (0x2U)

#define	SEMA4_CPNTF_GN6_SHIFT (1U)

#define	SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)

#define	SEMA4_CPNTF_GN5_MASK (0x4U)

#define	SEMA4_CPNTF_GN5_SHIFT (2U)

#define	SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)

#define	SEMA4_CPNTF_GN4_MASK (0x8U)

#define	SEMA4_CPNTF_GN4_SHIFT (3U)

#define	SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)

#define	SEMA4_CPNTF_GN3_MASK (0x10U)

#define	SEMA4_CPNTF_GN3_SHIFT (4U)

#define	SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)

#define	SEMA4_CPNTF_GN2_MASK (0x20U)

#define	SEMA4_CPNTF_GN2_SHIFT (5U)

#define	SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)

#define	SEMA4_CPNTF_GN1_MASK (0x40U)

#define	SEMA4_CPNTF_GN1_SHIFT (6U)

#define	SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)

#define	SEMA4_CPNTF_GN0_MASK (0x80U)

#define	SEMA4_CPNTF_GN0_SHIFT (7U)

#define	SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)

#define	SEMA4_CPNTF_GN15_MASK (0x100U)

#define	SEMA4_CPNTF_GN15_SHIFT (8U)

#define	SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)

#define	SEMA4_CPNTF_GN14_MASK (0x200U)

#define	SEMA4_CPNTF_GN14_SHIFT (9U)

#define	SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)

#define	SEMA4_CPNTF_GN13_MASK (0x400U)

#define	SEMA4_CPNTF_GN13_SHIFT (10U)

#define	SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)

#define	SEMA4_CPNTF_GN12_MASK (0x800U)

#define	SEMA4_CPNTF_GN12_SHIFT (11U)

#define	SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)

#define	SEMA4_CPNTF_GN11_MASK (0x1000U)

#define	SEMA4_CPNTF_GN11_SHIFT (12U)

#define	SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)

#define	SEMA4_CPNTF_GN10_MASK (0x2000U)

#define	SEMA4_CPNTF_GN10_SHIFT (13U)

#define	SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)

#define	SEMA4_CPNTF_GN9_MASK (0x4000U)

#define	SEMA4_CPNTF_GN9_SHIFT (14U)

#define	SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)

#define	SEMA4_CPNTF_GN8_MASK (0x8000U)

#define	SEMA4_CPNTF_GN8_SHIFT (15U)

#define	SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)

RSTGT - Semaphores (Secure) Reset Gate n
#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)

#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)

#define	SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)

#define	SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)

#define	SEMA4_RSTGT_RSTGTN_SHIFT (8U)

#define	SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)

RSTNTF - Semaphores (Secure) Reset IRQ Notification
#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)

#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)

#define	SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)

#define	SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)

#define	SEMA4_RSTNTF_RSTNTN_SHIFT (8U)

#define	SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)

Detailed Description

Macro Definition Documentation

◆ SEMA4_CPINE_INE0 [1/2]

#define SEMA4_CPINE_INE0 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)

INE0 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE0 [2/2]

#define SEMA4_CPINE_INE0 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)

INE0 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE1 [1/2]

#define SEMA4_CPINE_INE1 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)

INE1 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE1 [2/2]

#define SEMA4_CPINE_INE1 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)

INE1 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE10 [1/2]

#define SEMA4_CPINE_INE10 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)

INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE10 [2/2]

#define SEMA4_CPINE_INE10 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)

INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 10. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE11 [1/2]

#define SEMA4_CPINE_INE11 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)

INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE11 [2/2]

#define SEMA4_CPINE_INE11 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)

INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 11. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE12 [1/2]

#define SEMA4_CPINE_INE12 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)

INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE12 [2/2]

#define SEMA4_CPINE_INE12 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)

INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 12. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE13 [1/2]

#define SEMA4_CPINE_INE13 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)

INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE13 [2/2]

#define SEMA4_CPINE_INE13 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)

INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 13. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE14 [1/2]

#define SEMA4_CPINE_INE14 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)

INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE14 [2/2]

#define SEMA4_CPINE_INE14 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)

INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 14. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE15 [1/2]

#define SEMA4_CPINE_INE15 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)

INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE15 [2/2]

#define SEMA4_CPINE_INE15 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)

INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 15. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE2 [1/2]

#define SEMA4_CPINE_INE2 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)

INE2 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE2 [2/2]

#define SEMA4_CPINE_INE2 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)

INE2 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE3 [1/2]

#define SEMA4_CPINE_INE3 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)

INE3 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE3 [2/2]

#define SEMA4_CPINE_INE3 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)

INE3 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE4 [1/2]

#define SEMA4_CPINE_INE4 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)

INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE4 [2/2]

#define SEMA4_CPINE_INE4 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)

INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 4. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE5 [1/2]

#define SEMA4_CPINE_INE5 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)

INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE5 [2/2]

#define SEMA4_CPINE_INE5 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)

INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 5. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE6 [1/2]

#define SEMA4_CPINE_INE6 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)

INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE6 [2/2]

#define SEMA4_CPINE_INE6 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)

INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 6. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE7 [1/2]

#define SEMA4_CPINE_INE7 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)

INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE7 [2/2]

#define SEMA4_CPINE_INE7 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)

INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 7. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE8 [1/2]

#define SEMA4_CPINE_INE8 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)

INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE8 [2/2]

#define SEMA4_CPINE_INE8 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)

INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 8. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE9 [1/2]

#define SEMA4_CPINE_INE9 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)

INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_CPINE_INE9 [2/2]

#define SEMA4_CPINE_INE9 ( x ) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)

INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation of an interrupt notification from a failed attempt to lock gate 9. 0b0..The generation of the notification interrupt is disabled. 0b1..The generation of the notification interrupt is enabled.

◆ SEMA4_GATE_GTFSM [1/2]

#define SEMA4_GATE_GTFSM ( x ) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)

GTFSM - Gate Finite State Machine. 0b00..The gate is unlocked (free). 0b01..The gate has been locked by processor 0. 0b10..The gate has been locked by processor 1. 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.

◆ SEMA4_GATE_GTFSM [2/2]

#define SEMA4_GATE_GTFSM ( x ) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)

GTFSM - Gate Finite State Machine. 0b00..The gate is unlocked (free). 0b01..The gate has been locked by processor 0. 0b10..The gate has been locked by processor 1. 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no operation" and do not affect the gate state machine.

Macros

GATE - Semaphores Gate n Register

CPINE - Semaphores Processor n IRQ Notification Enable

CPNTF - Semaphores Processor n IRQ Notification

RSTGT - Semaphores (Secure) Reset Gate n

RSTNTF - Semaphores (Secure) Reset IRQ Notification

GATE - Semaphores Gate n Register

CPINE - Semaphores Processor n IRQ Notification Enable

CPNTF - Semaphores Processor n IRQ Notification

RSTGT - Semaphores (Secure) Reset Gate n

RSTNTF - Semaphores (Secure) Reset IRQ Notification

Detailed Description

Macro Definition Documentation

◆ SEMA4_CPINE_INE0 [1/2]

◆ SEMA4_CPINE_INE0 [2/2]

◆ SEMA4_CPINE_INE1 [1/2]

◆ SEMA4_CPINE_INE1 [2/2]

◆ SEMA4_CPINE_INE10 [1/2]

◆ SEMA4_CPINE_INE10 [2/2]

◆ SEMA4_CPINE_INE11 [1/2]

◆ SEMA4_CPINE_INE11 [2/2]

◆ SEMA4_CPINE_INE12 [1/2]

◆ SEMA4_CPINE_INE12 [2/2]

◆ SEMA4_CPINE_INE13 [1/2]

◆ SEMA4_CPINE_INE13 [2/2]

◆ SEMA4_CPINE_INE14 [1/2]

◆ SEMA4_CPINE_INE14 [2/2]

◆ SEMA4_CPINE_INE15 [1/2]

◆ SEMA4_CPINE_INE15 [2/2]

◆ SEMA4_CPINE_INE2 [1/2]

◆ SEMA4_CPINE_INE2 [2/2]

◆ SEMA4_CPINE_INE3 [1/2]

◆ SEMA4_CPINE_INE3 [2/2]

◆ SEMA4_CPINE_INE4 [1/2]

◆ SEMA4_CPINE_INE4 [2/2]

◆ SEMA4_CPINE_INE5 [1/2]

◆ SEMA4_CPINE_INE5 [2/2]

◆ SEMA4_CPINE_INE6 [1/2]

◆ SEMA4_CPINE_INE6 [2/2]

◆ SEMA4_CPINE_INE7 [1/2]

◆ SEMA4_CPINE_INE7 [2/2]

◆ SEMA4_CPINE_INE8 [1/2]

◆ SEMA4_CPINE_INE8 [2/2]

◆ SEMA4_CPINE_INE9 [1/2]

◆ SEMA4_CPINE_INE9 [2/2]

◆ SEMA4_GATE_GTFSM [1/2]

◆ SEMA4_GATE_GTFSM [2/2]