RTEMS supports a software managed interrupt stack. The interrupt stacks are statically allocated by <rtems/confdefs.h> and the switch is performed by hardware or the interrupt processing code. These variables contain pointers to the lowest and highest addresses in the chunk of memory allocated for the interrupt stack. Since it is unknown whether the stack grows up or down (in general), this gives the CPU dependent code the option of picking the version it wants to use.

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The following defines the number of bits actually used in the interrupt field of the task mode. How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

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This defines the number of entries in the _ISR_Vector_table managed by RTEMS in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be a compile-time constant.

It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to FALSE.

This defines the highest interrupt vector number for this port in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be less than CPU_INTERRUPT_NUMBER_OF_VECTORS. It may be not a compile-time constant.

It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to FALSE.

This is defined if the port has a special way to report the ISR nesting level. Most ports maintain the variable _ISR_Nest_level.

Disable all interrupts for an RTEMS critical section. The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

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Enable interrupts to the previous level (returned by _CPU_ISR_Disable). This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

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This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

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This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

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Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

NOTE: This routine usually must be implemented as a subroutine.

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This routine installs a "raw" interrupt handler directly into the processor's vector table.

This routine is not used by architecture-independent code and thus optional.

Parameters

[in]	vector	is the vector number
[in]	new_handler	is the raw ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

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This routine installs an interrupt vector.

This routine is only used by architecture-independent code if CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE, otherwise it is optional.

Parameters

[in]	vector	is the vector number
[in]	new_handler	is the RTEMS ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

Port Specific Information:

XXX document implementation including references if appropriate